CN108735704A - 芯片封装方法 - Google Patents

芯片封装方法 Download PDF

Info

Publication number
CN108735704A
CN108735704A CN201710945294.9A CN201710945294A CN108735704A CN 108735704 A CN108735704 A CN 108735704A CN 201710945294 A CN201710945294 A CN 201710945294A CN 108735704 A CN108735704 A CN 108735704A
Authority
CN
China
Prior art keywords
layer
dielectric layer
redistribution layer
redistribution
temporary carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710945294.9A
Other languages
English (en)
Inventor
徐宏欣
林南君
张简上煜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Powertech Technology Inc
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Publication of CN108735704A publication Critical patent/CN108735704A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种芯片封装方法，包含于一第一暂时载体上形成一第一重布层及一第一介电层，从而产生多个第一导电介面于该第一暂时载体上，每对相邻的第一导电介面具有一第一间距；于该第一重布层的一第一部分及该第一介电层上形成一第二介电层，从而覆盖该第一重布层的该第一部分，及露出该第一重布层的一第二部分；于该第二介电层的上方形成一第二重布层及一第三介电层，从而产生多个第二导电介面及一电路，其中该电路至少由该第一重布层及该第二重布层形成。每对相邻的第二导电介面具有一第二间距，且该第二间距大于该第一间距。

Description

芯片封装方法
技术领域
本发明关于一种芯片封装方法，尤指一种使用暂时载体将多层结构平坦化的芯片封装方法。
背景技术
在先前技术，包含一组介电层及一组重布层的多层结构从底侧形成，在底侧，可形成具有较大间距的导电介面。举例来说，图1为先前技术中，具有较大间距的多个导电介面的封装结构100的示意图。在封装结构100中，芯片单元110可设置于多层结构120上。多层结构120可包含介电层120p1-120p2及两金属层120r1-120r2。通过图案化介电层120p1-120p2及金属层120r1-120r2，可设计及形成电路。芯片单元110可包含芯片100c、及一组焊凸块1101-1104，其用以存取芯片100c。
如图1所示，金属层120r2为被图案化以形成具有较小间距的多个导电介面1301-1304，金属层120r1为被图案化以形成具有较大间距的导电介面140。金属层120r1比金属层120r2更先被图案化。当载体在没有任何结构形成于其上之前，可为平坦状态，所以当第一层材料形成于载体上时，可不致发生翘曲问题的困扰，但当堆叠形成于载体上的层数增加时，会造成载体翘曲，且越加严重，因此，越后续形成的结构就越容易受到翘曲问题的干扰，从而有害于工艺良品率。
由于具有较小间距的导电介面1301-1304用以连接芯片单元110，导电介面1301-1304比导电介面140更为关键。然而，若金属层120r1及介电层120p1先被形成，则后续形成的导电介面1301-1304则不甚理想。如图1所示，导电介面1301及1304比导电介面1302及1303位置更高，这是因为介电层120p1-120p2及金属层120r1-120r2的分布，使介电层120p2的上表面不均匀所致。如图1所示，导电介面1301至1304的高度变化，
导致当设置芯片单元110于多层结构120上时，导电介面1302、1303无法接触对应的焊凸块1102、1103，故使封装结构100的良品率下降。
发明内容
本发明实施例提供一种芯片封装方法，包含：于一第一暂时载体上形成一第一重布层及一第一介电层，从而产生多个第一导电介面于该第一暂时载体上，每对相邻的第一导电介面具有一第一间距；于该第一重布层的一第一部分及该第一介电层上形成一第二介电层，从而覆盖该第一重布层的该第一部分，及露出该第一重布层的一第二部分；于该第二介电层的上方形成一第二重布层及一第三介电层，从而产生多个第二导电介面及一电路，其中该电路至少由该第一重布层及该第二重布层形成，每对相邻的第二导电介面具有一第二间距，且该第二间距大于该第一间距。
本发明的技术效果在于，本发明可形成平坦的平面，故当芯片被结合至多层结构时，所有的导电介面可被连接到芯片的焊点，从而可改善封装结构的良品率，且可使覆晶接合工艺有更大的调整范围。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为先前技术的封装结构的示意图。
图2至图7为实施例中，形成封装结构的工艺示意图。
图8为实施例中，形成封装结构的方法流程图。
图9为图8的实施例的细节步骤图。
图10为图8的实施例的细节步骤图。
附图标号：
100 封装结构
110 芯片单元
120、255 多层结构
120r1-120r2 金属层
120p1-120p2 介电层
1101-1104 焊凸块
100c 芯片
140 导电介面
20 封装结构
T1、T2 暂时载体
2101-2106 第一导电介面
2201-2204 第二导电介面
L1 第一间距
L2 第二间距
R1 第一重布层
R2 第二重布层
P1 第一介电层
A1 脱模层
255c 电路
S1 平面
R11 第一部分
R12 第二部分
510 芯片
5101-5106 导电凸块
5201-5206 焊点
530 底部填充层
610 模塑层
D 距离
7101-7104 焊球
800 方法
810-830、8101-8104、810a-810d 步骤
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域相关技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明的保护的范围。
图2至图7的实施例中，形成封装结构20的工艺示意图。封装结构20可见于图7。
图2中，可如下述形成多层结构255。于暂时载体T1上可形成第一重布层R1及第一介电层P1，从而产生多个第一导电介面2101-2106。第一导电介面2101-2106于暂时载体T1上实质上共平面。第一导电介面2101-2106中，两相邻的第一导电介面的距离可至少为第一间距L1。图2显示具有六个第一导电介面2101-2106，此仅为举例，并非用以限制本发明的范围。根据实施例，可在暂时载体T1及第一介电层P1形成的平面S1之间，形成脱模层A1。
于第一重布层R1及第一介电层P1上方可形成第二介电层P2。当形成第二介电层P2时，可于第一重布层R1及第一介电层P1上方形成一介电层，且移除该介电层中无用的部分，以图案化该介电层。第二介电层P2可覆盖第一重布层R1的第一部分R11，及露出第二部分R12。第二部分R12可填入导电材料，从而电连接第一重布层R1及另一重布层(例如图2所示的第二重布层R2)。
图2的实施例中，多层结构255可包含三层介电层P1-P3及两层重布层R1-R2，因此，第二重布层R2可为最上层的重布层，第三介电层P3可为最上层的介电层。然而，根据另一实施例，于暂时载体T1上形成的多层结构可包含更多介电层及重布层。举例而言，可用四层介电层及三层重布层形成多层结构。
图2中，第一重布层R1及第二重布层R2可形成电路255c，第二重布层R2及第三介电层P3可产生多个第二导电介面2201-2204。每对相邻的第二导电介面(例如2203及2204)之间的距离可至少为第二间距L2，且第二间距L2大于该第一间距。同理，图2的第二导电介面的数量为四个，此数量仅为举例。
如上述，多层结构255可包含比图2更多的介电层及重布层。举例而言，可于第二介电层P2及第三介电层P3之间另形成第四介电层，或更多介电层亦可，并可移除第四介电层的一部分，以图案化第四介电层。于第二重布层R2及第一重布层R1之间可形成第三重布层，或更多重布层亦可，并可移除第三重布层的一部分以图案化第三重布层。第三介电层P3的一部分亦可被移除，以图案化第三介电层P3。当多层结构255包含上述的第四介电层及第三重布层，电路255c可至少由第一重布层R1、第二重布层R2及第一重布层R1与第二重布层R2之间的第三重布层形成。同理，当多层结构255包含第四重布层，电路255c可由第一至第四重布层形成，以此类推。
图3中，暂时载体T2可被置放在第二重布层R2及第三介电层P3上，以当第一暂时载体T1被移除后支撑多层结构255。在暂时载体T2、第二重布层R2及第三介电层P3之间，可形成黏着层A2。黏着层A2可为黏着材料形成的涂层，或黏附薄膜。如图3所示，第二导电介面2201-2204可由图案化第三介电层P3以露出第二重布层R2的一部分而形成。使用具弹性的黏着层A2，可降低暂时载体T2与多层结构255之间的应力。
通过将多层结构255设置于暂时载体T1上，平面S1可为平坦表面。图4为导电介面2101-2106及2201-2204形成后，移除暂时载体T1的示意图。当移除暂时载体T1时，可将脱模层A1用特定的光线曝照、加热、或以适合的方式处理。
图5中，多层结构255可翻转，以使导电介面2101-2106朝上，且芯片510可对应电连接于导电介面2101-2106。根据实施例，多个焊点5201-5206可设置于导电介面2101-2106上，然后芯片510的多个导电凸块5101-5106可设置于焊点5201-5206上。根据另一实施例，焊点5201-5206的第一侧可设置于导电凸块5101-5106，且焊点5201-5206的第二侧可设置于导电介面2101-2106。另可将底部填充材料填充于焊点5201-5206周围以形成底部填充层530，以提高可靠度。
图6中，可填充模塑材料以形成模塑层610。模塑层610可包覆芯片510。图7中，暂时载体T2可被移除，多个焊球7101-7104可被设置于导电介面2201-2204上。相比于图6，图7中，包含多层结构255与模塑层610的结构可被翻转，使导电介面2201-2204朝上，以置放焊球7101-7104。根据实施例，模塑层610可被削薄以减少从芯片510到模塑层610的表面的距离D，以减低封装结构20的厚度。
根据实施例，图5的导电凸块5101-5106可为导电柱体凸块，例如铜柱体凸块。关于导电凸块5101-5106及焊点5201-5206所形成的凸块结构，每个凸块结构中，较厚部分可为铜柱体，中段部分可为镍，近似于球面的部分可为焊点。上述的重布层可用导电材料(例如铜)以电镀制造。上述的介电层如P1-P3，可用聚亚酰胺制造。形成介电层时，可使用光感应介电材料，以使介电层被图案化时，可用具有适当波长的光线曝照，且可执行显影(develop)工艺与固化(cure)工艺，以使图案化后的介电层可被固定。
根据实施例，前述的暂时载体T1及T2可用刚性材料制造，例如玻璃、陶瓷或硅等。如上述，靠近导电介面2201-2204的暂时载体T2可被选择性使用。因此，在一实施例中，当未使用暂时载体T2时，移除暂时载体T2的步骤可予以省略。
图8为实施例中，产生芯片结构20的芯片封装方法800的流程图。图2可对应于图8的步骤810-830。方法800可包含：
步骤810：于第一暂时载体T1上形成第一重布层R1及第一介电层P1，从而产生多个第一导电介面2101-2106于第一暂时载体T1上，每对相邻的第一导电介面具有第一间距L1；
步骤820：于第一重布层R1的第一部分R11及第一介电层P1上形成第二介电层P2，从而覆盖第一重布层R1的第一部分R11，及露出第一重布层R1的第二部分R12；及
步骤830：于第二介电层P2的上方形成第二重布层R2及第三介电层P3，从而产生多个第二导电介面2201-2204及电路255c，其中电路255c为至少由第一重布层R1及第二重布层R2形成，每对相邻的第二导电介面具有第二间距L2，且第二间距L2大于第一间距L1。
根据实施例，步骤810可包含下列的步骤8101-8104。图9可对应于步骤8101-8104，其包含：
步骤8101：于第一暂时载体T1上形成第一介电层P1；
步骤8102：移除第一介电层P1的一部分，从而图案化第一介电层P1；
步骤8103：于第一暂时载体T1及第一介电层P1上形成第一重布层R1，从而形成多个第一导电介面2101-2106；及
步骤8104：移除第一重布层R1的一部分，从而图案化第一重布层R1。
根据图9的实施例，可于形成及图案化第一重布层R1之前，先形成及图案化第一介电层P1。
根据另一实施例，步骤810可包含下列步骤810a-810d。图10为图8的步骤810包含的步骤810a-810d的流程图，其包含：
步骤810a：于第一暂时载体T1上形成第一重布层R1；
步骤810b：移除第一重布层R1的一部分，从而图案化第一重布层R1，以形成多个第一导电介面2101-2106；
步骤810c：于第一暂时载体T1及第一重布层R1的剩余部分上形成第一介电层P1；及
步骤810d：移除第一介电层P1的一部分，从而图案化第一介电层P1。
根据图10的实施例，可先形成及图案化第一重布层R1，再形成及图案化第一介电层P1。
综上，根据实施例，本发明可形成平坦的平面S1，故当芯片510被结合至多层结构255时，所有的导电介面2101-2106可被连接到芯片510的焊点5201-5206，从而可改善封装结构20的良品率，且可使覆晶接合工艺有更大的调整范围。
以上所述仅为本发明的较佳实施例，凡依本发明申请专利范围所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (10)

1.一种芯片封装方法，其特征在于，包含：
于一第一暂时载体上形成一第一重布层及一第一介电层，从而产生多个第一导电介面于该第一暂时载体上，每对相邻的第一导电介面具有一第一间距；
于该第一重布层的一第一部分及该第一介电层上形成一第二介电层，从而覆盖该第一重布层的该第一部分，及露出该第一重布层的一第二部分；
于该第二介电层的上方形成一第二重布层及一第三介电层，从而产生多个第二导电介面及一电路，其中该电路至少由该第一重布层及该第二重布层形成，每对相邻的第二导电介面具有一第二间距，且该第二间距大于该第一间距。
2.如权利要求1所述的芯片封装方法，其特征在于，于该第一暂时载体上形成该第一重布层及该第一介电层，包含：
于该第一暂时载体上形成该第一介电层；
移除该第一介电层的一部分，从而图案化该第一介电层；
于该第一暂时载体及该第一介电层上形成该第一重布层，从而形成该多个第一导电介面；及
移除该第一重布层的一部分，从而图案化该第一重布层。
3.如权利要求1所述的芯片封装方法，其特征在于，于该第一暂时载体上形成该第一重布层及该第一介电层，包含：
于该第一暂时载体上形成该第一重布层；
移除该第一重布层的一部分，从而图案化该第一重布层，以形成该多个第一导电介面；
于该第一暂时载体及该第一重布层的一剩余部分上形成该第一介电层；及
移除该第一介电层的一部分，从而图案化该第一介电层。
4.如权利要求1所述的芯片封装方法，其特征在于，另包含：
于该第二介电层及该第三介电层之间形成一第四介电层；
移除该第四介电层的一部分，从而图案化该第四介电层；
于该第二重布层及该第一重布层之间形成一第三重布层；及
移除该第三重布层的一部分以图案化该第三重布层；
其中该电路至少由该第一重布层、该第二重布层及该第三重布层形成。
5.如权利要求1所述的芯片封装方法，其特征在于，另包含：
于该第二重布层及该第三介电层上置放一第二暂时载体，从而当该第一暂时载体被移除后，支撑该第一重布层、该第二重布层、及该第一介电层至该第三介电层。
6.如权利要求5所述的芯片封装方法，其特征在于，另包含：
移除该第一暂时载体；
翻转具有该第一介电层、该第一重布层、该第二介电层、该第二重布层及该第三介电层的一多层结构，从而使该多个第一导电介面朝向上方；及
将一芯片接附于该多个第一导电介面上。
7.如权利要求6所述的芯片封装方法，其特征在于，将该芯片接附于该多个第一导电介面上，包含：
于该多个第一导电介面上设置该芯片的多个第一焊点；
其中每个第一焊点为该芯片的一导电凸块的一部分。
8.如权利要求7所述的芯片封装方法，其特征在于，将该芯片接附于该多个第一导电介面上，另包含：
将一底部填充材料填充于该芯片的该导电凸块周围以形成一底部填充层。
9.如权利要求6所述的芯片封装方法，其特征在于，另包含：
填充一模塑材料以形成一模塑层，该模塑层包覆该芯片。
10.如权利要求6所述的芯片封装方法，其特征在于，另包含：
移除该第二暂时载体；及
于该多个第二导电介面上设置多个焊球。
CN201710945294.9A 2017-04-13 2017-10-12 芯片封装方法 Pending CN108735704A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762484907P 2017-04-13 2017-04-13
US62/484,907 2017-04-13
US15/603,475 2017-05-24
US15/603,475 US10177011B2 (en) 2017-04-13 2017-05-24 Chip packaging method by using a temporary carrier for flattening a multi-layer structure

Publications (1)

Publication Number Publication Date
CN108735704A true CN108735704A (zh) 2018-11-02

Family

ID=63790235

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710945294.9A Pending CN108735704A (zh) 2017-04-13 2017-10-12 芯片封装方法

Country Status (3)

Country Link
US (2) US10177011B2 (zh)
CN (1) CN108735704A (zh)
TW (2) TWI660435B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110729270A (zh) * 2019-03-04 2020-01-24 Pep创新私人有限公司 芯片封装方法及封装结构
US11488906B2 (en) * 2019-01-24 2022-11-01 Samsung Electro-Mechanics Co., Ltd. Bridge embedded interposer, and package substrate and semiconductor package comprising the same
JP2020155596A (ja) * 2019-03-20 2020-09-24 キオクシア株式会社 半導体装置
US11251170B2 (en) * 2019-04-29 2022-02-15 Powertech Technology Inc. Package structure and manufacturing method thereof
US11251099B2 (en) * 2019-07-31 2022-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control of packages using embedded core frame
US11296051B2 (en) * 2019-08-22 2022-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and forming method thereof
US11282772B2 (en) * 2019-11-06 2022-03-22 Advanced Semiconductor Engineering, Inc. Package structure, assembly structure and method for manufacturing the same
TWI733569B (zh) * 2020-08-27 2021-07-11 矽品精密工業股份有限公司 電子封裝件及其製法
CN115148712A (zh) * 2021-03-29 2022-10-04 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
US11705406B2 (en) * 2021-06-17 2023-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for forming the same
CN113471160A (zh) * 2021-06-29 2021-10-01 矽磐微电子(重庆)有限公司 芯片封装结构及其制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681613A (zh) * 2012-09-10 2014-03-26 台湾积体电路制造股份有限公司 具有离散块的半导体器件
US20150011051A1 (en) * 2010-05-18 2015-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package Systems Having Interposers
US20170011934A1 (en) * 2015-07-10 2017-01-12 Dyi-chung Hu Fabricating process for redistribution layer

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6423570B1 (en) * 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
CA2464078C (en) * 2002-08-09 2010-01-26 Casio Computer Co., Ltd. Semiconductor device and method of manufacturing the same
US7547969B2 (en) * 2004-10-29 2009-06-16 Megica Corporation Semiconductor chip with passivation layer comprising metal interconnect and contact pads
KR101767108B1 (ko) * 2010-12-15 2017-08-11 삼성전자주식회사 하이브리드 기판을 구비하는 반도체 패키지 및 그 제조방법
US9704824B2 (en) * 2013-01-03 2017-07-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded wafer level chip scale packages
US9035461B2 (en) * 2013-01-30 2015-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging methods
US9406588B2 (en) * 2013-11-11 2016-08-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method thereof
US9704769B2 (en) * 2014-02-27 2017-07-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming encapsulated wafer level chip scale package (EWLCSP)
US20160190056A1 (en) * 2014-12-29 2016-06-30 SooSan Park Integrated circuit packaging system with package-on-package mechanism and method of manufacture thereof
KR101731700B1 (ko) * 2015-03-18 2017-04-28 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9520333B1 (en) * 2015-06-22 2016-12-13 Inotera Memories, Inc. Wafer level package and fabrication method thereof
US9793231B2 (en) * 2015-06-30 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Under bump metallurgy (UBM) and methods of forming same
CN105304507B (zh) * 2015-11-06 2018-07-31 通富微电子股份有限公司 扇出晶圆级封装方法
CN105390471B (zh) * 2015-11-06 2018-06-12 通富微电子股份有限公司 扇出晶圆级封装结构
US10177114B2 (en) * 2015-11-25 2019-01-08 Invensas Corporation Hybrid 3D/2.5D interposer
JP6566879B2 (ja) * 2016-01-28 2019-08-28 新光電気工業株式会社 電子部品内蔵基板
US9997471B2 (en) * 2016-07-25 2018-06-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof
US20180166426A1 (en) * 2016-12-14 2018-06-14 Nanya Technology Corporation Semiconductor structure and a manufacturing method thereof
US10181455B2 (en) * 2017-01-17 2019-01-15 Apple Inc. 3D thin profile pre-stacking architecture using reconstitution method
US10381301B2 (en) * 2017-02-08 2019-08-13 Micro Technology, Inc. Semiconductor package and method for fabricating the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150011051A1 (en) * 2010-05-18 2015-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package Systems Having Interposers
CN103681613A (zh) * 2012-09-10 2014-03-26 台湾积体电路制造股份有限公司 具有离散块的半导体器件
US20170011934A1 (en) * 2015-07-10 2017-01-12 Dyi-chung Hu Fabricating process for redistribution layer

Also Published As

Publication number Publication date
TWI660435B (zh) 2019-05-21
US20180301418A1 (en) 2018-10-18
TW201903992A (zh) 2019-01-16
US10177011B2 (en) 2019-01-08
US20180301352A1 (en) 2018-10-18
TWI662667B (zh) 2019-06-11
TW201842593A (zh) 2018-12-01

Similar Documents

Publication Publication Date Title
CN108735704A (zh) 芯片封装方法
KR20180121893A (ko) 내장형 실리콘 기판의 팬 아웃 3d 패키지 구조
TWI536519B (zh) 半導體封裝結構以及其製造方法
TWI556400B (zh) 堆疊式扇出半導體晶片
CN102468257B (zh) 晶圆级半导体封装件及其制造方法
TWI401753B (zh) 可堆疊式封裝結構之製造方法
US20140057394A1 (en) Method for making a double-sided fanout semiconductor package with embedded surface mount devices, and product made
US9698072B2 (en) Low-stress dual underfill packaging
TWI447864B (zh) 封裝基板及其製法
CN109904083A (zh) 用于晶片级管芯桥的方法和设备
KR101750713B1 (ko) 마이크로스프링 접점을 갖는 인터포저 및 그 제조 및 사용 방법
TW201810443A (zh) 連接電子組件至基板
US11239185B2 (en) Embedded resistor-capacitor film for fan out wafer level packaging
US9132494B2 (en) Wiring board and method for manufacturing the same
TW201349397A (zh) 半導體封裝結構之多層基板
JP2014017485A (ja) ダイおよび基板を接続する剛性相互接続構造を有するデバイスパッケージならびにその方法
CN206040641U (zh) 半导体装置
CN109300882A (zh) 堆叠嵌入式封装结构及其制作方法
JP2013219228A (ja) 配線基板の製造方法及び配線基板
CN107785325A (zh) 半导体封装及其制造方法
CN103378041A (zh) 迹线上凸块芯片封装的方法和装置
CN109427700A (zh) 集成电路封装及其制作方法
TWI788189B (zh) 半導體封裝及其製造方法
CN205488088U (zh) 埋入硅基板扇出型3d封装结构
CN108598046A (zh) 芯片的封装结构及其封装方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20181102