CN108735704A - 芯片封装方法 - Google Patents
芯片封装方法 Download PDFInfo
- Publication number
- CN108735704A CN108735704A CN201710945294.9A CN201710945294A CN108735704A CN 108735704 A CN108735704 A CN 108735704A CN 201710945294 A CN201710945294 A CN 201710945294A CN 108735704 A CN108735704 A CN 108735704A
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- Prior art keywords
- layer
- dielectric layer
- redistribution layer
- redistribution
- temporary carrier
- Prior art date
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- Pending
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 17
- 229910000679 solder Inorganic materials 0.000 claims description 12
- 238000000465 moulding Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 5
- 239000004744 fabric Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 238000000059 patterning Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
Classifications
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract
一种芯片封装方法,包含于一第一暂时载体上形成一第一重布层及一第一介电层,从而产生多个第一导电介面于该第一暂时载体上,每对相邻的第一导电介面具有一第一间距;于该第一重布层的一第一部分及该第一介电层上形成一第二介电层,从而覆盖该第一重布层的该第一部分,及露出该第一重布层的一第二部分;于该第二介电层的上方形成一第二重布层及一第三介电层,从而产生多个第二导电介面及一电路,其中该电路至少由该第一重布层及该第二重布层形成。每对相邻的第二导电介面具有一第二间距,且该第二间距大于该第一间距。
Description
技术领域
本发明关于一种芯片封装方法,尤指一种使用暂时载体将多层结构平坦化的芯片封装方法。
背景技术
在先前技术,包含一组介电层及一组重布层的多层结构从底侧形成,在底侧,可形成具有较大间距的导电介面。举例来说,图1为先前技术中,具有较大间距的多个导电介面的封装结构100的示意图。在封装结构100中,芯片单元110可设置于多层结构120上。多层结构120可包含介电层120p1-120p2及两金属层120r1-120r2。通过图案化介电层120p1-120p2及金属层120r1-120r2,可设计及形成电路。芯片单元110可包含芯片100c、及一组焊凸块1101-1104,其用以存取芯片100c。
如图1所示,金属层120r2为被图案化以形成具有较小间距的多个导电介面1301-1304,金属层120r1为被图案化以形成具有较大间距的导电介面140。金属层120r1比金属层120r2更先被图案化。当载体在没有任何结构形成于其上之前,可为平坦状态,所以当第一层材料形成于载体上时,可不致发生翘曲问题的困扰,但当堆叠形成于载体上的层数增加时,会造成载体翘曲,且越加严重,因此,越后续形成的结构就越容易受到翘曲问题的干扰,从而有害于工艺良品率。
由于具有较小间距的导电介面1301-1304用以连接芯片单元110,导电介面1301-1304比导电介面140更为关键。然而,若金属层120r1及介电层120p1先被形成,则后续形成的导电介面1301-1304则不甚理想。如图1所示,导电介面1301及1304比导电介面1302及1303位置更高,这是因为介电层120p1-120p2及金属层120r1-120r2的分布,使介电层120p2的上表面不均匀所致。如图1所示,导电介面1301至1304的高度变化,
导致当设置芯片单元110于多层结构120上时,导电介面1302、1303无法接触对应的焊凸块1102、1103,故使封装结构100的良品率下降。
发明内容
本发明实施例提供一种芯片封装方法,包含:于一第一暂时载体上形成一第一重布层及一第一介电层,从而产生多个第一导电介面于该第一暂时载体上,每对相邻的第一导电介面具有一第一间距;于该第一重布层的一第一部分及该第一介电层上形成一第二介电层,从而覆盖该第一重布层的该第一部分,及露出该第一重布层的一第二部分;于该第二介电层的上方形成一第二重布层及一第三介电层,从而产生多个第二导电介面及一电路,其中该电路至少由该第一重布层及该第二重布层形成,每对相邻的第二导电介面具有一第二间距,且该第二间距大于该第一间距。
本发明的技术效果在于,本发明可形成平坦的平面,故当芯片被结合至多层结构时,所有的导电介面可被连接到芯片的焊点,从而可改善封装结构的良品率,且可使覆晶接合工艺有更大的调整范围。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。
图1为先前技术的封装结构的示意图。
图2至图7为实施例中,形成封装结构的工艺示意图。
图8为实施例中,形成封装结构的方法流程图。
图9为图8的实施例的细节步骤图。
图10为图8的实施例的细节步骤图。
附图标号:
100 封装结构
110 芯片单元
120、255 多层结构
120r1-120r2 金属层
120p1-120p2 介电层
1101-1104 焊凸块
100c 芯片
140 导电介面
20 封装结构
T1、T2 暂时载体
2101-2106 第一导电介面
2201-2204 第二导电介面
L1 第一间距
L2 第二间距
R1 第一重布层
R2 第二重布层
P1 第一介电层
A1 脱模层
255c 电路
S1 平面
R11 第一部分
R12 第二部分
510 芯片
5101-5106 导电凸块
5201-5206 焊点
530 底部填充层
610 模塑层
D 距离
7101-7104 焊球
800 方法
810-830、8101-8104、810a-810d 步骤
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域相关技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明的保护的范围。
图2至图7的实施例中,形成封装结构20的工艺示意图。封装结构20可见于图7。
图2中,可如下述形成多层结构255。于暂时载体T1上可形成第一重布层R1及第一介电层P1,从而产生多个第一导电介面2101-2106。第一导电介面2101-2106于暂时载体T1上实质上共平面。第一导电介面2101-2106中,两相邻的第一导电介面的距离可至少为第一间距L1。图2显示具有六个第一导电介面2101-2106,此仅为举例,并非用以限制本发明的范围。根据实施例,可在暂时载体T1及第一介电层P1形成的平面S1之间,形成脱模层A1。
于第一重布层R1及第一介电层P1上方可形成第二介电层P2。当形成第二介电层P2时,可于第一重布层R1及第一介电层P1上方形成一介电层,且移除该介电层中无用的部分,以图案化该介电层。第二介电层P2可覆盖第一重布层R1的第一部分R11,及露出第二部分R12。第二部分R12可填入导电材料,从而电连接第一重布层R1及另一重布层(例如图2所示的第二重布层R2)。
图2的实施例中,多层结构255可包含三层介电层P1-P3及两层重布层R1-R2,因此,第二重布层R2可为最上层的重布层,第三介电层P3可为最上层的介电层。然而,根据另一实施例,于暂时载体T1上形成的多层结构可包含更多介电层及重布层。举例而言,可用四层介电层及三层重布层形成多层结构。
图2中,第一重布层R1及第二重布层R2可形成电路255c,第二重布层R2及第三介电层P3可产生多个第二导电介面2201-2204。每对相邻的第二导电介面(例如2203及2204)之间的距离可至少为第二间距L2,且第二间距L2大于该第一间距。同理,图2的第二导电介面的数量为四个,此数量仅为举例。
如上述,多层结构255可包含比图2更多的介电层及重布层。举例而言,可于第二介电层P2及第三介电层P3之间另形成第四介电层,或更多介电层亦可,并可移除第四介电层的一部分,以图案化第四介电层。于第二重布层R2及第一重布层R1之间可形成第三重布层,或更多重布层亦可,并可移除第三重布层的一部分以图案化第三重布层。第三介电层P3的一部分亦可被移除,以图案化第三介电层P3。当多层结构255包含上述的第四介电层及第三重布层,电路255c可至少由第一重布层R1、第二重布层R2及第一重布层R1与第二重布层R2之间的第三重布层形成。同理,当多层结构255包含第四重布层,电路255c可由第一至第四重布层形成,以此类推。
图3中,暂时载体T2可被置放在第二重布层R2及第三介电层P3上,以当第一暂时载体T1被移除后支撑多层结构255。在暂时载体T2、第二重布层R2及第三介电层P3之间,可形成黏着层A2。黏着层A2可为黏着材料形成的涂层,或黏附薄膜。如图3所示,第二导电介面2201-2204可由图案化第三介电层P3以露出第二重布层R2的一部分而形成。使用具弹性的黏着层A2,可降低暂时载体T2与多层结构255之间的应力。
通过将多层结构255设置于暂时载体T1上,平面S1可为平坦表面。图4为导电介面2101-2106及2201-2204形成后,移除暂时载体T1的示意图。当移除暂时载体T1时,可将脱模层A1用特定的光线曝照、加热、或以适合的方式处理。
图5中,多层结构255可翻转,以使导电介面2101-2106朝上,且芯片510可对应电连接于导电介面2101-2106。根据实施例,多个焊点5201-5206可设置于导电介面2101-2106上,然后芯片510的多个导电凸块5101-5106可设置于焊点5201-5206上。根据另一实施例,焊点5201-5206的第一侧可设置于导电凸块5101-5106,且焊点5201-5206的第二侧可设置于导电介面2101-2106。另可将底部填充材料填充于焊点5201-5206周围以形成底部填充层530,以提高可靠度。
图6中,可填充模塑材料以形成模塑层610。模塑层610可包覆芯片510。图7中,暂时载体T2可被移除,多个焊球7101-7104可被设置于导电介面2201-2204上。相比于图6,图7中,包含多层结构255与模塑层610的结构可被翻转,使导电介面2201-2204朝上,以置放焊球7101-7104。根据实施例,模塑层610可被削薄以减少从芯片510到模塑层610的表面的距离D,以减低封装结构20的厚度。
根据实施例,图5的导电凸块5101-5106可为导电柱体凸块,例如铜柱体凸块。关于导电凸块5101-5106及焊点5201-5206所形成的凸块结构,每个凸块结构中,较厚部分可为铜柱体,中段部分可为镍,近似于球面的部分可为焊点。上述的重布层可用导电材料(例如铜)以电镀制造。上述的介电层如P1-P3,可用聚亚酰胺制造。形成介电层时,可使用光感应介电材料,以使介电层被图案化时,可用具有适当波长的光线曝照,且可执行显影(develop)工艺与固化(cure)工艺,以使图案化后的介电层可被固定。
根据实施例,前述的暂时载体T1及T2可用刚性材料制造,例如玻璃、陶瓷或硅等。如上述,靠近导电介面2201-2204的暂时载体T2可被选择性使用。因此,在一实施例中,当未使用暂时载体T2时,移除暂时载体T2的步骤可予以省略。
图8为实施例中,产生芯片结构20的芯片封装方法800的流程图。图2可对应于图8的步骤810-830。方法800可包含:
步骤810:于第一暂时载体T1上形成第一重布层R1及第一介电层P1,从而产生多个第一导电介面2101-2106于第一暂时载体T1上,每对相邻的第一导电介面具有第一间距L1;
步骤820:于第一重布层R1的第一部分R11及第一介电层P1上形成第二介电层P2,从而覆盖第一重布层R1的第一部分R11,及露出第一重布层R1的第二部分R12;及
步骤830:于第二介电层P2的上方形成第二重布层R2及第三介电层P3,从而产生多个第二导电介面2201-2204及电路255c,其中电路255c为至少由第一重布层R1及第二重布层R2形成,每对相邻的第二导电介面具有第二间距L2,且第二间距L2大于第一间距L1。
根据实施例,步骤810可包含下列的步骤8101-8104。图9可对应于步骤8101-8104,其包含:
步骤8101:于第一暂时载体T1上形成第一介电层P1;
步骤8102:移除第一介电层P1的一部分,从而图案化第一介电层P1;
步骤8103:于第一暂时载体T1及第一介电层P1上形成第一重布层R1,从而形成多个第一导电介面2101-2106;及
步骤8104:移除第一重布层R1的一部分,从而图案化第一重布层R1。
根据图9的实施例,可于形成及图案化第一重布层R1之前,先形成及图案化第一介电层P1。
根据另一实施例,步骤810可包含下列步骤810a-810d。图10为图8的步骤810包含的步骤810a-810d的流程图,其包含:
步骤810a:于第一暂时载体T1上形成第一重布层R1;
步骤810b:移除第一重布层R1的一部分,从而图案化第一重布层R1,以形成多个第一导电介面2101-2106;
步骤810c:于第一暂时载体T1及第一重布层R1的剩余部分上形成第一介电层P1;及
步骤810d:移除第一介电层P1的一部分,从而图案化第一介电层P1。
根据图10的实施例,可先形成及图案化第一重布层R1,再形成及图案化第一介电层P1。
综上,根据实施例,本发明可形成平坦的平面S1,故当芯片510被结合至多层结构255时,所有的导电介面2101-2106可被连接到芯片510的焊点5201-5206,从而可改善封装结构20的良品率,且可使覆晶接合工艺有更大的调整范围。
以上所述仅为本发明的较佳实施例,凡依本发明申请专利范围所做的均等变化与修饰,皆应属本发明的涵盖范围。
Claims (10)
1.一种芯片封装方法,其特征在于,包含:
于一第一暂时载体上形成一第一重布层及一第一介电层,从而产生多个第一导电介面于该第一暂时载体上,每对相邻的第一导电介面具有一第一间距;
于该第一重布层的一第一部分及该第一介电层上形成一第二介电层,从而覆盖该第一重布层的该第一部分,及露出该第一重布层的一第二部分;
于该第二介电层的上方形成一第二重布层及一第三介电层,从而产生多个第二导电介面及一电路,其中该电路至少由该第一重布层及该第二重布层形成,每对相邻的第二导电介面具有一第二间距,且该第二间距大于该第一间距。
2.如权利要求1所述的芯片封装方法,其特征在于,于该第一暂时载体上形成该第一重布层及该第一介电层,包含:
于该第一暂时载体上形成该第一介电层;
移除该第一介电层的一部分,从而图案化该第一介电层;
于该第一暂时载体及该第一介电层上形成该第一重布层,从而形成该多个第一导电介面;及
移除该第一重布层的一部分,从而图案化该第一重布层。
3.如权利要求1所述的芯片封装方法,其特征在于,于该第一暂时载体上形成该第一重布层及该第一介电层,包含:
于该第一暂时载体上形成该第一重布层;
移除该第一重布层的一部分,从而图案化该第一重布层,以形成该多个第一导电介面;
于该第一暂时载体及该第一重布层的一剩余部分上形成该第一介电层;及
移除该第一介电层的一部分,从而图案化该第一介电层。
4.如权利要求1所述的芯片封装方法,其特征在于,另包含:
于该第二介电层及该第三介电层之间形成一第四介电层;
移除该第四介电层的一部分,从而图案化该第四介电层;
于该第二重布层及该第一重布层之间形成一第三重布层;及
移除该第三重布层的一部分以图案化该第三重布层;
其中该电路至少由该第一重布层、该第二重布层及该第三重布层形成。
5.如权利要求1所述的芯片封装方法,其特征在于,另包含:
于该第二重布层及该第三介电层上置放一第二暂时载体,从而当该第一暂时载体被移除后,支撑该第一重布层、该第二重布层、及该第一介电层至该第三介电层。
6.如权利要求5所述的芯片封装方法,其特征在于,另包含:
移除该第一暂时载体;
翻转具有该第一介电层、该第一重布层、该第二介电层、该第二重布层及该第三介电层的一多层结构,从而使该多个第一导电介面朝向上方;及
将一芯片接附于该多个第一导电介面上。
7.如权利要求6所述的芯片封装方法,其特征在于,将该芯片接附于该多个第一导电介面上,包含:
于该多个第一导电介面上设置该芯片的多个第一焊点;
其中每个第一焊点为该芯片的一导电凸块的一部分。
8.如权利要求7所述的芯片封装方法,其特征在于,将该芯片接附于该多个第一导电介面上,另包含:
将一底部填充材料填充于该芯片的该导电凸块周围以形成一底部填充层。
9.如权利要求6所述的芯片封装方法,其特征在于,另包含:
填充一模塑材料以形成一模塑层,该模塑层包覆该芯片。
10.如权利要求6所述的芯片封装方法,其特征在于,另包含:
移除该第二暂时载体;及
于该多个第二导电介面上设置多个焊球。
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