CN107785325A - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

Info

Publication number
CN107785325A
CN107785325A CN201611022516.1A CN201611022516A CN107785325A CN 107785325 A CN107785325 A CN 107785325A CN 201611022516 A CN201611022516 A CN 201611022516A CN 107785325 A CN107785325 A CN 107785325A
Authority
CN
China
Prior art keywords
chip
active surface
primer
semiconductor packages
bonding area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201611022516.1A
Other languages
English (en)
Inventor
沈更新
凃清镇
吴自胜
林俊辰
叶惠雯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chipmos Technologies Inc
Original Assignee
Chipmos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Publication of CN107785325A publication Critical patent/CN107785325A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391—Forming a passivation layer after forming the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/06102—Disposition the bonding areas being at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/14155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705—Shape
    • H01L2224/17051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26122—Auxiliary members for layer connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/26145—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H01L2224/32058—Shape in side view being non uniform along the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本发明提供一种半导体封装及其制造方法，其中半导体封装，包括第一、第二芯片、多个第一、第二导电凸块及底胶。第一芯片包括一第一主动面，其中第一主动面包括一芯片接合区、多个位于芯片接合区内的第一内接点以及多个位于芯片接合区外的第一外接点。第二芯片倒装于第一芯片的芯片接合区处。第一导电凸块配置于第一外接点上。第二导电凸块位于第一芯片的第一内接点与第二芯片的第二接点之间。底胶位在第一主动面上且包覆第二导电凸块、至少局部的各第二芯片侧面及至少局部的各第一导电凸块。本发明还提供多种半导体封装的制造方法。本发明提供的半导体封装，具有较低的破裂率。

Description

半导体封装及其制造方法
技术领域
本发明涉及一种封装及其制造方法，尤其涉及一种半导体封装及其制造方法。
背景技术
随着科技发展的日新月异，集成电路(integrated circuits，IC)元件已广泛地应用于我们日常生活当中。一般而言，集成电路的生产主要分为三个阶段：硅晶圆的制造、集成电路的制作及集成电路的封装。
在目前的封装结构中，将小尺寸的芯片以芯片倒装的方式配置于大尺寸的芯片上并通过两者之间的导电凸柱电性连接是一种相当常见的封装型态。然而，在目前的多芯片封装中，小尺寸的芯片的侧面裸露，晶背也常是裸露的，而使得多芯片封装中小尺寸芯片的破裂率(chipping rate)较高。
发明内容
本发明提供一种半导体封装，其具有较低的破裂率。
本发明提供多种半导体封装的制造方法，其可制造出上述的半导体封装。
本发明的一种半导体封装，包括第一芯片、第二芯片、多个第一导电凸块、多个第二导电凸块及底胶。第一芯片包括第一主动面，其中第一主动面包括芯片接合区、多个位于芯片接合区内的第一内接点以及多个位于芯片接合区外的第一外接点。第二芯片倒装于(flip on)第一芯片的芯片接合区处，且包括第二主动面及连接于第二主动面的多个第二芯片侧面，其中第二主动面包括多个第二接点。这些第一导电凸块配置于这些第一外接点上。这些第二导电凸块位于这些第一内接点与这些第二接点之间，各第一内接点分别通过对应的第二导电凸块与对应的第二接点电性连接。底胶位在第一主动面上且包覆这些第二导电凸块、至少局部的各第二芯片侧面及至少局部的各第一导电凸块。
在本发明的一实施例中，上述的底胶包括封模底胶(molded underfill，MUF)，封模底胶包覆全部的这些第二芯片侧面。
在本发明的一实施例中，上述的第二芯片还包括相对于第二主动面的晶背，晶背被封模底胶覆盖，或者晶背外露于封模底胶。
在本发明的一实施例中，上述的半导体封装还包括多个焊件，这些第一导电凸块外露于封模底胶，这些焊件配置于封模底胶上且连接于这些第一导电凸块，其中各焊件包括焊球、焊帽或焊层。
在本发明的一实施例中，上述的这些第一导电凸块的高度大于或等于第二芯片的晶背至第一内接点之间的距离。
在本发明的一实施例中，上述的半导体封装还包括多个焊球及保护层，这些焊球配置于这些第一导电凸块上，各第一导电凸块为球底金属层(UBM)，封模底胶包覆局部的各焊球。保护层配置于第一芯片的第一主动面上，保护层包括至少对应于芯片接合区的一开口，且这些第一内接点与这些第一外接点外露于保护层。
在本发明的一实施例中，上述的第二芯片还包括相对于第二主动面的晶背，第二芯片的晶背至第一内接点之间的距离大于各第一导电凸块的高度，且各第一导电凸块的高度大于各第二导电凸块的高度。
在本发明的一实施例中，上述的各焊球凸出于封模底胶的高度为焊球的高度的0.5倍至0.8倍之间。
在本发明的一实施例中，上述的半导体封装还包括一保护层，配置于第一芯片的第一主动面上，这些第一内接点与这些第一外接点外露于保护层，保护层包括对应于芯片接合区的一开口，底胶包括一内底胶，内底胶位在第一芯片的芯片接合区与第二芯片之间，封模底胶包覆内底胶。
在本发明的一实施例中，上述的半导体封装还包括保护层，配置于第一芯片的第一主动面上的这些第一外接点所环绕的虚拟范围以外的区域，底胶包覆第二芯片的局部的各第二芯片侧面及局部的这些第一导电凸块，各第一导电凸块为焊球。
本发明的一种半导体封装的制造方法，包括：提供晶圆，包括阵列排列的多个第一芯片，其中各第一芯片包括第一主动面，第一主动面包括芯片接合区、多个位于芯片接合区内的第一内接点以及多个位于芯片接合区外的第一外接点；配置多个第一导电凸块于这些第一外接点上；倒装多个第二芯片于这些第一芯片的这些芯片接合区，其中各第二芯片包括第二主动面及连接于第二主动面的多个第二芯片侧面，各第二主动面包括多个第二接点，各第二主动面面对第一主动面且这些第二接点电性连接于这些第一内接点；进行模制(molding)底胶工艺，以在第一主动面上形成封模底胶，其中封模底胶包覆这些第一导电凸块及这些第二芯片；对封模底胶进行研磨工艺，而使这些第一导电凸块外露；配置多个焊件于这些第一导电凸块上以形成多个半导体封装；以及进行切割工艺，以使这些半导体封装彼此分离。
在本发明的一实施例中，上述的各焊件包括焊球、焊帽或焊层。
在本发明的一实施例中，上述的第二芯片还包括相对于第二主动面的晶背，在对封模底胶进行研磨工艺的步骤之后，晶背外露于封模底胶。
在本发明的一实施例中，在倒装这些第二芯片之后且进行模制底胶工艺之前，还包括：配置保护层于第一芯片的第一主动面上，这些第一内接点与这些第一外接点外露于保护层，保护层包括对应于芯片接合区的开口；以及配置内底胶于第一芯片的芯片接合区与第二芯片之间，其中在进行模制底胶工艺之后，封模底胶包覆内底胶。
本发明的一种半导体封装的制造方法，包括：提供晶圆，包括阵列排列的多个第一芯片，其中各第一芯片包括第一主动面，第一主动面包括芯片接合区、多个位于芯片接合区内的第一内接点以及多个位于芯片接合区外的第一外接点，第一主动面上配置有保护层，保护层包括至少对应于芯片接合区的开口，且这些第一内接点与这些第一外接点外露于保护层；配置多个焊球于这些第一外接点上以与这些第一外接点电性连接；倒装多个第二芯片于这些第一芯片的这些芯片接合区，其中各第二芯片包括第二主动面及连接于第二主动面的多个第二芯片侧面，各第二主动面包括多个第二接点，各第二主动面面对第一主动面且这些第二接点电性连接于这些第一内接点；进行模制(molding)底胶工艺，在第一主动面上形成封模底胶，其中封模底胶包覆这些第二芯片及局部的各焊球，以完成多个半导体封装；以及进行切割工艺，以使这些半导体封装彼此分离。
在本发明的一实施例中，上述的这些焊球与这些第一外接点之间配置有多个球底金属层(UBM)，封模底胶包覆这些球底金属层。
在本发明的一实施例中，上述的第二芯片还包括相对于第二主动面的晶背，第二芯片的晶背至第一内接点之间的距离大于各球底金属层的高度，且各球底金属层的高度大于第一主动面与第二主动面之间的距离。
在本发明的一实施例中，上述的各焊球凸出于封模底胶的高度为焊球的高度的0.5倍至0.8倍之间。
在本发明的一实施例中，在倒装这些第二芯片之后且进行模制底胶工艺之前，还包括：配置内底胶于第一芯片的芯片接合区与第二芯片之间，其中在进行模制底胶工艺之后，封模底胶包覆内底胶。
在本发明的一实施例中，上述的保护层位于第一芯片的第一主动面上的这些第一外接点所环绕的虚拟范围以外的区域，封模底胶包覆第二芯片的局部的各第二芯片侧面及局部的这些第一导电凸块，各第一导电凸块为焊球。
基于上述，本发明的半导体封装的底胶包覆这些第二导电凸块、至少局部的各第二芯片侧面及至少局部的各第一导电凸块，以增加整体的结构强度。因此，本发明的半导体封装能具有较低的破裂率。此外，本发明更提供多种半导体封装的制造方法，以制造出上述的半导体封装。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A至图1F是依照本发明的一实施例的一种半导体封装的制造流程示意图；
图1G至图1J是依照本发明的其他实施例的多种半导体封装的示意图；
图2A至图2E是依照本发明的另一实施例的一种半导体封装的制造流程示意图；
图2F至图2G是依照本发明的其他实施例的多种半导体封装的示意图；
图3是依照本发明的一实施例的一种半导体封装的示意图。
附图标记：
100、100a、100b、100c、100d、200、200a、200b、300：半导体封装；
105：晶圆；
110：第一芯片；
112：第一主动面；
114：芯片接合区；
116：第一内接点；
118：第一外接点；
119：虚拟范围；
120：第二芯片；
122：第二主动面；
124：第二接点；
126：第二芯片侧面；
128：晶背；
130：第一导电凸块；
132：球底金属层；
140：第二导电凸块；
150：底胶；
152：封模底胶；
154：内底胶；
160：焊件；
162：焊球；
164：焊帽；
166：焊层；
170、175：保护层。
具体实施方式
图1A至图1F是依照本发明的一实施例的一种半导体封装100的制造流程示意图。本实施例的半导体封装100的制造方法包括下列步骤。首先，请先参阅图1A，提供晶圆105，晶圆105包括阵列排列的多个第一芯片110。在图1A中仅示意性地示出晶圆105的其中一个剖面，此剖面以三个并排的第一芯片110为示意，实际上晶圆105的第一芯片110的数量并不以此为限制。在本实施例中，各第一芯片110包括第一主动面112，第一主动面112包括芯片接合区114、多个位于芯片接合区114内的第一内接点116以及多个位于芯片接合区114外的第一外接点118。
在工艺的一开始可选择性地对晶圆105进行清洗(Incoming Clean)的步骤，通过例如是高压水柱清洗的方式来移除第一芯片110表面的脏污。当然，在其他实施例中，也可以选择不对晶圆105进行清洗。
接着，配置一保护层170于第一芯片110的第一主动面112上，这些第一内接点116与这些第一外接点118外露于保护层170，保护层170包括对应于芯片接合区114的开口。详细地说，可先在第一芯片110上涂布保护层170，保护层170的材料可为一般的感光性光阻材料，如聚酰亚胺(Polyimide,PI)、聚苯恶唑(Polybenzoxazole,PBO)、苯并环丁烯(Benzocyclobuten,BCB)、丙烯酸酯(Acrylates)或环氧树脂(Epoxy)等。再罩设一光罩(未示出)在保护层170，并且进行曝光(Exposure)的程序，其中光罩的图案对应于所欲露出的第一芯片110的图案。之后进行显影(Develop)的程序，以显影液将未曝光的保护层170溶解并移除。接着，通过加热的方式固化(Curing)未被移除的保护层170，再通过例如是氧气等离子体或氮气等离子体或氮氧混合气等离子体等的方式对固化的保护层170进行表面处理，即可完成保护层170。再来，配置多个第一导电凸块130于这些第一外接点118上。配置第一导电凸块130的方式可包括植球、电镀、印刷等方式经后回焊(reflow)成型或不经后回焊(reflow)工艺。在本实施例中，第一导电凸块130的材质包括单一金属元素或合金，其材质可包括金、银、铜、锡、镍或其合金。且在本发明附图中，第一导电凸块130以柱状为例，然而，第一导电凸块130的外观形状也可以是球状，并不以上述为限制，且其所选用的材料也可采用单一种金属材料或采用两种或两种以上的金属材料电镀成型，例如，铜柱(CopperPillar)上形成一层锡银合金(Solder layer)，或铜柱(Copper Pillar)上形成一锡银合金帽(Solder cap)或铜柱上覆盖一层镍及金或于铜柱外壁覆盖一层金，均为本发明可行的导电凸块。
再来，请参阅图1B，倒装多个尺寸较小的第二芯片120于这些第一芯片110的这些芯片接合区114。在本实施例中，各第二芯片120包括一第二主动面122、连接于第二主动面122的多个第二芯片120侧面、相对于第二主动面122的一晶背128及配置在第二主动面122上的保护层175。各第二主动面122包括多个第二接点124，第二接点124外露于保护层175，各第二主动面122面对第一主动面112且这些第二接点124通过多个第二导电凸块140电性连接于这些第一内接点116使第一芯片110与第二芯片120接合并产生电性连接。接合的方式可为回焊(reflow)、热压合(thermal compression bond,TCB)、热压共晶(thermaleutectic)、超音波热压(thermal ultrasonic)等方式。在本实施例中，第一导电凸块130的高度会大于第二导电凸块140的高度。更进一步地说，第一导电凸块130的高度会大于第二导电凸块140与第二芯片120的总高度。
同样地，在本实施例中，第二导电凸块140的材质包括单一金属元素或合金，其材质可包括金、银、铜、锡、镍或其合金。且在本发明附图中，第二导电凸块140以柱状为例，然而，第二导电凸块140的外观形状也可以是球状，并不以上述为限制，且其所选用的材料也可采用单一种金属材料或采用两种或两种以上之金属材料电镀成型，例如，铜柱(CopperPillar)上形成一层锡银合金(Solder Layer)，或铜柱(Copper Pillar)上形成一锡银合金帽(Solder Cap)，或铜柱上覆盖一层镍及金或于铜柱外壁覆盖一层金，均为本发明的可行的导电凸块。
接着，请参阅图1C，进行模制(molding)底胶工艺，以在第一芯片110的第一主动面112上形成一底胶150。在本实施例中，底胶150以封模底胶152为例，其中封模底胶152包覆这些第一导电凸块130及这些第二芯片120。在本实施例中，封模底胶152的材质例如是由环氧树脂型材料、热固性材料、热塑性材料、UV固化材料、或其相似物所形成。热固性材料可包括酚型、酸酐型、或胺型硬化剂及丙烯酸聚合物添加剂。但封模底胶152的材质并不以此为限制。封模底胶152可用来提供第一芯片110与第二芯片120之间的固定效果，并能够提供缓冲及防潮防尘等效果来提升封装的可靠度。
再来，请参阅图1D，对底胶150(封模底胶152)进行一研磨工艺，而使这些第一导电凸块130外露。在本实施例中，通过对底胶150(封模底胶152)进行机械研磨来降低底胶150(封模底胶152)的高度。由于第一导电凸块130的高度大于第二芯片120的晶背128与第一主动面112之间的距离，因此，当第一导电凸块130外露时，第二芯片120的晶背128尚会被底胶150(封模底胶152)覆盖。
接着，请参阅图1E，配置多个焊件160于这些第一导电凸块130上以形成多个半导体封装100。在本实施例中，焊件160以焊球162为例，但焊件160的种类并不以此为限制。最后，进行一切割工艺，以使这些半导体封装100彼此分离，而形成如图1F所示的半导体封装100。
请参阅图1F，本实施例的半导体封装100包括一第一芯片110、一第二芯片120、多个第一导电凸块130、多个第二导电凸块140、一底胶150、多个焊件160及一保护层170。第一芯片110包括一第一主动面112，其中第一主动面112包括一芯片接合区114、多个位于芯片接合区114内的第一内接点116以及多个位于芯片接合区114外的第一外接点118。保护层170配置于第一芯片110的第一主动面112上，这些第一内接点116与这些第一外接点118外露于保护层170，保护层170包括对应于芯片接合区114的一开口。
第二芯片120倒装于(flip on)第一芯片110的芯片接合区114处，且包括一第二主动面122及连接于第二主动面122的多个第二芯片120侧面，其中第二主动面122包括多个第二接点124。这些第一导电凸块130配置于这些第一外接点118上。这些第二导电凸块140位于这些第一内接点116与这些第二接点124之间，各第一内接点116分别通过对应的第二导电凸块140与对应的第二接点124电性连接。
底胶150位在第一主动面112上且包覆这些第二导电凸块140、至少局部的各第二芯片120侧面及至少局部的各第一导电凸块130。更明确地说，底胶150包括一封模底胶152(molded underfill，MUF)，封模底胶152包覆全部的这些第二芯片120侧面。
在本实施例中，这些第一导电凸块130的高度大于或等于第二芯片120的晶背128至第一内接点116之间的距离，这些第一导电凸块130外露于封模底胶152，第二芯片120还包括相对于第二主动面122的一晶背128，晶背128被封模底胶152覆盖。这些焊件160配置于封模底胶152上且连接于这些第一导电凸块130，焊件160的种类以焊球162为例。
本实施例的半导体封装100通过底胶150(封模底胶152)包覆这些第二导电凸块140、至少局部的各第二芯片120侧面及至少局部的各第一导电凸块130，因此，半导体封装100的整体结构强度可有效地提升，而使得本实施例的半导体封装100能具有较低的破裂率。
需说明的是，虽然在本实施例中是先在这些第一外接点118上形成多个第一导电凸块130之后，再将第二芯片120覆设于芯片接合区114上。但在其他实施例中，也可以是先将第二芯片120覆设于芯片接合区114上，以使第二导电凸块140连接至第一内接点116，再在这些第一外接点118上形成多个第一导电凸块130，工艺顺序上可视需求而调整。
值得一提的是，在一未示出的工艺中，可再使这些单离化的半导体封装100以这些第一导电凸块130电性连接至一线路板(未示出)，以使第一芯片110、第二芯片120与线路板三者之间电性连接。在上述结构中，第二芯片120与第二导电凸块140会位于线路板与第一芯片110之间。
上面仅显示其中一种半导体封装100的形式。下面将举出其他种半导体封装100a、半导体封装100b、半导体封装100c、半导体封装100d，为了方便了解，在下面的这些实施例中，与前一实施例相同或相似的元件以与前一实施例相同或相似的元件编号来表示，不再多加赘述。图1G至图1J是依照本发明的其他实施例的多种半导体封装的示意图。
请先参阅图1G与图1H，图1G的半导体封装100a、图1H的半导体封装100b与前一实施例的半导体封装100的主要差异在于焊件160的形式。在图1F中，焊件160以焊球162为例。在图1G中，焊件160以焊帽164为例。在图1H中，焊件160以焊层166为例。当然，上面仅是举出其中几种焊件160的形式，实际上焊件160的形式并不以上述为限制。
请参阅图1I，图1I的半导体封装100c与图1F的半导体封装100的主要差异在于，在本实施例中，第二芯片120的晶背128外露于封模底胶152。也就是说，在制造本实施例的半导体封装100的过程中，对封模底胶152进行研磨工艺时，会将封模底胶152研磨到晶背128外露的状态。因此，在研磨工艺之后，第一导电凸块130会与第二芯片120的晶背128齐平。
请参阅图1J，图1J的半导体封装100d与图1F的半导体封装100的主要差异在于，在本实施例中，底胶150还包括内底胶154，内底胶154位在第一芯片110的芯片接合区114与第二芯片120之间，内底胶154填入保护层170的开口，且封模底胶152包覆内底填胶154。内底胶154的材质可与封模底胶152不同或相同。本实施例的半导体封装100藉由先利用内底胶154填充于第一芯片110的芯片接合区114与第二芯片120之间，以保护第二导电凸块140，再通过封模底胶152包覆第二芯片120与第一导电凸块130的两阶段式封装，以提供半导体封装100d良好的结构强度。
下面再提供另一种半导体封装的制造流程，图2A至图2E是依照本发明的另一实施例的一种半导体封装100的制造流程示意图。本实施例的半导体封装的制造方法包括下列步骤。
首先，请参阅图2A，提供一晶圆105，包括阵列排列的多个第一芯片110，其中各第一芯片110包括一第一主动面112，第一主动面112包括一芯片接合区114、多个位于芯片接合区114内的第一内接点116以及多个位于芯片接合区114外的第一外接点118，第一主动面112上配置有一保护层170，保护层170包括至少对应于芯片接合区114的开口，且这些第一内接点116与这些第一外接点118外露于保护层170。
接着，进行球底金属层132(UBM)的沉积工艺。在本实施例中，先通过氩气去移除第一外接点118上的氧化物。接着，在第一外接点118上依序溅镀钛钨层与金层或钛层与铜层，然后再电镀上金或铜或铜、镍、金等，以在这些第一外接点118形成多个球底金属层132。接着，配置多个焊球162于这些第一外接点118上的球底金属层132以与这些第一外接点118电性连接。
再来，请参阅图2B，倒装尺寸较小的多个第二芯片120于这些第一芯片110的这些芯片接合区114，其中各第二芯片120包括第二主动面122、连接于第二主动面122的多个第二芯片120侧面及相对于第二主动面122的晶背128。各第二主动面122包括多个第二接点124，各第二主动面122面对第一主动面112且这些第二接点124电性连接于这些第一内接点116。
接着，请参阅图2C，进行模制(molding)底胶工艺，在第一主动面112上形成底填胶150，在本实施例中，底胶150为封模底胶152，其中封模底胶152包覆这些第二芯片120、这些球底金属层132及局部的各焊球162，以完成多个半导体封装200。最后，请参阅图2D，进行切割工艺，以使这些半导体封装200彼此分离。
请参阅图2E，本实施例的半导体封装200包括第一芯片110、第二芯片120、多个第一导电凸块130(各第一导电凸块130为球底金属层132)、多个第二导电凸块140、底胶150(封模底胶152)、多个焊件160及保护层170。第一芯片110包括第一主动面112，其中第一主动面112包括芯片接合区114、多个位于芯片接合区114内的第一内接点116以及多个位于芯片接合区114外的第一外接点118。保护层170配置于第一芯片110的第一主动面112上，这些第一内接点116与这些第一外接点118外露于保护层170，保护层170包括对应于芯片接合区114的开口。
第二芯片120倒装于(flip on)第一芯片110的芯片接合区114处，且包括第二主动面122及连接于第二主动面122的多个第二芯片120侧面，其中第二主动面122包括多个第二接点124。这些球底金属层132配置于这些第一外接点118上。这些第二导电凸块140位于这些第一内接点116与这些第二接点124之间，各第一内接点116分别通过对应的第二导电凸块140与对应的第二接点124电性连接。
封模底胶152位在第一主动面112上且包覆这些第二导电凸块140、各第二芯片120侧面、各球底金属层132及局部的各焊球162。在本实施例中，第二芯片120的晶背128至第一内接点116之间的距离大于各球底金属层132的高度，且各球底金属层132的高度大于第一主动面112与第二主动面122之间的距离。此外，在本实施例中，各焊球162凸出于封模底胶152的高度为焊球162的高度的0.5倍至0.8倍之间，上述数值范围可使得封模底胶152对焊球162有一定的固定效果且不影响焊球162后续与线路板(未示出)的连接。本实施例的半导体封装100除了第二芯片120被封模底胶152包封之外，焊球162的一部分也被封模底胶152包封，可有效增加整体的结构强度。
下面继续介绍其他半导体封装200a、半导体封装200b。图2F至图2G是依照本发明的其他实施例的多种半导体封装100的示意图。请先参阅图2F，图2F的半导体封装200a与图2E的半导体封装200的主要差异在于，保护层170在第一芯片110上的位置。在图2E中，一部分的保护层170位在两第一外接点118之间，保护层170的开口大致上对应于芯片接合区114(标示于图2D)。在图2F中，保护层170只位在两第一外接点118之外，也就是说，保护层170的开口范围接近于第一外接点118所围绕的范围。
请参阅图2G，图2G的半导体封装200b与图2E的半导体封装200的主要差异在于，在本实施例中，底填胶150还包括内底胶154，内底胶154位在第一芯片110的芯片接合区114与第二芯片120之间，封模底胶152包覆内底胶154。内底胶154的材质可与封模底胶152不同或相同。本实施例的半导体封装100藉由先利用内底胶154填充于第一芯片110的芯片接合区114与第二芯片120之间，以保护第二导电凸块140，再通过封模底胶152包覆第二芯片120、球底金属层132及局部的各焊球162的两阶段式封装，以提供半导体封装200b良好的结构强度。
图3是依照本发明的一实施例的一种半导体封装100的示意图。请参阅图3，图3的半导体封装300与图2E的半导体封装200的主要差异在于，在本实施例中，保护层170配置于第一芯片110的第一主动面112上的这些第一外接点118所环绕的一虚拟范围119以外的区域。底填胶150以充填涂胶的方式包覆各第二芯片120侧面及局部的这些第一导电凸块130(焊球162)，而完全的包覆住第一外接点118与导电凸块130接合处，并终止于保护层170的边缘。本实施例的半导体封装100通过底胶150包覆第二芯片120的局部的各第二芯片120侧面及局部的焊球162而使半导体封装300的整体结构强度能够提升。
综上所述，本发明的半导体封装的底胶包覆这些第二导电凸块、至少局部的各第二芯片侧面及至少局部的各第一导电凸块，以增加整体的结构强度。因此，本发明的半导体封装能具有较低的破裂率。此外，本发明更提供多种半导体封装的制造方法，以制造出上述的半导体封装。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中普通技术人员，在不脱离本发明的精神和范围内，当可作些许的更改与润饰，均在本发明范围内。

Claims (20)

1.一种半导体封装，其特征在于，包括：
第一芯片，包括第一主动面，其中所述第一主动面包括芯片接合区、多个位于所述芯片接合区内的第一内接点以及多个位于所述芯片接合区外的第一外接点；
第二芯片，倒装于所述第一芯片的所述芯片接合区处，且包括第二主动面及连接于所述第二主动面的多个第二芯片侧面，其中所述第二主动面包括多个第二接点；
多个第一导电凸块，配置于所述多个第一外接点上；
多个第二导电凸块，位于所述多个第一内接点与所述多个第二接点之间，各所述第一内接点分别通过对应的所述第二导电凸块与对应的所述第二接点电性连接；以及
底填胶，位在所述第一主动面上且包覆所述多个第二导电凸块、至少局部的各所述第二芯片侧面及至少局部的各所述第一导电凸块。
2.根据权利要求1所述的半导体封装，其特征在于，所述底填胶包括封模底胶，所述封模底胶包覆全部的所述多个第二芯片侧面。
3.根据权利要求2所述的半导体封装，其特征在于，所述第二芯片还包括相对于所述第二主动面的晶背，所述晶背被所述封模底胶覆盖，或者所述晶背外露于所述封模底胶。
4.根据权利要求2所述的半导体封装，其特征在于，还包括：
多个焊件，所述多个第一导电凸块外露于所述封模底胶，所述多个焊件配置于所述封模底胶上且连接于所述多个第一导电凸块，其中各所述焊件包括焊球、焊帽或焊层。
5.根据权利要求4所述的半导体封装，其特征在于，所述多个第一导电凸块的高度大于或等于所述第二芯片的所述晶背至所述第一内接点之间的距离。
6.根据权利要求2所述的半导体封装，其特征在于，还包括：
多个焊球，配置于所述多个第一导电凸块上，各所述第一导电凸块为球底金属层，所述封模底胶包覆局部的各所述焊球：以及
保护层，配置于所述第一芯片的所述第一主动面上，所述保护层包括至少对应于所述芯片接合区的开口，且所述多个第一内接点与所述多个第一外接点外露于所述保护层。
7.根据权利要求6所述的半导体封装，其特征在于，所述第二芯片还包括相对于所述第二主动面的晶背，所述第二芯片的所述晶背至所述第一内接点之间的距离大于各所述第一导电凸块的高度，且各所述第一导电凸块的高度大于各所述第二导电凸块的高度。
8.根据权利要求6所述的半导体封装，其特征在于，各所述焊球凸出于所述封模底胶的高度为所述焊球的高度的0.5倍至0.8倍之间。
9.根据权利要求2所述的半导体封装，其特征在于，还包括：
保护层，配置于所述第一芯片的所述第一主动面上，所述多个第一内接点与所述多个第一外接点外露于所述保护层，所述保护层包括对应于所述芯片接合区的开口，所述底填胶包括内底胶，所述内底胶位在所述第一芯片的所述芯片接合区与所述第二芯片之间，所述封模底胶包覆所述内底胶。
10.根据权利要求1所述的半导体封装，其特征在于，还包括：
保护层，配置于所述第一芯片的所述第一主动面上的所述多个第一外接点所环绕的虚拟范围以外的区域，所述底胶包覆所述第二芯片的局部的各所述第二芯片侧面及局部的所述多个第一导电凸块，各所述第一导电凸块为焊球。
11.一种半导体封装的制造方法，其特征在于，包括：
提供晶圆，包括阵列排列的多个第一芯片，其中各所述第一芯片包括第一主动面，所述第一主动面包括芯片接合区、多个位于所述芯片接合区内的第一内接点以及多个位于所述芯片接合区外的第一外接点；
配置多个第一导电凸块于所述多个第一外接点上；
倒装多个第二芯片于所述多个第一芯片的所述多个芯片接合区，其中各所述第二芯片包括第二主动面及连接于所述第二主动面的多个第二芯片侧面，各所述第二主动面包括多个第二接点，各所述第二主动面面对所述第一主动面且所述多个第二接点电性连接于所述多个第一内接点；
进行一模制底胶工艺，以在所述第一主动面上形成封模底胶，其中所述封模底胶包覆所述多个第一导电凸块及所述多个第二芯片；
对所述封模底胶进行研磨工艺，而使所述多个第一导电凸块外露；
配置多个焊件于所述多个第一导电凸块上以形成多个半导体封装；以及
进行切割工艺，以使所述多个半导体封装彼此分离。
12.根据权利要求11所述的半导体封装的制造方法，其特征在于，各所述焊件包括焊球、焊帽或焊层。
13.根据权利要求11所述的半导体封装的制造方法，其特征在于，所述第二芯片还包括相对于所述第二主动面的晶背，在对所述封模底胶进行所述研磨工艺的步骤之后，所述晶背外露于所述封模底胶。
14.根据权利要求11所述的半导体封装的制造方法，其特征在于，在倒装所述多个第二芯片之后且进行所述模制底胶工艺之前，还包括：
配置保护层于所述第一芯片的所述第一主动面上，所述多个第一内接点与所述多个第一外接点外露于所述保护层，所述保护层包括对应于所述芯片接合区的开口；以及
配置内底胶于所述第一芯片的所述芯片接合区与所述第二芯片之间，
其中在进行所述模制底胶工艺之后，所述封模底胶包覆所述内底胶。
15.一种半导体封装的制造方法，其特征在于，包括：
提供晶圆，包括阵列排列的多个第一芯片，其中各所述第一芯片包括第一主动面，所述第一主动面包括芯片接合区、多个位于所述芯片接合区内的第一内接点以及多个位于所述芯片接合区外的第一外接点，所述第一主动面上配置有一保护层，所述保护层包括至少对应于所述芯片接合区的开口，且所述多个第一内接点与所述多个第一外接点外露于所述保护层；
配置多个焊球于所述多个第一外接点上以与所述多个第一外接点电性连接；
倒装多个第二芯片于所述多个第一芯片的所述多个芯片接合区，其中各所述第二芯片包括第二主动面及连接于所述第二主动面的多个第二芯片侧面，各所述第二主动面包括多个第二接点，各所述第二主动面面对所述第一主动面且所述多个第二接点电性连接于所述多个第一内接点；
进行模制底胶工艺，在所述第一主动面上形成封模底胶，其中所述封模底胶包覆所述多个第二芯片及局部的各所述焊球，以完成多个半导体封装；以及
进行切割工艺，以使所述多个半导体封装彼此分离。
16.根据权利要求15所述的半导体封装的制造方法，其特征在于，所述多个焊球与所述多个第一外接点之间配置有多个球底金属层，所述封模底胶包覆所述多个球底金属层。
17.根据权利要求16所述的半导体封装的制造方法，其特征在于，所述第二芯片还包括相对于所述第二主动面的晶背，所述第二芯片的所述晶背至所述第一内接点之间的距离大于各所述球底金属层的高度，且各所述球底金属层的高度大于所述第一主动面与所述第二主动面之间的距离。
18.根据权利要求15所述的半导体封装的制造方法，其特征在于，各所述焊球凸出于所述封模底胶的高度为所述焊球的高度的0.5倍至0.8倍之间。
19.根据权利要求15所述的半导体封装的制造方法，其特征在于，在倒装所述多个第二芯片之后且进行所述模制底胶工艺之前，还包括：配置内底胶于所述第一芯片的所述芯片接合区与所述第二芯片之间，其中在进行所述模制底胶工艺之后，所述封模底胶包覆所述内底胶。
20.根据权利要求15所述的半导体封装的制造方法，其特征在于，所述保护层位于所述第一芯片的所述第一主动面上的所述多个第一外接点所环绕的虚拟范围以外的区域，所述封模底胶包覆所述第二芯片的局部的各所述第二芯片侧面及局部的所述多个第一导电凸块，各所述第一导电凸块为焊球。
CN201611022516.1A 2016-08-30 2016-11-16 半导体封装及其制造方法 Pending CN107785325A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW105127804A TWI610409B (zh) 2016-08-30 2016-08-30 半導體封裝及其製造方法
TW105127804 2016-08-30

Publications (1)

Publication Number Publication Date
CN107785325A true CN107785325A (zh) 2018-03-09

Family

ID=61243349

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611022516.1A Pending CN107785325A (zh) 2016-08-30 2016-11-16 半导体封装及其制造方法

Country Status (3)

Country Link
US (1) US20180061811A1 (zh)
CN (1) CN107785325A (zh)
TW (1) TWI610409B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10048716B1 (en) * 2017-02-10 2018-08-14 Apple Inc. Method and apparatus for power distribution in integrated circuits
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US11257679B2 (en) * 2018-11-26 2022-02-22 Stmicroelectronics Pte Ltd Method for removing a sacrificial layer on semiconductor wafers
CN111696928B (zh) * 2019-03-15 2022-10-28 富泰华工业（深圳）有限公司 半导体封装结构及其制造方法
US11362010B2 (en) * 2019-10-16 2022-06-14 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out feature
TWI766280B (zh) * 2020-05-14 2022-06-01 南茂科技股份有限公司 晶圓級晶片尺寸封裝結構及其製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060237833A1 (en) * 2003-01-27 2006-10-26 Klein Dean A System having semiconductor component with multiple stacked dice
US20070013064A1 (en) * 2005-07-15 2007-01-18 Shinko Electric Industries Co., Ltd. Semiconductor device and electronic apparatus
US20130320518A1 (en) * 2012-05-31 2013-12-05 Sts Semiconductor & Telecommunications Co., Ltd. Wafer-level package and method of manufacturing the same
CN103515342A (zh) * 2012-06-29 2014-01-15 台湾积体电路制造股份有限公司 封装结构及其形成方法
US20140170814A1 (en) * 2010-11-02 2014-06-19 Fujitsu Semiconductor Limited Ball grid array semiconductor device and its manufacture

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW560698U (en) * 2002-09-09 2003-11-01 Via Tech Inc Structure of chip package
TW591770B (en) * 2003-03-14 2004-06-11 Ind Tech Res Inst Packaging method for semiconductor device
US20100120199A1 (en) * 2008-11-07 2010-05-13 Bok Sim Lim Stacked package-on-package semiconductor device and methods of fabricating thereof
US9082806B2 (en) * 2008-12-12 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
JP6163108B2 (ja) * 2011-03-04 2017-07-12 ポドマジェルスキー，カール 水泡又は気泡を生成する方法と装置
US8981559B2 (en) * 2012-06-25 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
CN103568890B (zh) * 2012-07-18 2016-04-06 宝钜儿童用品香港股份有限公司 儿童座椅
KR101953396B1 (ko) * 2013-10-23 2019-03-04 앰코테크놀로지코리아(주) 반도체 패키지 및 그 제작 방법
US10032652B2 (en) * 2014-12-05 2018-07-24 Advanced Semiconductor Engineering, Inc. Semiconductor package having improved package-on-package interconnection
US9601472B2 (en) * 2015-04-24 2017-03-21 Qualcomm Incorporated Package on package (POP) device comprising solder connections between integrated circuit device packages
US20160379910A1 (en) * 2015-06-24 2016-12-29 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060237833A1 (en) * 2003-01-27 2006-10-26 Klein Dean A System having semiconductor component with multiple stacked dice
US20070013064A1 (en) * 2005-07-15 2007-01-18 Shinko Electric Industries Co., Ltd. Semiconductor device and electronic apparatus
US20140170814A1 (en) * 2010-11-02 2014-06-19 Fujitsu Semiconductor Limited Ball grid array semiconductor device and its manufacture
US20130320518A1 (en) * 2012-05-31 2013-12-05 Sts Semiconductor & Telecommunications Co., Ltd. Wafer-level package and method of manufacturing the same
CN103515342A (zh) * 2012-06-29 2014-01-15 台湾积体电路制造股份有限公司 封装结构及其形成方法

Also Published As

Publication number Publication date
TW201807788A (zh) 2018-03-01
TWI610409B (zh) 2018-01-01
US20180061811A1 (en) 2018-03-01

Similar Documents

Publication Publication Date Title
KR102425720B1 (ko) 반도체 패키지 및 그 제조 방법
TWI701790B (zh) 晶片封裝結構與其形成方法
CN103515362B (zh) 堆叠式封装器件和封装半导体管芯的方法
CN107785325A (zh) 半导体封装及其制造方法
CN206657808U (zh) 电子装置
CN102005432B (zh) 四面无引脚封装结构及其封装方法
CN108063094A (zh) 基于基板的扇出型晶圆级封装
JP5068990B2 (ja) 電子部品内蔵基板
CN108597998A (zh) 晶圆级系统封装方法及封装结构
US20130288430A1 (en) Semiconductor device and method for manufacturing thereof
CN106169459A (zh) 半导体封装组件及其形成方法
KR20170047019A (ko) 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
CN103311138A (zh) 封装方法和封装的半导体器件
TW200416787A (en) Semiconductor stacked multi-package module having inverted second package
TW200836311A (en) Semiconductor device package with multi-chips and method of the same
US8431478B2 (en) Solder cap bump in semiconductor package and method of manufacturing the same
CN105977225B (zh) 封装结构以及封装方法
CN206040641U (zh) 半导体装置
TW201727850A (zh) 半導體裝置及其製造方法
US8283780B2 (en) Surface mount semiconductor device
CN109559996A (zh) 一种3D高密度互联的PoP塑封器件制备方法
CN105845585A (zh) 一种芯片封装方法及芯片封装结构
US9024439B2 (en) Substrates having bumps with holes, semiconductor chips having bumps with holes, semiconductor packages formed using the same, and methods of fabricating the same
KR20120042240A (ko) Ｔｍｖ 패키지온패키지 제조방법
JP2003258009A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20180309