TW201349397A - 半導體封裝結構之多層基板 - Google Patents

半導體封裝結構之多層基板 Download PDF

Info

Publication number
TW201349397A
TW201349397A TW102110736A TW102110736A TW201349397A TW 201349397 A TW201349397 A TW 201349397A TW 102110736 A TW102110736 A TW 102110736A TW 102110736 A TW102110736 A TW 102110736A TW 201349397 A TW201349397 A TW 201349397A
Authority
TW
Taiwan
Prior art keywords
layer
conductive
substrate
carrier
semiconductor substrate
Prior art date
Application number
TW102110736A
Other languages
English (en)
Other versions
TWI694557B (zh
Inventor
Shoa-Siong Raymond Lim
Hwee-Seng Jimmy Chew
Original Assignee
Advanpack Solutions Private Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanpack Solutions Private Ltd filed Critical Advanpack Solutions Private Ltd
Publication of TW201349397A publication Critical patent/TW201349397A/zh
Application granted granted Critical
Publication of TWI694557B publication Critical patent/TWI694557B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本發明提供一種半導體基板，半導體基板包括二或多層堆疊結構層，堆疊結構層形成於一犧牲載體上。各堆疊結構層包括一導電線路層及一相互連接件，各堆疊結構層被封膠於一樹脂封膠複合物中。封膠複合物之頂部表面係為研磨面且設置一黏合層於研磨面上。於一最外部導電線路層形成於黏合層上及載體或加強環被移除後，獲得一多層基板。

Description

半導體封裝結構之多層基板
本發明係有關用於半導體封裝結構之多層基板及製造其基板之方法。
傳統之半導體晶片係安裝於導線架(leadframes)上。導線架通常透過以下步驟來形成。塗佈光阻層於銅基板上，使用一遮罩以暴露一圖案於光阻層上，移除光阻層之正或負光阻，接著蝕刻銅來獲得一圖案化導線架。然而，藉由蝕刻形成之圖案化導線架不適合使用於比傳統導線架更密集之互連線路的晶片上。蝕刻將產生底部切割(undercutting)及較細的傳導線路，而導致高生產量之可靠度問題。
Advanpack Solutions所申請之美國專利No.7,795,071敘述一種用於半導體封裝結構之一單層圖案化基板之製造方法。一組圖案線路佈線(patterned conductor layouts)係形成於一鋼材載體上，絕緣材料被注入於一模型中以密封(seal) 導電線路。於移除鋼材載體後，具有一組圖案線路佈線之一基板被形成。更進一步地，圖案化導電佈線係相互地電性絕緣。而於一傳統引線架上，對應至各晶片之各導電佈線係電性連接至鄰接的佈線。
由此可看出存在形成更複雜之導電線路的多層基板的需要，來支持積層線路之未來設計。這些多層基板允許各個導電層使用於訊號、電源、數位或類似的線路等。
以下說明一簡單的摘要，以提供本發明之基礎理解。此摘要並非本發明之詳盡綜述，且並不因而限定本發明之主要技術特徵。反而，這裡以一廣義形式呈現本發明之部分發明概念下，以作為下述詳細介紹之序言。
本發明係提供包括二或多個堆疊結構層之基板，堆疊結構層形成於一犧牲載板(sacrificial carrier)上。各堆疊結構層包括一導電線路層及一相互連接層。各堆疊結構層係封膠於一樹脂複合物(resin compound)中。多層基板係接著藉由形成一最外部導電線路層(outermost conductor trace layer)及移除載體來完成。
於一實施例中，本發明提供一種多層基板，多層基板包括一犧牲載體、一第一導電線路層(first conductor trace layer)、一第二導電線路層(second conductor trace layer)及一相互連接層(interconnect layer)。犧牲載體具有電性傳導且可化學蝕刻；第一導電線路層形成於犧牲載體上；相互連接層設置於第一及第二導電線路層之間，其中相互連接層包括間柱(stud)，間柱連接於第一及第二導電線路層之選擇區域之間。
於多層基板之一實施例中，第一導電線路層及相互連接層係封裝於一樹脂封膠複合物(resin molding compound)中。樹脂封膠之頂部表面係為研磨面(abrasively ground)且一黏合層(adhesion layer)係設置於研磨表面上。黏合層可以是一導電種子層(conductor seed layer)、一聚亞醯氨層(polyimide layer)或一編織玻璃纖維層板(woven glass fiber laminate)。因此，多層基板包括二或多個堆疊結構層，各堆疊結構層係由一導電線路層、一相互連接層及一黏合層所組成，使得最外部層係為一導電線路層。
於另一實施例中，本發明提供一種製造多層半導體基板之方法。此方法包括：形成一第一導電線路層於一犧牲載體上，其中第一導電線路層包括複數導電佈線(conductor layout)；形成一相互連接層於第一導電線路層上，其中相互連接層包括間柱，間柱連接於第一導電線路層之選擇區域；封裝第一導電線路層及相互連接層於一樹脂封膠複合物中；研磨封膠封裝件之一表面為平面並暴露相互連接間柱；設置一黏合層於研磨之封裝件(encapsulation)表面上；重複上述步驟以形成一多層基板之附 加堆疊結構(additional built-up structure)，使得具有二或多個堆疊結構層；及形成一最外部導電線路層於頂部黏合層上。
於另一實施例中，此方法：更包括以一絕緣層密封最外部導電線路層；選擇性地移除絕緣層以暴露最外部導電線路層之區域，最外部導電線路層之區域用以外部電性連接。
較佳地，載體之一內部部分被移除以留下一加強環(reinforcing ring)，加強環位於基板或一組導電佈線之周圍，導電佈線於第一導電線路層中。較佳地，第一導電線路層被一焊接遮罩密封及選擇性移除焊接遮罩以暴露第一導電線路層上之區域，第一導電線路層上之暴露區域用以外部電性連接。
10‧‧‧載體、晶片
20‧‧‧焊接凸塊
22‧‧‧焊球
24‧‧‧金屬柱
30‧‧‧底膠填充複合物
40‧‧‧封膠
100‧‧‧製程
105‧‧‧基板
105a‧‧‧基板
110‧‧‧載體
110a‧‧‧開口
110b‧‧‧加強環(環狀載體)
114‧‧‧第一電性導電材料
114a‧‧‧導電線路層(導電佈線)
114b‧‧‧導電體
118‧‧‧第二電性傳導材料(間柱)
118a‧‧‧相互連接件(導電間柱、相互連接層)
120‧‧‧多層堆疊結構層(封膠絕緣體、第一絕緣層)
122‧‧‧底表面
123‧‧‧黏合層
124‧‧‧黏合層(導電種子層)
128a‧‧‧第二導電線路層
128b‧‧‧選擇區域(第二導電線路層)
130‧‧‧第二絕緣層
140‧‧‧焊接遮罩
150‧‧‧已完成之半導體封裝結構
150a‧‧‧封裝結構
150b‧‧‧封裝結構
160‧‧‧孔洞
170‧‧‧壓力釋放槽
218‧‧‧第二相互連接層(第二間柱)
218a‧‧‧相互連接件
220‧‧‧多層堆疊結構層(第二絕緣封膠)
222‧‧‧表面
224‧‧‧黏合層(第二導電種子層)
228a‧‧‧第三導電線路層
228b‧‧‧選擇區域(最外部導電線路層)
230a‧‧‧焊接遮罩
XX、YY‧‧‧線
本發明藉由並非用以限制之實施例，並配合所附圖式，作詳細說明如下：
第1A-1J圖繪示根據本發明實施例之一雙層基板之結構。
第2A-2D、3及4圖繪示於第1J圖中使用多層基板以形成半導體封裝結構之方法。
第5及6圖繪示根據本發明另一實施例之一雙層基板之結構
第7A-7F圖繪示根據本發明另一實施例之一三層基板之結構。
第8圖繪示根據本發明所獲得之一已完成基板之平面圖。
本發明之一或多個具體且可選擇之實施例伴隨所附圖示將於下所述。然而沒有這些具體細節也可以執行本發明，此應為本領域通常知識者所熟知的。部份細節限於文章長度上，不加以描敘以便不模糊本發明。為了便於參考，當意指圖示中相同或類似特徵時，於說明書中將以相同標號或連續標號代表。
第1A-1J圖繪示根據本發明實施例中一多層基板105之堆疊流程圖，多層基板105包括二個導電線路層。如第1A圖中所繪示，於製程100中第一步驟係提供一載體110，載體110具有一第一表面及相對之一第二表面。較佳地，載體110係由具有高楊氏係數彈性之低價材料所製成，載體110係為電性傳導且適用以化學蝕刻，例如是鋼材。載體110之特性允許於多層基板105之製作期間載體110被部分地犧牲移除及/或半導體封裝完成後載體110被全部移除。較佳地，載體110例如是以退火方式減緩壓力(stress-relieved)或部分減緩壓力，連續製程步驟涉及以一光阻塗佈於載體之一表面，以一遮罩暴露光阻，選擇性地蝕刻光阻，及獲得一圖案化光阻。藉由設置例如是銅材料之一第一電性導電材料(first electric conductor material)114於圖案化光阻上，並接著移除光阻，一圖案化第一導電線路層(patterned first conduetor trace layer)114a係形成於載體110上。圖案化第一導電線路層114a因此包含用以連接一些半導體晶片之複數第一導電佈線(first conductor layout)。較佳地，第一導電材料114係為銅及一適合沉積之製程 係為電鍍。第1B圖繪示穿透過第一導電線路層114a之部分放大圖。為了便於參考，圖案化之第一導電線路層及第一導電佈線以相同標號114a標示。藉由類似微影製程(photolithographic process)或藉由沉積一第二電性導電材料118於所產生之圖案化光阻上來界定相互連結之孔洞，如第1C圖中所繪示，由導電間柱(conductor stud)118組成之一第一相互連接層118a因而形成於第一導電線路層114a上。可選擇地，第一導電線路層114a及第一相互連接層118a係藉由削除(subtractive)微影製程所形成。附加的(additive)、半附加及半削除(semi-additive)之各種結合，可用以產生所需之圖案化結構。以電性絕緣該導電線路及封裝導電線路/間柱於一絕緣材料中，一組第一導電佈線114a及導電間柱118a係設置於一凹處(cavity)中或數組第一導電佈線114a及導電間柱118a係設置於複數凹處中。一絕緣或介電封膠複合物(molding compound)較佳地預先加熱至一液體狀態於一融化溫度下被注入凹處或複數凹處中。較佳地，液態封膠複合物於一正壓下被注入，使得封膠複合物係稠密地封裝一組第一導電佈線114a及導電間柱118a，於封膠複合物固化後以形成一緻密複合結構(compact composite structure)或一第一絕緣層120；由於封膠複合物堅固地結合至第一導電佈線114a及導電間柱118a，使得於濕處理製程中液體不會滲入(enter)導電-封膠複合物之間的介面中。如第1D圖中繪示，因此獲得一半完成基板。較佳地，第一絕緣層120由包含樹脂和二氧化矽填充物的一封膠複合物組 成。較佳地，於第一絕緣層120形成後，二氧化矽矽填充物(silica fillers)被嵌入於樹脂中。
繪示於第1D圖中之半完成基板被移至一機器中心，及第一絕緣層120之自由表面(free surface)藉由研磨料研磨平整至一深度，如第1E圖所繪示，所有導電間柱118a被暴露於底表面122。較佳地，導電間柱118a之暴露表面係為平整的或凹陷(recess)於第一絕緣層120之背表面(如第1E圖所示)，使得第一絕緣層120界定出導電間柱之邊緣及絕緣一導電間柱至另一導電間柱間。於研磨後，於封膠複合物中之二氧化矽填充物也被暴露出。特別地是，此時底表面122包括已置入二氧化矽填充物之樹脂；如第1F圖所繪示，底表面122被發現用以提供沉積一導電種子層(conductor seed layer)124之堅固黏合力。可選擇性地，於研磨期間時藉由增加研磨料的移除速率，表面二氧化矽填充物自樹脂中被提煉出以形成複數凹陷(dimple)於底表面122上。凹陷之底表面122提供一增加表面面積以改善下一個鄰接層之堆疊(buildup)的黏合力。當第一導電材料114係為銅時，導電種子層124材料也係為銅。適用以沉積銅種子層124之方法係為無電電鍍(electroless plating)、電解電鍍(electrolytic plating)、濺射、化學氣相沉積(CVD)或物理氣相沉積(PVD)。
藉由使用微影製程，接著一圖案化光阻形成於導電種子層124上且藉由電鍍銅於圖案化光阻上，如第1G圖中所繪示之一圖案化第二導電線路層128a被獲得。第二導電線路層128a 係由複數第二導電佈線128a所製成；各第二導電佈線128a係通過各相關連之第一導電間柱118a電性連接至相關連之第一導電佈線114a。
如第1H所繪示，圖案化第二導電線路層128a藉由以第二絕緣或介電層130封裝來完成。較佳地，第二絕緣層130係為一焊墊遮罩(soldermask)，焊墊遮罩包括一感光聚合物材料(photo imageable polymer material)。較佳地，第二絕緣層130係以網印製(screen printed)之方式設置於圖案化第二導電線路層128a上。第二絕緣層130接著暴露於輻射射線(例如是雷射)中，通過一遮罩及藉由選擇性移除，如第1I圖所繪示第二導電線路層128a之選擇區域128b被暴露用以外部電性連接。用以焊接性於已暴露之第二導電線路層128b上之進一步製程可以包括沉積一錫層或一鎳/金層。
如第1I圖所繪示，載體110大於已封膠之第一絕緣層120。有益地，載體110之一內部部分110a例如藉由蝕刻來部分地被犧牲及移除，使得剩餘一環狀(ring)110b並獲得如第1J圖所繪示之一已完成基板105。於移除載體100之後，第一導電線路層114a與第一絕緣層120之表面共同被暴露出來。較佳地，第一導電佈線114a之表面係為平整或凹陷於第一絕緣層120之頂表面(如第1J圖所示)，使得絕緣層120界定第一導電佈線114a之邊緣並絕緣一第一導電佈線至另一第一導電佈線間。如上所述，載體110係由具有高楊氏係數之材料所製成並減緩壓力；藉 由剩餘於基板105上載體110之一環狀110b，環狀載體110b幫助維持已完成基板105之平坦度，同時提供用以處理及後續製造之已完成基板105之堅硬度。於另一實施例中，內部開口110a小於一組已封膠之第一絕緣層120，使得複數開口110a形成於載體110上，而不是僅留下環繞於整個基板之一載體環(carrier ring)。再者，於封膠區域120外部之周圍區域內，載體環110b藉由定位孔或基準孔160(如第8圖所示)來形成。另外，若載板110使用前未減緩壓力，壓力釋放槽(stress-relief slots)170(如第8圖所示)可能會於內部110a被蝕刻前被打印(stamped)或形成於周圍部份。有助益地，具有定位/基準孔或壓力釋放槽之載體周圍部份界定出夾持區域，夾持區域用於上述之第一絕緣層120之封膠射入或擠壓、單一之已完成之半導體封裝結構或使用於其他之中間製程，使得所需要之夾持區域遠離於脆弱之封膠區域，封膠區域包括第一及第二導電線路及相互連接間柱(interconnecting stud)，因而確保連續地製程不會損壞到封膠區域。
為簡化圖示，第2A圖繪示形成於一封膠絕緣體120周圍之環狀載體110B。如第2A圖中所繪示，一半導體晶片10通過連接焊接凸塊(solder bump)20及金屬柱(pillar)24連接至第一導電佈線114a。晶片之嵌入藉由一底膠填充複合物(underfill compound)30也被增強。於第2B圖中，於晶片10嵌設於基板105後，整個晶片被封裝於一封膠(molding)40中。 較佳地，封膠40係由具有與第一絕緣層120之相似於或相同特性之材料所製成用以將由於特性的差異所產生的壓力降至最低。焊球22也可被設置來連接用以外部電性連接之已暴露第二導電佈線128b。於第2C圖中，已封裝之晶片沿著XX及YY線被切割以提供一已完成之半導體封裝結構150，已完成之半導體封裝結構150包括藉由本發明之製程100所獲得之基板105。
除了使用焊接凸塊連接以外，如第3圖中所繪示之晶片10可以是以線路連接至第一導電佈線114a，及另一已完成之半導體封裝結構150a包括藉由上述製程100所獲得之基板105。再者，如第4圖所繪示，一已完成之半導體封裝結構150c可以包括二或更多晶片、被動元件(passives)或封裝結構，包括使用不同半導體製造技術製成之晶片。
請參考至第1J及2C圖中，各第一導電佈線114a之周圍，一些外圍導電體114b並沒有電性連接至第一導電佈線114a之剩餘部份且被提供用以控制電鍍製程。舉例來說，導電體114b可以作為「電流竊取者(current stealers)」於間柱118及/或第二導電線路層128a電鍍時用以改變電流分佈來達到均勻的電鍍厚度。可選擇性地，藉由改變越過基板區域之混合熱膨脹係數(coefficient of thermal expansion,CTE)，導電體114b被提供用以改變於基板105上之壓力分佈。
第5及6圖繪示上述實施例中之不同結構。舉例來說，如第5圖中所繪示，於沉積導電種子層124前，一黏合層123 係用於已封膠之第一絕緣層120之底表面122以增加第二導電線路層128a之黏合。較佳地，黏合層123係為一聚亞醯氨或編織玻璃纖維層板。於第6圖中，基板105之一頂表面以一焊接遮罩140來沉積，使得第一導電線路層114a之選擇區域被暴露出用以外部電性連接。
第7A至7F圖繪示包含三個導電線路層之一多層基板105a之製造流程圖。第7A圖繪示於第1G圖中半完成之半導體基板之結構的後續堆疊(continued buildup)。如第7A圖所繪示，包括第二導電間柱218之一第二相互連接層218係藉由微影及電鍍製程形成於圖案化第二導電線路層218a上。於第7B圖中，並非藉由第二導電線路層128a之堆疊的導電種子層124，係藉由化學蝕刻來移除。
於第7C圖中，於半完成基板上之已封膠第一絕緣層120係以一第二絕緣封膠(second insulator molding)220來封膠。如於第一絕緣層內，第二絕緣封膠也包括一介質樹脂(matrix of resin)及嵌入式無機二氧化矽填充物(embedded inorganic silica fillers)。第二絕緣封膠220可以是與第一絕緣封膠120相同尺寸。如第7C圖所繪示，第二絕緣封膠220較大且第二絕緣封膠220封裝第一絕緣封膠於所謂的二次射出封膠(molding-over-molding)中。
如第1E圖中，第二絕緣封膠220之自由表面係為研磨面(abrasively ground)用以提供一平表面222。已研磨之封 膠表面222也提供用以被沉積之一第二導電種子層224及被堆疊之一第三導電線路層228a較佳之黏合力。當第三導電線路層228a係為一已完成基板之最外部導電線路層，最外部導電線路層係被以焊接遮罩所封裝，且如第7F圖所示用以外部電性連接之最外部導電線路層之選擇區域接著被暴露出。
於第7E圖中繪示載體110之一內部部分，載體110之一內部部分被部份地蝕刻以暴露出第一導電線路層114a，以至於在基板製成完成前，於基板105a上留下一強化環(reinforcement ring)110b。一強化環110b形成於基板105a製程完成之後是可能。所產生之基板105a包括複數絕緣層，複數絕緣層鄰接至具有絕緣層之另一絕緣層上，具有絕緣層之另一絕緣層具有一對應之(導電元件)導電線路層且一相互連接層嵌入於其內。平行於鄰接絕緣層之連接表面之一分隔面位於二絕緣層之間，使得一絕緣層內之導電線路元件不會穿越分隔面至另一鄰接的絕緣層。然而，於各對應之絕緣層內之導電線路元件電性連接至另一導電線路元件，以使得基板105a之頂部表面電性連接於基板之背部表面。特別地是，於一絕緣層內之相互連接層是電性地及實質地連接於鄰接絕緣層之導電線路層。
第8圖繪示根據第1J或7F圖中俯視基板105，105a頂部之一平面圖。如第8圖中通過載體110內之開口110a所示，繪示出一組九個導電佈線114a之第一導電線路層114a，第一導電線路層114a被封裝於一封膠120，220中。如上所述，於各導 電佈線114a中，這裡的單獨之導電體114b被提供作為”電流竊取者”於電鍍期間用以校正電流之分佈；另外單獨之導電體114b可用以緩和穿越基板之混合熱膨脹係數，將製程期間中熱改變所導致之任何翹曲(warpage)降至最低。於基板105，105a周圍之夾持區域內，也就是通過強化環170之厚度，夾持區域內有定位(positioning)或基準(fiducial)孔洞160及壓力釋放槽(stress-relief slots)170。
上述圖示繪示形成具有二個或三個導電線路層之多層基板。藉由形成各附加之堆疊層以獲得具有超過三層之導電線路層是有可能的，各附加之堆疊層具有一導電線路層及一相互連結間柱層(interconnect stud layer)，並封裝一導電線路層及一相互連結間柱層於一樹脂封膠複合物中。於本發明中，多層基板允許更多複雜的相互連結途徑來支撐新半導體晶片之封裝結構。有助益地，多層導電線路也可以分開設計以裝載不同型態之訊號或電源，例如減少訊號干擾。導電佈線之型態尺寸並不受限於蝕刻之特性，根據本發明之多層基板也提供達成線路微型化(miniaturization)之優勢。
雖然已經描述和解釋了特定的實施例，但是應當理解的是可以對本發明做出多種改變、改進和變型及其組合而不偏離本發明的範圍。例如，在基板的堆疊結構中，可以通過形成圖案化的通孔層連接一導電線路層與另一相隔二層或多層的導電線路層，此特徵將提供多一級的互連佈線，而傳統的導線架則是 不可能達到的。
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和區域內，當可作各種之更動與潤飾。因此，本發明之保護區域當視後附之申請專利區域所介定者為準。
105a‧‧‧基板
110b‧‧‧加強環、環狀載體
114a‧‧‧導電線路層、第一導電線路層、導電佈線
218a‧‧‧相互連接件
224‧‧‧黏合層、第二導電種子層
228a‧‧‧第三導電線路層
228b‧‧‧選擇區域(最外部導電線路層)
230a‧‧‧焊接遮罩

Claims (17)

  1. 一種多層半導體基板，包括：一犧牲載體(sacrificial carrier)，係為電性導電且可化學蝕刻；一第一導電線路層(first conductor trace layer)，形成於該犧牲載體上；一第二導電線路層(second conductor trace layer)；以及一第一相互連接層(first interconnect layer)，設置於第一及第二導電線路層間，其中間柱(stud)連接介於第一及第二導電線路層間之選擇區域。
  2. 如申請專利範圍第1項所述之多層半導體基板，其中該第一導電線路層及該第一相互連接層係封裝於一樹脂封膠複合物(resin molding compound)內。
  3. 如申請專利範圍第2項所述之多層半導體基板，其中該樹脂封膠係為研磨平面用以暴露複數第一相互連接間柱(first interconnect stud)，一研磨表面(ground surface)被沉積一導電種子層(conductor seed layer)。
  4. 如申請專利範圍第3項所述之多層半導體基板，其中該導電種子層係建立於一黏合層(adhesion layer)上用以增加該第二 導電線路層之黏合性。
  5. 如申請專利範圍第4項所述之多層半導體基板，其中該黏合層包括一聚亞醯氨(polyimide)或一編織玻璃纖維(woven glass fiber laminate)。
  6. 如申請專利範圍第3或4項所述之多層半導體基板，更包括一第二絕緣層，該第二絕緣層沉積於該第二導電線路層上，使得該第二導電線路層被選擇性移除以暴露該第二導電線路層之區域，該第二導電線路層之區域用以外部電性連接。
  7. 如申請專利範圍第3或4項所述之多層半導體基板，更包括一或多個中間堆疊層，各該中間堆疊層包括一導電線路元件層(conductor trace component layer)及一相互連接間柱元件層(interconnect stud component layer)，且各堆疊層被封裝於一樹脂封膠複合物(resin molding compound)內，使得一封膠表面係為研磨面並以一導電種子層沉積。
  8. 如申請專利範圍第6或7項所述之多層半導體基板，其中該犧牲載體之一內部部份被蝕刻以使得剩餘一強化載體環(reinforcement carrier ring)於該犧牲載體之周圍區域或於一組導電佈線周圍。
  9. 一種製造一多層基板之方法，該多層基板用於半導體封裝結構，該方法包括：形成一第一導電線路層(first conductor trace layer)於一犧牲載體(sacrificial carrier)上，其中該第一導電線路層包括複數導電佈線(conductor layout)；形成一相互連接層(interconnect layer)於該第一導電線路層上，其中該相互連接層包括複數間柱(stud)，該些間柱連接該第一導電線路層之選擇區域；封裝該第一導電線路層及該相互連接層於一樹脂封膠複合物(resin molding compound)中；研磨一封膠封裝體(molded encapsulation)之一表面為平面且用以暴露該些相互連接間柱；設置一黏合層(adhesion layer)於該研磨封裝體表面上；重複上述步驟以形成該多層基板之一額外堆疊結構，以形成二或多個堆疊結構層(built-up structural layer)；以及形成一最外部導電線路層(outermost conductor trace layer)於該黏合層之頂部上。
  10. 如申請專利範圍第9項所述之方法，其中該樹脂封膠複合物包括一樹脂及二氧化矽填充物(silica filler)。
  11. 如申請專利範圍第9或10項所述之方法，其中研磨之步驟包括暴露該二氧化矽填充物以增加下一連續層之黏合性。
  12. 如申請專利範圍第9或10項所述之方法，其中該研磨之步驟包括使該二氧化矽填充物產生一凹陷表面，該凹陷表面用以增加下一連續層之黏合性。
  13. 如申請專利範圍第9至12項中其中一項所述之方法，其中設置該黏合層之步驟包括設置一導電種子層(conductor seed layer)、一聚亞醯氨(polyimide layer)或一編織玻璃纖維(woven glass fiber laminate)。
  14. 如申請專利範圍第9項所述之方法，更包括：以一絕緣層密封該最外部導電線路層；以及選擇性移除該絕緣層以暴露該最外部導電線路層之區域，該最外部導電線路層之區域用以外部電性連接。
  15. 如申請專利範圍第14項所述之方法，更包括一移除該犧牲載體之一內部部分以暴露該第一導電線路層並留下一加強環(reinforcing ring)於該犧牲載體之部份周圍或一組導電佈線(conductor layout)周圍，該組導電佈線位於該第一導電線路層上。
  16. 如申請專利範圍第15項所述之方法，更進一步密封一焊接遮罩(soldermask)於該第一導電線路層並選擇性移除該焊接遮罩以暴露該第一導電線路層之區域，該第一導電線路層之區域用以外部電性連接。
  17. 一種多層基板，係由申請專利範圍第9至16項之其中一項所述之方法所獲得，其中該導電線路層被界定來傳輸個別訊號及/或電源。
TW102110736A 2012-03-26 2013-03-26 半導體基板、半導體封裝件及其製造方法 TWI694557B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201261615399P 2012-03-26 2012-03-26
US61/615,399 2012-03-26

Publications (2)

Publication Number Publication Date
TW201349397A true TW201349397A (zh) 2013-12-01
TWI694557B TWI694557B (zh) 2020-05-21

Family

ID=48325844

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102110736A TWI694557B (zh) 2012-03-26 2013-03-26 半導體基板、半導體封裝件及其製造方法

Country Status (9)

Country Link
US (2) US10049950B2 (zh)
JP (2) JP6436396B2 (zh)
KR (1) KR20140147091A (zh)
CN (2) CN104254917B (zh)
MY (1) MY171427A (zh)
PH (1) PH12014502113A1 (zh)
SG (1) SG11201405931PA (zh)
TW (1) TWI694557B (zh)
WO (1) WO2013147706A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI710292B (zh) * 2018-12-19 2020-11-11 大陸商慶鼎精密電子（淮安）有限公司 電路板及其製作方法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015081141A1 (en) * 2013-11-26 2015-06-04 Diodes Incorporation A chip scale package
TWI541963B (zh) * 2014-05-30 2016-07-11 恆勁科技股份有限公司 封裝基板及其製作方法
TWI591762B (zh) * 2014-06-30 2017-07-11 恆勁科技股份有限公司 封裝裝置及其製作方法
US20180261535A1 (en) * 2014-12-15 2018-09-13 Bridge Semiconductor Corp. Method of making wiring board with dual routing circuitries integrated with leadframe
JP6444269B2 (ja) * 2015-06-19 2018-12-26 新光電気工業株式会社 電子部品装置及びその製造方法
JP6750202B2 (ja) 2015-10-14 2020-09-02 味の素株式会社 樹脂組成物、接着フィルムおよびコアレス基板の製造方法
US10411329B2 (en) 2016-01-20 2019-09-10 Apple Inc. Packaged devices with antennas
MY172923A (en) * 2016-03-31 2019-12-13 Twisden Ltd Integrated circuit package having pin up interconnect
US20170287838A1 (en) 2016-04-02 2017-10-05 Intel Corporation Electrical interconnect bridge
JP7063718B2 (ja) * 2018-05-17 2022-05-09 エイブリック株式会社 プリモールド基板とその製造方法および中空型半導体装置とその製造方法
US10755994B2 (en) * 2018-10-29 2020-08-25 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor substrate
CN109731798B (zh) * 2019-01-25 2021-04-20 南京航空航天大学 镍叠片的分拣储存方法
CN112242476B (zh) * 2019-07-16 2022-03-18 佛山市国星光电股份有限公司 一种led显示单元组及显示面板

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4108986A1 (de) 1990-03-19 1991-09-26 Hitachi Ltd Zusammengeschaltete, mehrschichtige platten und verfahren zu ihrer herstellung
IL128200A (en) * 1999-01-24 2003-11-23 Amitec Advanced Multilayer Int Chip carrier substrate
JP3592129B2 (ja) * 1999-04-15 2004-11-24 新光電気工業株式会社 多層配線基板の製造方法
JP3446818B2 (ja) * 1999-05-10 2003-09-16 日本電気株式会社 半導体装置の実装構造、及びその製造方法
US6221693B1 (en) * 1999-06-14 2001-04-24 Thin Film Module, Inc. High density flip chip BGA
US6861345B2 (en) * 1999-08-27 2005-03-01 Micron Technology, Inc. Method of disposing conductive bumps onto a semiconductor device
JP3548082B2 (ja) * 2000-03-30 2004-07-28 三洋電機株式会社 半導体装置及びその製造方法
US20020016139A1 (en) * 2000-07-25 2002-02-07 Kazuto Hirokawa Polishing tool and manufacturing method therefor
JP2002198656A (ja) * 2000-12-25 2002-07-12 Sony Corp 高密度実装用基板の製法
JP4507424B2 (ja) * 2001-02-28 2010-07-21 住友ベークライト株式会社 半導体装置の製造方法
JP2002261190A (ja) * 2001-02-28 2002-09-13 Sony Corp 半導体装置、その製造方法及び電子機器
JP5017750B2 (ja) 2001-06-04 2012-09-05 日立化成工業株式会社 接続基板とその接続基板を用いた多層配線板と接続基板の製造方法とその方法を用いた多層配線板の製造方法
JP3880397B2 (ja) * 2001-12-27 2007-02-14 日東電工株式会社 保護テープの貼付・剥離方法
TWI248190B (en) * 2004-03-18 2006-01-21 Siliconware Precision Industries Co Ltd Integrated circuit substrate with conductive ring and semiconductor device integrated with the substrate
JP4063240B2 (ja) * 2004-04-21 2008-03-19 日本電気株式会社 半導体装置搭載基板とその製造方法、並びに半導体パッケージ
CA2582022C (en) * 2004-09-30 2021-05-18 Vanda Pharmaceuticals, Inc. Methods for the administration of iloperidone
JP2006108211A (ja) * 2004-10-01 2006-04-20 North:Kk 配線板と、その配線板を用いた多層配線基板と、その多層配線基板の製造方法
JP2006318964A (ja) * 2005-05-10 2006-11-24 Sanyo Epson Imaging Devices Corp 配線基板の製造方法、配線基板および電気光学装置
US7838779B2 (en) * 2005-06-17 2010-11-23 Nec Corporation Wiring board, method for manufacturing same, and semiconductor package
IL171378A (en) * 2005-10-11 2010-11-30 Dror Hurwitz Integrated circuit support structures and the fabrication thereof
US7911038B2 (en) * 2006-06-30 2011-03-22 Renesas Electronics Corporation Wiring board, semiconductor device using wiring board and their manufacturing methods
DE102007034402B4 (de) 2006-12-14 2014-06-18 Advanpack Solutions Pte. Ltd. Halbleiterpackung und Herstellungsverfahren dafür
JP4073945B1 (ja) * 2007-01-12 2008-04-09 新光電気工業株式会社 多層配線基板の製造方法
US7638814B2 (en) * 2007-06-19 2009-12-29 Philips Lumileds Lighting Company, Llc Solderless integrated package connector and heat sink for LED
JP4993739B2 (ja) * 2007-12-06 2012-08-08 新光電気工業株式会社 配線基板、その製造方法及び電子部品装置
US8154121B2 (en) * 2008-02-26 2012-04-10 Intel Corporation Polymer interlayer dielectric and passivation materials for a microelectronic device
KR101383434B1 (ko) * 2008-07-31 2014-04-08 세키스이가가쿠 고교가부시키가이샤 에폭시 수지 조성물, 프리프레그, 경화체, 시트상 성형체, 적층판 및 다층 적층판
US9847268B2 (en) * 2008-11-21 2017-12-19 Advanpack Solutions Pte. Ltd. Semiconductor package and manufacturing method thereof
JP5339928B2 (ja) * 2009-01-15 2013-11-13 新光電気工業株式会社 配線基板及びその製造方法
TWI466278B (zh) * 2010-04-06 2014-12-21 Kingpak Tech Inc 晶圓級影像感測器構裝結構及其製造方法
US8609995B2 (en) * 2010-07-22 2013-12-17 Ngk Spark Plug Co., Ltd. Multilayer wiring board and manufacturing method thereof
CN102299082B (zh) * 2010-08-31 2014-04-16 先进封装技术私人有限公司 半导体承载元件的制造方法及应用其的封装件的制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI710292B (zh) * 2018-12-19 2020-11-11 大陸商慶鼎精密電子（淮安）有限公司 電路板及其製作方法

Also Published As

Publication number Publication date
WO2013147706A1 (en) 2013-10-03
US20150155214A1 (en) 2015-06-04
JP6436396B2 (ja) 2018-12-12
US20180323121A1 (en) 2018-11-08
MY171427A (en) 2019-10-12
CN104254917B (zh) 2019-04-09
JP2019050397A (ja) 2019-03-28
CN109920774A (zh) 2019-06-21
PH12014502113A1 (en) 2014-12-10
US10049950B2 (en) 2018-08-14
CN104254917A (zh) 2014-12-31
SG11201405931PA (en) 2014-10-30
JP2015518651A (ja) 2015-07-02
KR20140147091A (ko) 2014-12-29
TWI694557B (zh) 2020-05-21
US10446457B2 (en) 2019-10-15

Similar Documents

Publication Publication Date Title
TWI694557B (zh) 半導體基板、半導體封裝件及其製造方法
TWI607531B (zh) 底部元件限制於介電材凹穴內之封裝疊加半導體組體
CN109937476B (zh) 晶片级封装和方法
CN110660680B (zh) 半导体结构的形成方法
TWI538065B (zh) 半導體三維封裝體、半導體結構及其製作方法
TWI426586B (zh) 具有用於將焊墊鍍於晶片下方之導線的球柵陣列封裝
TWI538137B (zh) 具有單側基板設計的半導體封裝及其製造方法
JP2019512168A (ja) シリコン基板に埋め込まれたファンアウト型の３ｄパッケージ構造
US20080284017A1 (en) Methods of fabricating circuit board and semiconductor package, and circuit board and semiconductor package fabricated using the methods
CN107346766A (zh) 整合扇出型封装及其制造方法
KR20170004917A (ko) 칩 패키지
TW201834085A (zh) 封裝堆疊結構及其製造方法
TWI651788B (zh) 電子結構以及電子結構陣列
CN110858576A (zh) 覆晶封装基板及其制法
US20140167276A1 (en) Substrate for semiconductor package, semiconductor package using the substrate, and method of manufacturing the semiconductor package
WO2022095695A1 (zh) Mcm封装结构及其制作方法
TW202010077A (zh) 覆晶封裝基板及其製法
US9842827B2 (en) Wafer level system in package (SiP) using a reconstituted wafer and method of making
TWI550732B (zh) 晶片封裝結構的製作方法
TWI512921B (zh) 載板結構與晶片封裝結構及其製作方法
US20240030099A1 (en) Semiconductor structure and manufacturing method thereof
TWI484572B (zh) 導電凸塊的製造方法及線路基板
TW202320276A (zh) 半導體基板結構及其製造方法
KR20070078954A (ko) 반도체 패키지용 기판 제조방법