JP6436396B2 - 半導体パッケージング用の多層基板および多層基板を製造する方法 - Google Patents
半導体パッケージング用の多層基板および多層基板を製造する方法 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims description 91
- 238000000034 method Methods 0.000 title claims description 36
- 239000004065 semiconductor Substances 0.000 title claims description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000004806 packaging method and process Methods 0.000 title description 4
- 239000010410 layer Substances 0.000 claims description 220
- 239000004020 conductor Substances 0.000 claims description 154
- 239000012212 insulator Substances 0.000 claims description 49
- 238000000465 moulding Methods 0.000 claims description 31
- 150000001875 compounds Chemical class 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 239000000945 filler Substances 0.000 claims description 12
- 239000012790 adhesive layer Substances 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 239000011347 resin Substances 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 6
- 230000003014 reinforcing effect Effects 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 4
- 239000003365 glass fiber Substances 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- 238000009713 electroplating Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 239000002131 composite material Substances 0.000 description 4
- 229910000831 Steel Inorganic materials 0.000 description 3
- 238000003486 chemical etching Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 239000012530 fluid Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000010959 steel Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000011573 trace mineral Substances 0.000 description 2
- 235000013619 trace mineral Nutrition 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012876 carrier material Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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Description
Claims (18)
- 多層半導体基板であって、以下の
導電性を有し、化学エッチングが可能な犠牲キャリア、
半導体ダイとの接続のための、複数の第1の導体レイアウトを含んだパターン化された第1の導体トレース層であって、前記犠牲キャリアの上に形成されたパターン化された第1の導体トレース層、
導電性のスタッドビアで構成された第1の相互接続層であって、パターン化された前記第1の導体トレース層上に形成された第1の相互接続層、
成形コンパウンドを備えた第1の絶縁体層であって、パターン化された前記第1の導体トレース層と前記第1の相互接続層を封入する第1の絶縁体層、
前記第1の絶縁体層の研磨された表面に形成された導体シード層、
半導体ダイとの接続のための、複数の第2の導体レイアウトを備えた、パターン化された第2の導体トレース層であって、前記導体シード層の上に形成されたパターン化された第2の導体トレース層、および
前記導体シード層およびパターン化された前記第2の導体トレース層を封入する第2の絶縁体層、を備え、
形成された多層半導体基板において、前記第1の導体レイアウトが前記第1の絶縁体層の表面とともに露出する、多層半導体基板。 - 前記第1の導体トレース層、および第1の相互接続層が、前記成形コンパウンドに封入される、請求項1に記載の多層半導体基板。
- 前記成形コンパウンドの表面に前記第1の相互接続層のスタッドビアが露出し、前記成形コンパウンドの表面が前記導体シード層で覆われている、請求項2に記載の多層半導体基板。
- 前記導体シード層が接着層上に作製されて、前記第2の導体トレース層の接着を改善する、請求項3に記載の多層半導体基板。
- 前記接着層が、ポリイミドまたは編組み状のガラス・ファイバの積層板を含む、請求項4に記載の多層半導体基板。
- 外部との電気接続のために、前記第2の絶縁体層が、選択的に除去されて、前記第2の導体トレース層の領域を露出させるよう動作可能である、請求項3または4に記載の多層半導体基板。
- 1つまたは複数の中間ビルドアップ層をさらに備え、各中間ビルドアップ層が、導体トレースの構成要素層および相互接続スタッドビアの構成要素層を含み、各中間ビルドアップ層が前記成形コンパウンド内に封入され、研磨された成形コンパウンドの表面が導体シード層で覆われている、請求項3または4に記載の多層半導体基板。
- 前記犠牲キャリアの内部がエッチング除去され、その結果、補強キャリア・リングが多層半導体基板の周辺領域上、または1組の導体レイアウトの周りに残る、請求項6または7に記載の多層半導体基板。
- 半導体パッケージ用の多層基板を製造する方法であって、以下のステップすなわち、
パターン化された第1の導体トレース層を犠牲キャリア上に形成するステップであって、パターン化された前記第1の導体トレース層が、半導体ダイと接続するための複数の導体レイアウトを含むステップ、
相互接続層をパターン化された前記第1の導体トレース層上に形成するステップであって、前記相互接続層が、パターン化された前記第1の導体トレース層の選択された領域と接続する導電性スタッドビアを備えるステップ、
パターン化された前記第1の導体トレース層および前記相互接続層を成形コンパウンド内に封入して第1の絶縁体層を形成するステップと、
前記第1の絶縁体層の表面を、平坦化し、すべての導電性スタッドビアが研磨された表面に露出する深さまで研磨するステップ、
前記第1の絶縁体層の研磨された表面に導体シード層を形成するステップ、
前記導体シード層の上にパターン化された第2の導体トレース層を形成するステップであって、パターン化された前記第2の導体トレース層は半導体ダイと接続するための複数の第2の導体レイアウトを含むステップ、
前記導体シード層とパターン化された前記第2の導体トレース層を成形コンパウンドを用いて、封入し、第2の絶縁体層を形成するステップ、および
前記第2の絶縁体層形成後、犠牲キャリアの内側部部分を部分的に取り除くステップであって、前記犠牲キャリアの輪が残り、前記第1の導体トレース層の導体レイアウトが前記第1の絶縁体層の表面とともに外部に露出するステップ、を含む方法。 - 前記成形コンパウンドが、樹脂充填剤およびシリカ充填剤を含む、請求項9に記載の方法。
- 前記第1の絶縁体層の研磨が、シリカ充填剤を露出させて次の隣接した層の接着を改善するステップを含む、請求項9または10に記載の方法。
- 前記第1の絶縁体層の研磨が、表面のシリカ充填剤を抽出し、凹んだ表面を形成して、次の隣接した層の接着を改善するステップを含む、請求項9または10に記載の方法。
- さらに前記第1の絶縁体層の研磨された表面へ接着層を付着させるステップを含み、前記接着層はポリイミド層、または編組み状のガラス・ファイバである、請求項9〜12のいずれか一項に記載の方法。
- 最も外側の導体トレース層を絶縁体層で封止するステップと、
外部との電気接続のために、前記絶縁体層を選択的に除去して、前記最も外側の導体トレース層の領域を露出させるステップと
をさらに含む、請求項9に記載の方法。 - 前記犠牲キャリアの内側部部分を部分的に取り除くステップにおいて、取り除かれなかった犠牲キャリアの部分が、前記基板の周辺の周り、または前記第1の導体トレース層に配置された1組の導体レイアウトの周りに位置する補強リングを構成する、請求項14に記載の方法。
- 前記第1の導体トレース層上にソルダーマスクを封止するステップと、外部との電気接続のために、前記ソルダーマスクを選択的に除去して、前記第1の導体トレース層の領域を露出させるステップとをさらに含む、請求項15に記載の方法。
- 前記ステップを繰り返して、多層基板に追加のビルドアップ層を形成し、2層以上のビルドアップ層を備える、請求項9に記載の方法。
- 前記第1および第2の導体トレース層が、別々の信号および/または電力のタイプを運ぶように画定される、請求項1〜8のいずれか一項に記載の多層半導体基板。
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