CN104254917A - 用于半导体封装的多层基底 - Google Patents

用于半导体封装的多层基底 Download PDF

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CN104254917A
CN104254917A CN201380021583.XA CN201380021583A CN104254917A CN 104254917 A CN104254917 A CN 104254917A CN 201380021583 A CN201380021583 A CN 201380021583A CN 104254917 A CN104254917 A CN 104254917A
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layer
conductive traces
substrate
conductor
interconnection
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CN104254917B (zh
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林少雄
周辉星
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Advanpack Solutions Pte Ltd
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Abstract

本发明提供半导体基底(105、105a)，其包括形成在牺牲性载体(110)上的两层或多层堆积的结构层(120、220)。每个堆积的结构层包括导体迹线层(114a)和互连层(118a、218a)，结构层模制在树脂模塑料内。该模塑料的顶表面被研磨，然后，由粘合层(123、124、224)沉积。然后在最外面的导体迹线层(128a、228a)形成在粘合层上且载体(110)或加强环(110b)被移去之后，可以获得多层基底(105、105a)。

Description

用于半导体封装的多层基底
技术领域
本发明涉及用于半导体封装的多层基底以及制造此类基底的方法。
背景技术
传统的半导体芯片安装在引线框架上。这些引线框架通常这样形成：用光阻材料层涂敷铜基底，使用掩模暴露出光阻材料层上的图案，积极或消极地除去光阻材料层，然后蚀刻掉铜以给出刻有图案的引线框架。然而，此类通过蚀刻形成的带有图案的引线框架不适合与需要比传统引线框架更细且更紧密的互连迹线的芯片一起使用。蚀刻过程固有地会造成底切，对于高产量的制造来说，由此形成的细导线迹线可能具有可靠性问题。
授予新加坡先进封装私人有限公司(Advanpack Solutions)的美国专利第7,795,071号描述了形成用于半导体封装的单层带图案基底的方法。一组带图案的导体布局形成在钢载体上，将绝缘材料注入到模具内以密封导电迹线。移去钢载体之后，含有一组图案的导体布局的基底便形成。有利的是，带图案的导体布局彼此电气绝缘，而在传统引线框架上，对应于每个芯片的每个导体布局电气地连接到邻近的布局上。
由此可以看到，需要形成具有更加复杂导电迹线的布线的多层基底，以支持集成电路的后续设计。有利的是，这些多层基底允许各独立的导体层用于信号、电源、数字/模拟电路等。
发明内容
下面给出简化的概述，以提供对本发明的基本理解。该概述不是本发明外延的综述，并不意图标识出本发明的关键特征。相反，将以一般化的形式给出本发明的发明构思中的一些，其作为下面的详细描述的前序。
本发明寻求提供基底，其含有形成在牺牲性载体上的两个或多个堆积的结构层。每个堆积的结构层包括导体迹线层和互连层。每个堆积的结构层模制在树脂化合物内。然后通过形成最外导体迹线层并移去载体，来完成该多层基底。
在一个实施例中，本发明提供多层基底，多层基底包括：牺牲性载体，其能够导电且能够被化学蚀刻；第一导体迹线层，其形成在牺牲性载体上；第二导体迹线层和设置在第一和第二导体迹线层之间的互连层，其中，短柱连接第一和第二导体迹线层之间的选定区域。
在多层基底的一个实施例中，第一导体迹线层和互连层被封装在树脂模塑料内。树脂模具的顶表面被研磨，粘合层沉积在研磨表面上。该粘合层可以是导体种子层、聚酰亚胺层或编织的玻璃纤维层叠物。多层基底因此包括两个或多个堆积层，每个堆积层由导体迹线层、互连层和粘合层组成，使得最外层是导体迹线层。
在另一实施例中，本发明提供制造多层半导体基底的方法。该方法包括：在牺牲性载体上形成第一导体迹线层，其中，第一导体迹线层包含多个导体布局；在第一导体迹线层上形成互连层，其中，互连层包括短柱，短柱与第一导体迹线层的选定区域连接；将第一导体迹线层和互连层封装在树脂模塑料内；将已模制的封装表面研磨成平面并暴露出互连的短柱；将粘合层沉积在已磨削的封装表面上；重复以上步骤以形成多层基底的附加的堆积结构，使得有2个或更多个堆积的结构层；以及在顶部粘合层上形成最外导体迹线层。
在另一实施例中，该方法还包括：用绝缘材料密封最外导体迹线层；选择性地移去绝缘层以暴露出最外导体迹线层的区域，以用于外部的电气连接。
较佳地，除去载体的内部部分，以留下位于基底周围或包含在第一导体迹线层内的一组导体布局周围的加强环。较佳地，第一导体迹线层用阻焊掩模密封，并且选择性地移去阻焊掩模以暴露第一导体迹线层上的用于外部电气连接的区域。
附图说明
参照附图，现将借助于本发明非限制性实施例来描述本发明，附图中：
图1A至图1J示出根据本发明实施例的两层基底的结构；
图2A至图2D、图3和图4示出使用图1J所示的多层基底来形成半导体封装的方法；
图5和图6示出根据本发明另一实施例的两层基底的结构；
图7A至图7F示出根据本发明还有另一实施例的三层基底的结构；
图8示出根据本发明获得的最终基底的平面图。
具体实施方式
现将参照附图，描述本发明一个或多个具体的和可替换的实施例。然而，本技术领域内技术人员将会明白，本发明也可在没有此类具体细节的情况下来实践。某些细节可不作详细描述以免模糊本发明。为便于参考，当参照附图共有的相同或相似特征时，在全部的附图中将使用共同的附图标记或系列标记。
图1A-1J示出根据本发明的实施例的多层基底105逐步形成过程，该多层基底105包括两层导体迹线。如图1A所示，工艺100中的第一步骤是提供具有第一表面和相反面向的第二表面的载体110。较佳地，该载体110由具有较高杨氏弹性模量的低成本材料制成，载体110是导电的并适合于化学蚀刻，如钢。在多层基底105制造过程中和/或完全在半导体芯片10封装之后，该载体110的这些特性允许其被牺牲性地部分移除。较佳地，载体110例如通过退火来进行应力释放或部分应力释放。
其后的工艺步骤包括用光阻材料涂敷载体110的表面，使用掩模暴露出光阻材料，选择性地蚀刻光阻材料，并获得带图案的光阻材料。通过将诸如铜等第一导电材料114沉积在带图案的光阻材料上，然后移去光阻材料，带图案的第一导体迹线层114a便形成在载体110上。带图案的第一导体迹线层114a因此含有多个用于与某些半导体芯片连接的第一导体布局。较佳地，第一导电材料114是铜，并且合适的沉积工艺是电镀。图1B示出通过第一导体迹线层114a的截面的放大图。为了更便于参照，带图案的第一导体迹线层或第一导体布局用同样的附图标记114a表示。通过光刻工艺并通过将第二导体材料118沉积在限定互连通路的生成的带图案光阻材料上，由导体短柱118组成的第一互连层118a因此形成在第一导体迹线层114a上，如图1C所示。可替换地，第一导体迹线层114a和第一互连层118a通过减色光刻工艺形成。可采用加色、半加色或半减色工艺的各种组合来形成所要求的图案结构。为了电隔离导体迹线并将导体迹线/短柱包裹在绝缘材料内，将一组第一导体布局114a和第一导体短柱118a设置在一内腔中，或将多组第一导体布局114a和导体短柱118a设置在多个内腔中。优选地预热到流体状态的绝缘的或介电的模塑料(模制化合物或模制复合物)在熔化温度下注入到该内腔或多个内腔中，较佳地，以正压力注入流体模塑料，使得模塑料致密地封装该组第一导体布局114a和导体短柱118a，从而在模塑料固化之后，形成致密的复合结构或第一绝缘体层120；由此，模塑料牢固地粘结到第一导体布局114a和导体短柱118a上，这样，在湿法处理过程中，流体不能进入导体－模塑料接口。如图1D所示，由此获得了半成品基底。较佳地，第一绝缘体层120包括含有树脂基体和二氧化硅填料的模塑料。较佳地，在第一绝缘体层120形成之后，二氧化硅填料被嵌入在树脂内。
如图1D所示的半成品基底被移入到机加工中心，通过研磨使第一绝缘体层120的自由表面形成平面，如图1E所示，研磨的深度达到所有导体短柱118a都暴露在磨削表面122上。较佳地，导体短柱118a的暴露表面与第一绝缘体层120的后表面齐平或凹入该后表面(如图1E所示)，使得第一绝缘体层120限定导体短柱的边缘，并使导体短柱彼此隔离。磨削之后，模塑料中的二氧化硅填料也暴露出来。具体来说，磨削表面122现包括内置有二氧化硅填料的树脂；形成磨削表面122以为沉积导体种子层124提供强附着力，如图1F所示。可替换地，通过在研磨过程中提高材料移除速率，表面二氧化硅填料从树脂中被提取出来，以在磨削表面122上形成多个坑。该带坑的磨削表面122提供了增大的表面面积以改进下一相邻层附着力堆积。如果第一导体材料114是铜，那么导体种子124的材料也是铜。用于沉积铜种子层124的合适方法是化学镀层、电镀层、喷溅镀层、化学气相沉积(CVD)或物理气相沉积(PVD)。
然后通过使用光刻工艺，带图案的光阻材料形成在导体种子层124上，并通过将铜电镀到带图案的光阻材料上，获得带图案的第二导体迹线层128a，如图1G所示。第二导体迹线层128a由多个第二导体布局128a组成；这些第二导体布局128a的每个因此通过相关的第一导体短柱118a电气地连接到各个相关的第一导体布局层114a。
如图1H所示，带图案的第二导体迹线层128a通过用第二绝缘层或介电层130密封它而完成。较佳地，第二绝缘层130是含有光可成像的聚合物材料的阻焊掩模。较佳地，第二绝缘层130被丝网印刷到带图案的第二导体迹线层128a上。然后第二绝缘层130通过掩模暴露于诸如激光辐照等辐照之下，并通过有选择的移除，第二导体迹线层128a的选定区域128b暴露出来，以用于外部的电气连接，如图1I所示。为有利于可焊接性，对暴露的第二导体迹线层128b上的进一步处理可包括沉积锡层或镍/金层。
如图1I所示，载体110大于模制的第一绝缘层120。有利的是，载体110的内部110a例如通过蚀刻等被部分地牺牲或移除，使得环110b被保持并获得最终基底105，如图1J所示。在移去载体110之后，第一导体布局114a连同第一绝缘体层120的表面一起暴露。较佳地，第一导体布局114a的表面与第一绝缘体层120的顶表面齐平或凹入该顶表面(如图1J所示)，使得第一绝缘体层120形成第一导体布局114a的边缘，并使第一导体布局彼此绝缘。如上所述，载体110是由较高的杨氏弹性模量材料制成，并经过应力释放；通过在基底105上留下载体的环110b，该载体环110b有助于保持多个最终基底105的平面性，同时，对最终基底105提供刚度，以便于操作和其后的加工。在另一实施例中，内部开口110a小于一组已模制的第一绝缘体层120，使得多个开口110a形成在载体110上，而不是只留下整个基底周围的载体环。此外，在模制区域120之外的周边区域内，载体环110b形成有定位或基准孔160(如图8中所示)；此外，如果载体110在使用前未进行应力释放，那么可以在将内部部分110a蚀刻掉之前，在周边区域内冲压或形成应力释放狭槽170(显示在图8中)。有利的是，载体的带有定位/基准孔或应力释放狭槽的周边区域，限定夹持区域，该夹持区域用于第一绝缘体层120的上述注射或压缩模制，最终半导体封装的分离，或用于其它中间制造过程中的其它使用，使得所需的夹持区域定位成远离含有第一和第二导体迹线和互连短柱的专用模制区域，因此，确保后续工艺不损坏已模制的区域。
为图示简单起见，图2A示出围绕已模制的第一绝缘体层120形成的载体环110b。如图2A所示，半导体芯片10通过焊料隆起20和金属柱24连接件连接到第一导体布局114a。底充化合物30也加强了芯片10的安装。在图2B中，在芯片10安装在基底105上之后，整个芯片被封装在模具40内。较佳地，模具40由具有与第一绝缘体层120材料相似或相同特性的材料制成，以使因特性差异形成的应力减到最小。焊球22也可设置成与暴露的第二导体布局128b接触，以用于外部的电气连接。在图2C中，将封装的芯片沿着分离线XX和YY切割，以提供含有通过本发明工艺100获得的基底105的最终半导体封装150。
替代焊料隆起连接的使用，如图3所示，芯片10可用引线联接到第一导体布局114a，并且通过上述工艺100获得含有基底105的另一最终半导体封装150a。此外，如图4所示，最终半导体封装150c可包括两个或多个芯片、钝化模(passives)或封装，其包括使用不同半导体制造技术制成的芯片。
返过来参照图1J和2C，位于每个第一导体布局114a周围的某些周边导体114b不电连接到第一导体布局114a的其余部分，并设置成控制电镀。例如，导体114b可起作“电流偷盗者(current stealer)”，以在短柱118和/或第二导体迹线层128a的电镀过程中改变电流的分布以达到均匀的电镀厚度。可替换地，导体114b设置成通过改变整个基底区域的热膨胀的复合系数(CTE)来改变基底105上的应力分布。
图5和图6示出上述实施例结构中的变化。例如，如图5所示，在布置导体种子层124之前，将粘合层123施加到已模制的第一绝缘体层120的磨削表面122上，以促进第二导体迹线层128a的粘结。较佳地，粘合层123是聚酰亚胺或编织玻璃纤维层叠物。在图6中，基底105的顶表面沉积有阻焊掩模140，使得第一导体迹线层114a的选定区域暴露来以用于外部电气连接。
图7A-7F示出包括三个导体迹线层的多层基底105a的逐步形成过程。图7A示出图1G中所示半成品基底结构的继续形成过程。如图7A所示，第二互连层218包括各第二导体短柱218，该第二互连层218通过光刻和电镀工艺形成在带图案的第二导体迹线层128上。在图7B中，通过化学蚀刻除去未堆积有第二导体迹线层128a的导体种子层124。
在图7C中，在半成品基底上的第一绝缘体层120由第二绝缘体模具220进行包覆模制。如在第一绝缘体层中那样，第二绝缘体模具也包含树脂基底或嵌入的无机二氧化硅填料。第二绝缘体模具220可与第一绝缘体层120具有相同的尺寸。如图7C所示，第二绝缘体模具220较大，并且其在所谓的模制-包覆模制过程中封装第一绝缘体层120。
如图1E所示，将第二绝缘体模具220的自由表面进行研磨以提供平坦表面222。该研磨过的模具表面222还对待要沉积的第二导体种子层224和待要堆积的第三导体迹线层228a提供良好的附着。如果第三导体迹线层228a是最终基底的最外导体迹线层，那么该最外导体迹线层用阻焊掩模密封，然后如图7F所示，暴露出该最外导体迹线层的选定区域，以用于外部的电气连接。
在图7E中，图中示出载体110的内部被部分地蚀刻掉以暴露出第一导体迹线层114a，使得在完成对基底的处理之前，加强环110b保持在基底105a上。加强环110b可在对基底105a的处理完成之后才形成。生成的基底105a包括彼此毗邻的多个绝缘体层，其中每个绝缘体层都具有对应的(导体元件)导体迹线层和嵌入在其内的互连层。平行于毗邻绝缘层的接触表面的划分平面位于两个绝缘体层之间，使得一个绝缘体层内的导体迹线元件不会越过该划分平面到达邻近的绝缘体层。然而，在每个对应绝缘体层内的导体迹线元件彼此电气地连接，以使基底105a的顶表面电气地连接到基底后表面。具体来说，一个绝缘体层内的互连层电气地和物理地连接到毗邻绝缘层的导体迹线层。
图8示出根据图1J或图7F从顶部看所得到的基底105、105a的俯视图。如图8所示，通过载体110内的开口110a，第一导体迹线层114a示出，一组9个的导体布局114a被封装在模具120、220内。如先前所描述的，在各个导体布局114a内，存在有独立的导体114b，其设置为“电流偷盗者”以在电镀过程中用来调整电流分布；此外，这些独立的导体114b可用来修改整个基底的热膨胀复合系数，以使因处理过程中热变化引起的任何翘曲减到最小。位于基底105、105a周围的夹持区域中，即，在加强环110b的整个厚度上，存在有定位或基准孔160和应力释放狭槽170。
以上附图示出了带有2个或3个导体迹线层的多层基底的形成过程。通过形成带有导体迹线层和互连短柱层的各附加堆积层并将这些两个部件层封装在树脂模塑料内，可以获得带有3个以上导体迹线层的多层基底。通过本发明，多层基底允许较复杂的互连布线以支持新的半导体芯片的封装。有利的是，多层导体迹线还可分开地被指定为运载不同类型的信号或功率(电力)，例如，用以减低信号干扰。由于导体布局的特征尺寸不受限于蚀刻特征，所以，根据本发明的多层基底还在实现电路小型化中提供了进步。
尽管已经描述和图示了具体的实施例，但应该理解到，在不脱离本发明的范围的情形下，对本发明还可作出许多改变、修改、变型和其组合。例如，可形成带图案通道层，以在该基底的堆积结构中将一导体迹线层和定位在两层或多层远处的导体迹线层进行连接；该特征将会提供附加程度的互连布线，其在传统引线框架中是不可能的。

Claims (17)

1.一种多层半导体基底，所述多层半导体基底包括：
牺牲性载体，其能够导电且能够进行化学蚀刻；
第一导体迹线层，其形成在所述牺牲性载体上；
第二导体迹线层；以及
(第一)互连层，其设置在所述第一导体迹线层和所述第二导体迹线层之间，其中，短柱连接所述第一导体迹线层和所述第二导体迹线层之间的选定区域。
2.如权利要求1所述的多层半导体基底，其特征在于，所述第一导体迹线层和(第一)互连短柱层封装在树脂模制化合物内。
3.如权利要求2所述的多层半导体基底，其特征在于，所述树脂模具被研磨以暴露所述(第一)互连短柱，然后，导体种子层沉积在已磨削的表面上。
4.如权利要求3所述的多层半导体基底，其特征在于，所述导体种子层形成在粘合层上，以促进所述第二导体迹线层的粘合。
5.如权利要求4所述的多层半导体基底，其特征在于，所述粘合层包括聚酰亚胺或编织的玻璃纤维层叠物。
6.如权利要求3或4所述的多层半导体基底，其特征在于，还包括沉积在所述第二导体迹线层上的第二绝缘层，使得所述第二绝缘层能够被操作以选择性地被移除，以暴露出所述第二导体迹线层的用于外部电连接的区域。
7.如权利要求3或4所述的多层半导体基底，其特征在于，还包括一个或多个中间堆积层，每个所述中间堆积层包括导体迹线部件层和互连短柱部件层，而每个所述堆积层封装在树脂模制化合物内，以使模制表面被研磨并且然后由导体种子层沉积。
8.如权利要求6或7所述的多层半导体基底，其特征在于，所述牺牲性载体的内部被蚀刻掉，以使加强载体环保持在所述基底的周边区域上或保持在一组导体布局的周围。
9.一种制造用于半导体封装的多层基底的方法，所述方法包括：
在牺牲性载体上形成第一导体迹线层，其中，所述第一导体迹线层包含多个导体布局；
在所述第一导体迹线层上形成互连层，其中，所述互连层包括与所述第一导体迹线层的选定区域连接的短柱；
将所述第一导体迹线层和所述互连层封装在树脂模制化合物内；
将已模制的封装表面研磨成平坦的并暴露互连的短柱；
将粘合层沉积在已磨削的封装表面上；
重复以上步骤以形成多层基底的附加堆积结构，使得存在2个或更多个堆积的结构层；以及
在顶部粘合层上形成最外导体迹线层。
10.如权利要求9所述的方法，其特征在于，所述树脂模制化合物包括树脂和二氧化硅填料。
11.如权利要求9或10所述的方法，其特征在于，研磨已模制的封装体包括暴露二氧化硅填料以促进下一相邻层的粘合。
12.如权利要求9或10所述的方法，其特征在于，研磨已模制的封装体包括取出表面二氧化硅填料，以形成凹坑表面来促进下一相邻层的粘合。
13.如权利要求9至12中任一项所述的方法，其特征在于，沉积所述粘合层包括沉积导体种子层、聚酰亚胺层或编织的玻璃纤维层叠物。
14.如权利要求9所述的方法，其特征在于，还包括：
用绝缘层密封所述最外导体迹线层；以及
选择性地移除所述绝缘层，以暴露所述最外导体迹线层的用于外部电连接的区域。
15.如权利要求14所述的方法，其特征在于，还包括移除所述牺牲性载体的内部，以暴露出所述第一导体迹线层并留出加强环，所述加强环位于所述基底的周界的周围或位于定位在所述第一导体迹线层内的一组导体布局的周围。
16.如权利要求15所述的方法，其特征在于，进一步地，将阻焊掩模密封在所述第一导体迹线层上，并选择性地移除所述阻焊掩模以暴露所述第一导体迹线层的用于外部电连接的区域。
17.如权利要求9至16中任一项所述获得的多层基底，其特征在于，所述导体迹线层被限定用于运载分离的信号和/或功率类型。
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