JP4993739B2 - 配線基板、その製造方法及び電子部品装置 - Google Patents
配線基板、その製造方法及び電子部品装置 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 230000003014 reinforcing effect Effects 0.000 claims description 159
- 239000000758 substrate Substances 0.000 claims description 54
- 230000002093 peripheral effect Effects 0.000 claims description 33
- 230000015572 biosynthetic process Effects 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 28
- 239000011347 resin Substances 0.000 claims description 22
- 229920005989 resin Polymers 0.000 claims description 22
- 239000012779 reinforcing material Substances 0.000 claims description 11
- 229920001187 thermosetting polymer Polymers 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 187
- 238000000034 method Methods 0.000 description 40
- 239000010949 copper Substances 0.000 description 16
- 239000010931 gold Substances 0.000 description 15
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 11
- 229910000679 solder Inorganic materials 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 7
- 238000007747 plating Methods 0.000 description 7
- 229910052759 nickel Inorganic materials 0.000 description 4
- 230000002787 reinforcement Effects 0.000 description 4
- 239000000654 additive Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000004850 liquid epoxy resins (LERs) Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000002815 nickel Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
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- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
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- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Description
(配線基板)
図7は第1の実施の形態の配線基板を示す断面図であり、図8は図7の配線基板の上面図である。図7は図8のII-II線に沿う断面図に相当する。
次に、図9(b)を参照して上述の配線基板102を用いた電子部品装置について説明する。図9(b)は、上述の配線基板102を用いた電子部品装置を示す断面図である。
図4〜図7は第1の実施の形態に係る配線基板の製造方法を示す断面図である。
次に、図9(a)、(b)を参照して上述の配線基板を用いた電子部品装置の製造方法について説明する。図9(a)、(b)は、上述の配線基板102を用いた電子部品装置の製造方法を示す断面図である。
図10は第2の実施の形態の配線基板103を示す上面図である。
Claims (8)
- 配線層と絶縁層とが交互に積層された配線形成領域と、前記配線形成領域の周囲の外周領域とを有し、前記外周領域に沿って連続して延在する第1補強材と、該第1補強材に係合し、厚さ方向に延在する第2補強材とを有する補強構造体を備えている配線基板であって、
前記第1補強材は、多層構造をなして各配線層の平面内に連続して延在し、かつ前記配線基板の各辺に沿うように形成された補強パターンであり、前記第2補強材は、異なる層の該補強パターンに挟まれた前記絶縁層に埋め込まれた補強柱であり、
前記補強パターン及び前記補強柱は前記配線形成領域を囲むように形成され、
前記配線基板は、一面側が電子部品実装面であり、他面側が外部装置実装面であることを特徴とする配線基板。 - 同じ前記層内で、前記補強パターンが複数、並行するように配置されていることを特徴とする請求項1に記載の配線基板。
- 同じ前記層内で、前記補強パターンが複数、格子を形成するように配置されていることを特徴とする請求項1に記載の配線基板。
- 前記配線形成領域では、異なる層の前記配線層同士が前記絶縁層に埋め込まれたビアにより接続され、
前記外周領域では、前記補強パターンが前記配線層と同層に、前記配線層と同じ材料、同じ厚さかつ同じ幅で形成され、前記補強柱が前記ビアと同じ材料で形成されていることを特徴とする請求項1乃至3のいずれか1項に記載の配線基板。 - 配線形成領域と、該配線形成領域を囲む外周領域とがそれぞれ配置される仮基板を準備する工程と、
前記仮基板上の配線形成領域に第1配線層を形成するとともに、前記外周領域に沿って連続して延在する第1補強パターンを形成する工程と、
前記第1配線層及び前記第1補強パターンの上に第1絶縁層を形成する工程と、
前記第1配線層上の前記第1絶縁層にビアホールを形成するとともに、前記第1補強パターン上の前記第1絶縁層に開口部を形成する工程と、
前記配線形成領域のビアホール内にビアを形成するとともに、前記外周領域の開口部内に前記ビアと同じ材料の補強柱を形成する工程と、
前記配線形成領域のビアと接続する第2配線層を前記第1絶縁層上に形成するとともに、前記外周領域に連続して延在し、前記補強柱に接続する第2補強パターンを前記第1絶縁層上に形成する工程と、
前記仮基板を除去する工程と、
を有することを特徴とする配線基板の製造方法。 - 前記第1補強パターンを形成する工程において、前記第1配線層と同じ材料、同じ厚さかつ同じ幅で該第1補強パターンを形成し、
前記第2補強パターンを形成する工程において、前記第2配線層と同じ材料、同じ厚さかつ同じ幅で該第2補強パターンを形成することを特徴とする請求項5記載の配線基板の製造方法。 - 請求項1乃至4の何れか1項に記載の配線基板と、
前記配線基板の最外層の配線層に接続された電子部品とを有することを特徴とする電子部品装置。 - 前記配線基板と前記電子部品との隙間に熱硬化性樹脂が充填されていることを特徴とする請求項7記載の電子部品装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2007315925A JP4993739B2 (ja) | 2007-12-06 | 2007-12-06 | 配線基板、その製造方法及び電子部品装置 |
US12/211,458 US8138424B2 (en) | 2007-12-06 | 2008-09-16 | Wiring substrate including a reinforcing structural body |
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JP2007315925A JP4993739B2 (ja) | 2007-12-06 | 2007-12-06 | 配線基板、その製造方法及び電子部品装置 |
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JP2009141121A JP2009141121A (ja) | 2009-06-25 |
JP2009141121A5 JP2009141121A5 (ja) | 2010-10-28 |
JP4993739B2 true JP4993739B2 (ja) | 2012-08-08 |
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KR100704919B1 (ko) * | 2005-10-14 | 2007-04-09 | 삼성전기주식회사 | 코어층이 없는 기판 및 그 제조 방법 |
US20100073894A1 (en) * | 2008-09-22 | 2010-03-25 | Russell Mortensen | Coreless substrate, method of manufacturing same, and package for microelectronic device incorporating same |
TWI393233B (zh) * | 2009-08-18 | 2013-04-11 | Unimicron Technology Corp | 無核心層封裝基板及其製法 |
JP5623308B2 (ja) | 2010-02-26 | 2014-11-12 | 日本特殊陶業株式会社 | 多層配線基板及びその製造方法 |
JP5638269B2 (ja) | 2010-03-26 | 2014-12-10 | 日本特殊陶業株式会社 | 多層配線基板 |
JP5566771B2 (ja) | 2010-05-18 | 2014-08-06 | 日本特殊陶業株式会社 | 多層配線基板 |
CN102376675B (zh) * | 2010-08-04 | 2015-11-25 | 欣兴电子股份有限公司 | 嵌埋有半导体元件的封装结构及其制法 |
JP5732238B2 (ja) * | 2010-11-29 | 2015-06-10 | シャープ株式会社 | 固体撮像装置および電子情報機器 |
US8595927B2 (en) * | 2011-03-17 | 2013-12-03 | Ibiden Co., Ltd. | Method for manufacturing multilayer printed wiring board |
US8841209B2 (en) * | 2011-08-18 | 2014-09-23 | International Business Machines Corporation | Method for forming coreless flip chip ball grid array (FCBGA) substrates and such substrates formed by the method |
TWI694557B (zh) * | 2012-03-26 | 2020-05-21 | 先進封裝技術私人有限公司 | 半導體基板、半導體封裝件及其製造方法 |
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JP5662551B1 (ja) | 2013-12-20 | 2015-01-28 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
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JP6428038B2 (ja) * | 2014-08-19 | 2018-11-28 | 株式会社デンソー | 回路基板 |
TWI595810B (zh) * | 2015-05-22 | 2017-08-11 | 欣興電子股份有限公司 | 封裝結構及其製作方法 |
CN106298707B (zh) * | 2015-06-05 | 2019-05-21 | 欣兴电子股份有限公司 | 封装结构及其制作方法 |
JP6505521B2 (ja) * | 2015-06-26 | 2019-04-24 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
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TWI641087B (zh) * | 2015-12-28 | 2018-11-11 | 矽品精密工業股份有限公司 | 電子封裝件及封裝用之基板 |
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JP3921756B2 (ja) * | 1997-10-06 | 2007-05-30 | 株式会社デンソー | プリント基板およびその製造方法 |
JP2001015638A (ja) * | 1999-06-30 | 2001-01-19 | Mitsumi Electric Co Ltd | Icパッケージの基板 |
JP2004288661A (ja) * | 2003-01-29 | 2004-10-14 | Kyocera Corp | 配線基板 |
JP2006270082A (ja) * | 2005-02-25 | 2006-10-05 | Kyocera Corp | 配線基板及びそれを用いた電子装置 |
WO2006120826A1 (ja) | 2005-05-12 | 2006-11-16 | Murata Manufacturing Co., Ltd. | セラミック多層基板 |
JP4452222B2 (ja) * | 2005-09-07 | 2010-04-21 | 新光電気工業株式会社 | 多層配線基板及びその製造方法 |
TWI290349B (en) * | 2005-12-30 | 2007-11-21 | Advanced Semiconductor Eng | Thermally enhanced coreless thin substrate with an embedded chip and method for manufacturing the same |
JP2009135162A (ja) * | 2007-11-29 | 2009-06-18 | Shinko Electric Ind Co Ltd | 配線基板及び電子部品装置 |
KR101067199B1 (ko) * | 2009-07-07 | 2011-09-22 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
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