TW201903992A - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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Publication number
TW201903992A
TW201903992A TW107109765A TW107109765A TW201903992A TW 201903992 A TW201903992 A TW 201903992A TW 107109765 A TW107109765 A TW 107109765A TW 107109765 A TW107109765 A TW 107109765A TW 201903992 A TW201903992 A TW 201903992A
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Taiwan
Prior art keywords
wafer
redistribution structure
protective layer
conductive
redistribution
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TW107109765A
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English (en)
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TWI662667B (zh
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張簡上煜
徐宏欣
林南君
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力成科技股份有限公司
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Publication of TW201903992A publication Critical patent/TW201903992A/zh
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Abstract

一種封裝結構，包括第一重佈線結構、晶片、絕緣密封體以及保護層。第一重佈線結構具有第一表面以及相對於第一表面的第二表面。晶片配置於第一重佈線結構的第一表面上，且具有主動面以及相對於主動面的背面。絕緣密封體密封晶片以及第一重佈線結構的第一表面。保護層直接地配置於晶片的背面上。另提供一種封裝結構的製造方法。

Description

封裝結構及其製造方法
本發明是有關於一種封裝結構，且特別是有關於一種具有保護層的封裝結構。
隨著科技突飛猛進，為了使產品更小、更輕、整合度更高以及更具市場競爭力，電子產品需要被設計得小巧輕盈。然而，隨著電子產品的體積日益縮小，電子晶片因斷裂（crack）與翹曲（warpage）而導致故障或失效的風險也越來越高。因此，如何將封裝結構做得越小但仍保持原有的可靠度與功能性，以降低成品的失效的風險乃此領域的一項挑戰。
本發明提供一種封裝結構及其製造方法，可降低晶片的封裝結構故障或失效的風險，並提升其可靠度。
本發明提供一種封裝結構，包括第一重佈線結構、晶片、絕緣密封體以及保護層。第一重佈線結構具有第一表面以及相對於第一表面的第二表面。晶片配置於第一重佈線結構的第一表面上，且具有主動面以及相對於主動面的背面。絕緣密封體密封晶片與第一重佈線結構的第一表面。保護層直接地配置於晶片的背面上。
在本發明的一實施例中，第二重佈線結構包括至少一介電層以及多個第二導電元件。多個第二導電元件配置於至少一介電層中，且晶片透過第一重佈線結構及導電柱與第二導電元件電性連接。
在本發明的一實施例中，封裝結構還包括底膠。底膠配置於第一重佈線結構的第一表面與晶片的主動面之間。
在本發明的一實施例中，晶片透過覆晶接合製程與第一重佈線結構電性連接。
本發明的封裝結構的製造方法，其至少包括以下步驟。提供第一承載基底。形成第一重佈線結構於第一承載基底上。第一重佈線結構具有第一表面與相對於第一表面的第二表面，其中第一表面附著至第一承載基底。提供第二承載基底。第二承載基底附著至第一重佈線結構的第二表面。將第一重佈線結構分離自第一承載基底。將晶片配置於第一重佈線結構的第一表面上，其中晶片具有主動面與相對於主動面的背面。保護層直接地形成於背面，且晶片的主動面黏接至第一重佈線結構的第一表面。
在本發明的一實施例中，封裝結構的製造方法還包括形成第一離形層於第一承載基底與第一重佈線結構之間。
在本發明的一實施例中，封裝結構的製造方法還包括形成第二離形層於第二承載基底與第一重佈線結構的第二表面之間，以將第二承載基底分離自第一重佈線結構。
基於上述，本發明的保護層是形成於晶片的背面，藉此強化晶片以充分地減少在封裝結構的製造過程中所產生翹曲的問題。再者，由於減少了晶片翹曲的問題，可增加覆晶接合（flip-chip bonding）的良率，以減少無接點（non-joint）的問題。因此，增加了在晶片上配置有保護層的晶片的整體強度。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1J是依照本發明的一實施例的封裝結構的製造方法的剖面示意圖。請參考圖1A，提供第一承載基底60。在實施例中，第一承載基底60可以是由矽（silicon）、聚合物（polymer）或其他合適的材料製成。於第一承載基底60上形成第一離形層70，以增強第一承載基底60與後續形成於其上的其他結構之間的黏著性，並於製程中改善整體封裝結構的剛性。第一離形層70例如是光熱轉換（light to heat conversion，LTHC）黏著層或其他合適的黏著層。
請參考圖1B，第一重佈線結構100形成於第一承載基底60與第一離形層70上。在實施例中，第一重佈線結構100具有第一表面100a與相對於第一表面100a的第二表面100b。第一重佈線結構100可包括多個介電層及多個導電元件配置於其中。如圖1B所示，第一導電元件120包括三個走線層（trace layer）121、122、133分別配置於三個介電層111、112、113中。第一導電元件120包括與走線層121、122、123連接的多個互連結構（interconnect structure）。第一導電元件120包括形成於第二表面100b上的多個球墊126，且球墊126透過互連結構與走線層121、122、123電性連接。舉例而言，首先，可以於第一承載基底60上形成走線層121。接著，於第一承載基底60上形成包括多個開口的介電層111，以覆蓋走線層121，且介電層111的開口可以暴露出至少一部分的走線層121。隨後，可以於介電層111上及其開口中形成走線層122，且走線層122電性連接至走線層121。可以執行多次上述步驟以依次形成介電層112、走線層123、介電層113及球墊126。
如圖1B所示，介電層113暴露出走線層123與配置於其上的互連結構，使走線層123可透過互連結構與其他走線層或封裝結構電性連接。為了獲得較佳的細線距（line-and-space，L/S）的重佈線層的良率，圖案化的電路包括走線層122及走線層121，其中位於介電層112中的走線層122有細間距（fine pitch）圖案，位於第一表面100a上的走線層121有大間距圖案。此外，球墊126可以由銅、鎳、錫、金、銀或其組合製成。
請參考圖1C，第二承載基底80附著至第一重佈線結構100的第二表面100b。再者，第二離形層90形成於第二承載基底80與第一重佈線結構100之間。球墊126可以嵌入於第二離形層90之中。第一承載基底60透過第一離形層70隨圖1C中箭頭所指的方向自第一重分佈結構100的第一表面100a分離。
請參考圖1D，在第一重佈線結構100分離自第一承載基底60之後，第一重佈線結構100的第一表面100a可具有對於後續覆晶接合製程較理想的表面共面性（coplanarity）。在本實施例中，自第一表面100a暴露出的走線層121的表面可以低於介電層111的表面。介電層111的表面及走線層121的表面之間的高度差可以小於3μm。再者，多個導電柱200形成於第一重佈線結構100的第一表面100a上，且電性連接至走線層121。在本實施例中，導電柱200可以由銅、鎳、錫、金、銀或其組合製成。
請參考圖1E，晶片500經由覆晶接合製程配置於第一重佈線結構100的第一表面100a上，但本發明不以此為限。晶片500的數量可以依電路設計而定，本發明不對晶片500的數量加以限制。如圖1E所示，導電柱200可圍繞於晶片500。晶片500具有主動面520及相對於主動面520的背面540。在配置晶片500於第一表面100a上之前，可以將保護層600直接地形成於背面540上。保護層600能夠防止晶片500在覆晶接合製程期間產生斷裂。此外，尤其是對於大尺寸的晶片來說，借助於保護層600可減少晶片翹曲的問題，並可改善覆晶接合的良率，以避免無接點的問題，藉此增強在後續形成的封裝結構10（如圖1J所示）的整體強度。保護層600的厚度例如介於5μm與30μm之間。毛細底膠（Capillary Underfill，CUF）300形成於晶片500的主動面520與第一重佈線結構100的第一表面100a之間並至少圍繞晶片500側面530的一部份。在晶片500的背面540上的保護層600可防止毛細底膠300溢流至背面540。毛細底膠300可利用絕緣材料，例如環氧樹脂（epoxy）或其他合適的樹脂來形成。再者，多個凸塊550以及多個接墊560位於主動面520與第一重佈線結構100的第一表面100a之間作為互連結構，以電性連接晶片500與第一重佈線結構100的第一導電元件120。
請參考圖1F，藉由絕緣密封體700將晶片500、保護層600以及導電柱200密封。如圖1F所示，絕緣密封體700形成在晶片500、保護層600以及導電柱200上，使絕緣密封體700完全地覆蓋所有的導電柱200、晶片500以及保護層600。絕緣密封體700可包括經由模封製程而配置於第一重佈線結構100上的模塑化合物（molding compound）。如圖1F所示，絕緣密封體700可具有厚度t1，且厚度t1大於導電柱200的高度。
請參考圖1G，將絕緣密封體700的厚度t1薄化至厚度t2，以暴露出導電柱200的頂表面，用以例如在後續的製程中在導電柱200上形成另一個重佈線結構。在薄化製程之後，絕緣密封體700可以仍然是覆蓋住保護層600。此外，在薄化製程後，可加強絕緣密封體700與導電柱200的表面粗糙度（surface roughness），藉此增加隨後在其上形成的層的黏合性。薄化製程可以利用機械磨削（mechanical grinding）、化學機械研磨（Chemical-Mechanical Polishing，CMP）、蝕刻或其他合適方法來執行。導電柱200的蝕刻製程可以包括異向性（anisotropic）蝕刻或等向性（isotropic）蝕刻。
請參考圖1H，形成第二重佈線結構400於絕緣密封體700之上。第二重佈線結構400可以包括至少一個介電層以及至少一個導電元件。如圖1H所示，第二重佈線結構400包括第二導電元件420。第二導電元件420可以包括走線層422、423分別配置於介電層412、413中。再者，走線層422、423電性連接至導電柱200。
請參考圖1I與圖1J，第二承載基底80透過第二離形層90自第一重佈線結構100的第二表面100b分離，以形成封裝結構10，如圖1J所示。
圖2A至圖2D是依照本發明的一實施例的封裝結構的晶片和保護層的製造方法的剖面示意圖。請參考圖2A，提供具有主動面520’以及相對於主動面520’的背面540’的晶圓500’。主動面520’具有形成於其上的多個凸塊550與接墊560。請參考圖2B，保護層600形成於背面540’上。請參考圖2C，於晶圓500’ 上執行單體化製程（singulation process）以形成多個晶片500，如圖2C與圖2D所示。單體化製程包括如旋轉刀（rotating blade）切割或鐳射（laser beam）切割。
在實施例中，保護層600的熱膨脹係數（coefficient of thermal expansion，CTE）小於聚醯亞胺（polyimide）的熱膨脹係數，但是大於模塑化合物的熱膨脹係數與矽材的熱膨脹係數。舉例來說，保護層600的熱膨脹係數介於5ppm/℃與40 ppm/℃之間。如此一來，保護層600可以降低於晶圓500’的鋸切製程中，晶片斷裂或崩碎（chipping）的風險。此外，特別是對於大尺寸的晶片來說，保護層600可作為緩衝層以降低晶片500的翹曲問題，並提升覆晶接合製程的良率以避免無接點的風險。具體來說，當晶片500的翹曲問題減少時，晶片500可借助校準（alignment）製程來接合至具有細間距的線距圖案的第一重佈線結構100的走線層121。
圖3是依照本發明的另一實施例的封裝結構的剖面示意圖。封裝結構20類似於圖1J的封裝結構10，因此，相同的構件以相同的標號表示，於此不再重複。封裝結構20與封裝結構10之間的差異在於，絕緣密封體700可以進一步地被薄化至移除配置於保護層600以上的絕緣密封體700，以暴露出保護層600。藉此，保護層600的頂表面可以與絕緣密封體700的頂表面及導電柱200的頂表面共面（coplanar）。如此一來，第二重佈線結構400可直接地接觸保護層600。在實施例中，保護層600可作為緩衝層以避免於封裝結構20的製程中第二重佈線結構400與晶片500之間產生脫層（delamination）。
在本實施例中，保護層600可以由類似於絕緣密封體700的材料（例如模塑化合物）製成。藉此，保護層600與絕緣密封體700可具有類似的性質。如此一來，可延長在薄化或磨削保護層600以及絕緣密封體700的製程中所使用的砂輪（mold grinding wheel）的使用年限。此外，保護層600可具有良好的熱傳導係數（在2W/m-k與5W/m-k之間的範圍內），以提升封裝結構20的散熱性能。
圖4是依照本發明的另一實施例的封裝結構的剖面示意圖。封裝結構30類似於圖1J的封裝結構10，因此，相同的構件以相同的標號表示，於此不再重複。封裝結構30與封裝結構10之間的差異在於，使用成型底膠（Molded Underfill，MUF）來取代毛細底膠300。舉例來說，絕緣密封體700可以是模塑化合物，有時稱為成型底膠。成型底膠可將晶片500密封並將晶片500與第一重佈線結構100之間的空隙填滿，藉此改善封裝結構30的可靠性。可根據不同的封裝結構的實際設計需求採用不同的底膠。
圖5A至5C是應用圖1J的封裝結構10的半導體封裝的一些示例性實施例的示意圖。請參考圖5A，堆疊晶片結構800可形成於封裝結構10之上。多個凸塊127可配置於封裝結構10的底面上，以將封裝結構10接合於電路基板或中介板（interposer）上。在實施例中，多個接墊814可形成於堆疊晶片結構800的各個晶片810的表面上。不同晶片810表面上的接墊814可經由多個凸塊812以及導線816相互接合且電性連接。堆疊晶片結構800的各個晶片810也可經由凸塊812以及導線816電性連接並接合至封裝結構10以及晶片500。如圖5A所示，電磁干擾（electromagnetic interference，EMI）屏蔽結構50可被配置成環繞並保護封裝結構10以及堆疊晶片結構800。
請參考圖5B，多個扇出（fan-out）結構900以及多個被動元件950（例如電容器、電感器或天線）也可配置於封裝結構10之上。
請參考圖5C，多個晶圓級晶片尺寸封裝（wafer level chip scale package，WLCSP）結構1000與被動元件950可配置於封裝結構10之上。藉此，如圖5A、圖5B及圖5C所示，封裝結構10的配置可依照不同功能或不同應用種類的實際需求來調整。
綜上所述，本發明的封裝結構可包括第一重佈線結構、第二重佈線結構以及晶片。第二重佈線結構配置於第一重佈線結構之上。晶片配置於並被密封於第一重佈線結構與第二重佈線結構之間，且晶片具有主動面與相對於主動面的背面。此外，本發明的封裝結構包括配置於晶片的背面的保護層。
在封裝結構的製造過程中，保護層可避免晶片於晶圓鋸切製程中產生斷裂或崩碎。此外，當晶片以覆晶的方式接合於第一重佈線結構時，保護層可減少晶片斷裂與翹曲的問題，也可改善覆晶接合的良率以避免無接點的問題，從而提升封裝結構的整體強度。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10、20、30‧‧‧封裝結構
100‧‧‧第一重佈線結構
100a‧‧‧第一表面
100b‧‧‧第二表面
111、112、113、411、412、413‧‧‧介電層
120‧‧‧第一導電元件
121、122、123、422、423‧‧‧走線層
126‧‧‧球墊
127、550、812‧‧‧凸塊
200‧‧‧導電柱
300‧‧‧毛細底膠
400‧‧‧第二重佈線結構
420‧‧‧第二導電元件
50‧‧‧電磁干擾屏蔽結構
500、810‧‧‧晶片
500’‧‧‧晶圓
520、520’‧‧‧主動面
530‧‧‧側面
540、540’‧‧‧背面
560、814‧‧‧接墊
600‧‧‧保護層
700‧‧‧絕緣密封體
60‧‧‧第一承載基底
70‧‧‧第一離形層
80‧‧‧第二承載基底
800‧‧‧堆疊晶片結構
816‧‧‧導線
90‧‧‧第二離形層
900‧‧‧扇出結構
950‧‧‧被動元件
1000‧‧‧晶圓級晶片尺寸封裝結構
t1、t2‧‧‧厚度
圖1A至圖1J是依照本發明一實施例的封裝結構的製造方法的剖面示意圖。 圖2A至圖2D是依照本發明一實施例的封裝結構的晶片和保護層的製造方法的剖面示意圖。 圖3是依照本發明的另一實施例的封裝結構的剖面示意圖。 圖4是依照本發明的另一實施例的封裝結構的剖面示意圖。 圖5A至5C是應用圖1J的封裝結構的半導體封裝的一些示例性實施例的示意圖。

Claims (10)

  1. 一種封裝結構，包括： 第一重佈線結構，具有第一表面以及相對於所述第一表面的第二表面； 晶片，配置於所述第一重佈線結構的所述第一表面上，且具有主動面以及相對於所述主動面的背面； 絕緣密封體，密封所述晶片與所述第一重佈線結構的所述第一表面；以及 保護層，直接地配置於所述晶片的所述背面上。
  2. 如申請專利範圍第1項所述的封裝結構，其中所述第一重佈線結構包括： 至少一介電層；以及 多個第一導電元件，配置於所述至少一介電層中，且所述晶片與暴露於所述第一表面的所述第一導電元件電性連接。
  3. 如申請專利範圍第2項所述的封裝結構，更包括： 多個凸塊，配置於所述主動面與所述第一重佈線結構的所述第一表面之間，且分別與所述第一導電元件電性連接，其中面向所述第一表面的所述凸塊的表面與所述絕緣密封體的表面共面。
  4. 如申請專利範圍第1項所述的封裝結構，更包括： 第二重佈線結構，配置於所述晶片的所述背面、所述保護層與所述絕緣密封體之上；以及 多個導電柱，圍繞於所述晶片並配置於所述第一重佈線結構與所述第二重佈線結構之間。
  5. 如申請專利範圍第1項所述的封裝結構，其中所述保護層的厚度介於5μm與30μm之間。
  6. 一種封裝結構的製造方法，包括： 提供第一承載基底； 形成第一重佈線結構於所述第一承載基底上，所述第一重佈線結構具有第一表面與相對於所述第一表面的第二表面，其中所述第一表面附著至所述第一承載基底； 提供第二承載基底，所述第二承載基底附著至所述第一重佈線結構的所述第二表面； 將所述第一重佈線結構分離自所述第一承載基底；以及 將晶片配置於所述第一重佈線結構的所述第一表面上，其中所述晶片具有主動面與相對於所述主動面的背面，保護層直接地形成於所述背面，且所述晶片的所述主動面黏接至所述第一重佈線結構的所述第一表面。
  7. 如申請專利範圍第6項所述的封裝結構的製造方法，其中形成所述第一重佈線結構的步驟包括： 形成至少一介電層與多個第一導電元件，且所述晶片與所述第一導電元件電性連接。
  8. 如申請專利範圍第7項所述的封裝結構的製造方法，更包括： 形成多個導電柱於所述第一重佈線結構的所述第一表面，其中所述導電柱圍繞所述晶片； 利用絕緣密封體密封所述晶片、所述保護層與所述導電柱，包括： 配置所述絕緣密封體於所述晶片、所述保護層與所述導電柱上；以及 減少所述絕緣密封體的厚度以暴露出所述導電柱的頂表面。
  9. 如申請專利範圍第8項所述的封裝結構的製造方法，更包括： 形成第二重佈線結構於所述絕緣密封體上，包括： 形成至少一介電層與多個第二導電元件，且所述導電柱分別與所述第一導電元件及所述第二導電元件電性連接。
  10. 如申請專利範圍第6項所述的封裝結構的製造方法，其中配置所述晶片於所述第一重佈線結構的所述第一表面上的步驟包括： 形成多個凸塊於所述晶片的所述主動面與所述第一重佈線結構的所述第一表面之間。
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