TWI689056B - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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TWI689056B
TWI689056B TW108100441A TW108100441A TWI689056B TW I689056 B TWI689056 B TW I689056B TW 108100441 A TW108100441 A TW 108100441A TW 108100441 A TW108100441 A TW 108100441A TW I689056 B TWI689056 B TW I689056B
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semiconductor die
conductive bumps
sealing body
adhesive layer
insulating sealing
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TW202013628A (zh
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張簡上煜
徐宏欣
林南君
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力成科技股份有限公司
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Abstract

提供一種封裝結構包括半導體晶粒、絕緣密封體、介電層以及重佈線路層。半導體晶粒具有主動面、相對於主動面的背面以及配置於主動面上的多個導電凸塊。絕緣密封體密封半導體晶粒。重佈線路層配置於絕緣密封體上且電性連接至多個導電凸塊。介電層配置於絕緣密封體與重佈線路層之間，其中介電層密封每一多個導電凸塊的至少一部分。另提供一種封裝結構的製造方法。

Description

封裝結構及其製造方法
本發明是有關於一種封裝結構及其製造方法，且特別是有關於一種具有更好的封裝性能及可靠度的封裝結構。
為了使電子產品實現輕薄短小的設計，半導體封裝技術跟著日益進展，以試圖發展出小體積、重量輕、高密度以及在市場上具有高競爭力的產品。舉例而言，扇出型（fan-out）封裝由於其密實度（compactness）而趨於熱門。然而，隨著這些產品的尺寸減小，如封裝可靠度及破裂（cracking）等諸多問題變得極其重要。藉由整合扇出型封裝改善所提供的可靠度與性能，同時排除半導體晶粒的破裂問題，實為未來封裝上的關鍵因素。
據此，本發明直接提供一種封裝結構及其製造方法，其中此封裝結構增強封裝性能與可靠度，同時減少半導體晶粒的破裂問題。
本發明提供一種封裝結構包括半導體晶粒、絕緣密封體、介電層以及重佈線路層。半導體晶粒具有主動面、相對於主動面的背面以及配置於主動面上的多個導電凸塊。絕緣密封體密封半導體晶粒。重佈線路層配置於絕緣密封體上且電性連接至多個導電凸塊。介電層配置於絕緣密封體與重佈線路層之間，其中介電層密封每一多個導電凸塊的至少一部分。
在本發明的一實施例中，上述的介電層的側壁與絕緣密封體的側壁以及重佈線路層的側壁對齊。
在本發明的一實施例中，上述的多個導電凸塊的高度範圍從3微米至20微米。
在本發明的一實施例中，上述的絕緣密封體更覆蓋半導體晶粒的所述主動面，多個導電凸塊藉由絕緣密封體以及介電層密封。
在本發明的一實施例中，上述的介電層完全覆蓋絕緣密封體的頂面。
在本發明的一實施例中，上述的封裝結構更包括多個導電端子。多個導電端子配置於重佈線路層上，其中多個導電端子經由重佈線路層電性連接至多個導電凸塊。
本發明更提供一種封裝結構的製造方法。方法至少包括以下步驟。提供載板。形成黏著層於載板上。接合半導體晶粒於黏著層上，其中半導體晶粒具有主動面、相對於主動面的背面以及配置於主動面上的多個導電凸塊。半導體晶粒以面朝下的方式接合於黏著層上，以使多個導電凸塊面向黏著層。形成絕緣密封體於黏著層上以密封半導體晶粒。剝離載板，使得黏著層從半導體晶粒以及絕緣密封體上分離。形成介電層於絕緣密封體上以覆蓋半導體晶粒的主動面以及絕緣密封體。形成重佈線路層於介電層及半導體晶粒上，其中重佈線路層電性連接至多個導電凸塊。
在本發明的一實施例中，上述的絕緣密封體的頂面與半導體晶粒的主動面形成共面。
在本發明的一實施例中，上述的製造方法形成介電層後，執行介電層的薄化步驟，直到介電層的頂面與多個導電凸塊的頂面共面。
在本發明的一實施例中，上述的製造方法在薄化步驟後，多個導電凸塊的高度範圍從3微米至20微米。
在本發明的一實施例中，上述的製造方法形成介電層以完全覆蓋所述絕緣密封體的頂面，以使介電層將所述重佈線路層與絕緣密封體分開。
在本發明的一實施例中，上述的介電層的側壁與絕緣密封體的側壁以及重佈線路層的側壁對齊。
基於上述，本發明所形成的封裝結構中半導體晶粒具有藉由介電層密封或藉由介電層以及絕緣密封體密封的多個導電凸塊。此外，半導體晶粒的背面及側壁藉由絕緣密封體密封及保護。因此，可改善封裝的可靠度及性能，且減少了晶粒破裂的問題。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
下文將會附加標號以對本發明較佳實施例進行詳細描述，並以圖式說明。在可能的情況下，相同或相似的構件在圖式中將以相同的標號顯示。
圖1A至圖1H是依據本發明一實施例的封裝結構的製造方法的剖面示意圖。
請參照圖1A，提供載板101。在一些實施例中，載板101可以由矽、聚合物或其他適宜材料所製成。在一些其他實施例中，載板101可以是玻璃基板或玻璃支撐板。其他合適的基板材料也可以被使用作為載板101，只要所述材料能夠承載在其之上所形成的封裝結構且能夠承受後續的製程即可。如圖1A所示，於載板101上形成黏著層103，以增強載板101與隨後形成於其上的其他結構之間的黏著力，並改善製造過程中整個封裝結構的剛性。在某些實施例中，黏著層103可以是光熱轉換（light to heat conversion, LTHC）黏著層，其可以在室溫下透過施加雷射而從載板101上剝離。然而，本發明不限於此。在一些替代的實施例中，可以視需求而使用其他類型適宜的黏著層。
請參照圖1B，於載板101上形成黏著層103後，可以於載板101上配置至少一半導體晶粒105。在所示的實施例中，於黏著層103上接合半導體晶粒105。雖然圖中僅繪示兩個半導體晶粒105，但應注意的是，於本發明並不加以限制半導體晶粒105的數量，且前述的數量可以基於需求做調整。每一半導體晶粒105可以包括半導體基板105a、多個接觸接墊105b、保護層105c、後保護層105d以及多個導電凸塊105e。於半導體基板105a上配置多個接觸接墊105b。保護層105c被配置於半導體基板105a上且具有暴露出部分接觸接墊105b的開口。後保護層105d覆蓋保護層105c且具有暴露出至少部分接觸接墊105b的多個開口。於開口中配置多個導電凸塊105e，以覆蓋被暴露出的部分接觸接墊105b。
半導體晶粒105具有主動面AS以及相對於主動面AS的背面BS。於半導體晶粒105的主動面AS上配置多個導電凸塊105e。在一些實施例中，半導體晶粒105可以以面朝下的方式接合黏著層103，以使多個導電凸塊105e面向黏著層103。如圖1B所示，於接合期間，多個導電凸塊105e部分陷入黏著層103中。在一些實施例中，多個導電凸塊105e的高度約為20微米（micrometer, µm）至50微米，而多個導電凸塊105e的5微米至10微米可以陷入黏著層103中。換句話說，黏著層103與半導體晶粒105的主動面AS之間存在間隙。
請參照圖1C，於黏著層103上接合半導體晶粒105後，於黏著層103上形成絕緣密封體108，以覆蓋及密封半導體晶粒105。絕緣密封體108至少覆蓋半導體晶粒105的背面BS及側表面SW。在一些實施例中，絕緣密封體108可以完全覆蓋半導體晶粒105的背面BS。在某些實施例中，形成絕緣密封體108，以填入黏著層103與半導體晶粒105的主動面AS之間的間隙中，使得多個導電凸塊105e被絕緣密封體108所密封。絕緣密封體108可以經由模塑製程（molding process）形成。舉例而言，絕緣密封體108的材料可以包括環氧樹脂（epoxy resin）或其它適宜的聚合物材料。在一些其他的實施例中，絕緣密封體108可以包括分佈在環氧樹脂或其它適宜的聚合物材料中的填充物。填充物的材料包括二氧化矽、氧化鋁或其它適宜的材料。填充物能夠增強絕緣密封體108的機械強度，使絕緣密封體108可以良好地保護半導體晶粒105。
請參照圖1D，於黏著層103上形成絕緣密封體108後，載板101與黏著層103從絕緣密封體108以及半導體晶粒105上剝離或分離。在一些實施例中，藉由對黏著層103（如LTHC離型層）照射紫外光雷射，可以使在其上形成的其他元件從黏著層103以及載板101上剝離。在剝離製程之後，暴露出多個導電凸塊105e，且藉由絕緣密封體108覆蓋半導體晶粒105的主動面AS。此外，多個導電凸塊105e從絕緣密封體108向外凸起。
請參照圖1E，載板101與黏著層103剝離後，於絕緣密封體108上形成介電層110，以覆蓋多個導電凸塊105e。在一些實施例中，介電層110覆蓋絕緣密封體108的頂面108T以及多個導電凸塊105e的頂面105T。舉例而言，介電層110可以完全覆蓋絕緣密封體108的頂面108T。此外，介電層110填充多個導電凸塊105e之間的間隙。介電層110可以由氧化矽、氮化矽、碳化矽、氮氧化矽、聚酰亞胺、苯並環丁烯（benzocyclobutene, BCB）或其他類似者等的非有機或有機介電材料所製成。
請參照圖1F，形成介電層110後，執行介電層110的薄化步驟，直到暴露出多個導電凸塊105e的頂面105T。薄化製程包括執行機械研磨製程（mechanical grinding process）、化學機械研磨製程（chemical-mechanical polishing, CMP）、蝕刻或其他適宜的製程或其組合。在薄化製程後，多個導電凸塊105e的頂面105T實質上與介電層110的頂面110T共面（coplanar）。在一些實施例中，於薄化製程後，多個導電凸塊105e的高度範圍從3微米至20微米。也就是說，於薄化製程期間，可以稍微研磨到導電凸塊105e。如圖1F所示，藉由介電層110與絕緣密封體108密封多個導電凸塊105e的側壁。
請參照圖1G，在薄化介電層110後，於半導體晶粒105與介電層110上形成重佈線路層112。在一些實施例中，重佈線路層112包括交替形成的多個介電層112A和多個導電層112B。多個介電層112A可以由氧化矽、氮化矽、碳化矽、氮氧化矽、聚酰亞胺、苯並環丁烯（benzocyclobutene, BCB）或其他類似者等的非有機或有機介電材料所製成，但本發明不限於此。多個導電層112B可以由銅、鋁、鎳或其他適宜的導電材料所製成，但本發明不限於此。
如圖1G所示，重佈線路層112電性連接至半導體晶粒105。此外，導電層112B電性連接至半導體晶粒105的多個導電凸塊105e。在所示的實施例中，圖中繪示了四層介電層112A以及三層導電層112B，然而，本發明不限於此。在一些替代的實施例中，介電層112A與導電層112B的數量可以基於產品設計做調整。在一些實施例中，重佈線路層112中最上方的介電層112A可以包括多個導電接墊112C配置於其上。舉例而言，導電接墊112C是凸塊底金屬（Under bump metallurgy, UBM）圖案，以用於置球（ball mount）。在一些其他實施例中，會省略導電接墊112C（UBM圖案）。在一些實施例中，介電層110將重佈線路層112與絕緣密封體108分開。
在形成重佈線路層112後，於重佈線路層112上可選擇性地配置多個導電端子114。多個導電端子114經由重佈線路層112電性連接至多個導電凸塊105e。在一些實施例中，導電端子114可以包括錫球或焊球，然而，本發明不限於此。在某些實施例中，可以藉由執行置球製程或回焊製程來形成導電端子114。
請參照圖1H，於重佈線路層112上形成多個導電端子114後，沿著切割線DL（如圖1G所示）執行切割製程，以切割整個晶圓結構或面板結構（切穿絕緣密封體108、介電層110以及重佈線路層112），而構成多個封裝結構10。在切割製程後，介電層110的側壁與絕緣密封體108的側壁以及重佈線路層112的側壁對齊。在示例性的實施例中，切割製程為包括機械刀片鋸切（mechanical blade sawing）或雷射切割的晶圓切割製程或面板切割製程。
在完整的結構中，藉由絕緣密封體108覆蓋每一封裝結構10的半導體晶粒105的背面BS。因此，可以達到較好地保護晶粒背面，且可避免水氣滲透。此外，藉由介電層110以及絕緣密封體108密封多個導電凸塊105e。並且，多個導電凸塊105e與介電層110的頂面（105T/110T）實質上共面。這些特徵增強了封裝的可靠度與性能，且減少了晶粒破裂的問題。在一實施例中，縱使保護層105c及/或後保護層105d受損，例如是具有低介電常數（low k）材料所形成的保護層105c及/或後保護層105d，也可以降低半導體晶粒105損壞的可能。
圖2A至圖2F是依據本發明另一實施例的封裝結構的製造方法的剖面示意圖。圖2A至圖2F的實施例與圖1A至圖1H的實施例類似，因此採用相同的標號來表示相同或近似的元件，故於此不加以贅述。這些實施例的差別在於：於載板101上接合半導體晶粒105的方式。
如圖2A所示，於載板101上形成黏著層103後（圖1B的步驟），於載板101上配置多個半導體晶粒105。在所示的實施例中，半導體晶粒105以面朝下的方式接合黏著層103。在半導體晶粒105的接合步驟中，多個導電凸塊105e完全陷入黏著層103中。換句話說，黏著層103沒有暴露出多個導電凸塊105e，且半導體晶粒105的主動面AS與黏著層103接觸。在一些實施例中，多個導電凸塊105e的高度約為20微米至50微米，而多個導電凸塊105e完全陷入黏著層103中。因此，沒有間隙存在於黏著層103與半導體晶粒105的主動面AS之間。
請參照圖2B，於黏著層103上接合半導體晶粒105後，於黏著層103上形成絕緣密封體108，以覆蓋及密封半導體晶粒105。絕緣密封體108至少覆蓋半導體晶粒105的背面BS及側表面SW。在一些實施例中，絕緣密封體108可以完全覆蓋半導體晶粒105的背面BS。此外，如圖2B所示，絕緣密封體108的頂面108T實質上與半導體晶粒105的主動面AS形成共面。
請參照圖2C，於黏著層103上形成絕緣密封體108後，載板101與黏著層103從絕緣密封體108以及半導體晶粒105上剝離或分離。在剝離製程之後，暴露出多個導電凸塊105e。
請參照圖2D，載板101與黏著層103剝離後，於絕緣密封體108上形成介電層110，以覆蓋多個導電凸塊105e。接著，執行介電層110的薄化步驟，直到暴露出多個導電凸塊105e的頂面105T。在薄化製程後，多個導電凸塊105e的頂面105T實質上與介電層110的頂面110T共面，且多個導電凸塊105e的高度範圍從3微米至20微米。此外，藉由介電層110密封多個導電凸塊105e。
請參照圖2E，在薄化介電層110後，於半導體晶粒105與介電層110上形成重佈線路層112。類似於圖1G的實施例，圖2E中的重佈線路層112包括交替形成的多個介電層112A和多個導電層112B。在一些實施例中，重佈線路層112中最上方的介電層112A可以包括多個導電接墊112C配置於其上。舉例而言，導電接墊112C是凸塊底金屬圖案，以用於置球。在一些其他實施例中，會省略導電接墊112C（UBM圖案）。在形成重佈線路層112後，於重佈線路層112上可選擇性地配置多個導電端子114。多個導電端子114經由重佈線路層112電性連接至多個導電凸塊105e。
請參照圖2F，於重佈線路層112上形成多個導電端子114後，沿著切割線DL（如圖2E所示）執行切割製程，以切割整個晶圓結構或面板結構（切穿絕緣密封體108、介電層110以及重佈線路層112），而構成多個封裝結構20。在切割製程後，介電層110的側壁與絕緣密封體108的側壁以及重佈線路層112的側壁對齊。
在完整的結構中，藉由絕緣密封體108覆蓋每一封裝結構20的半導體晶粒105的背面BS。因此，可以達到較好地保護晶粒背面，且可避免水氣滲透。此外，藉由介電層110密封多個導電凸塊105e。並且，多個導電凸塊105e與介電層110的頂面（105T/110T）實質上共面。這些特徵增強了封裝的可靠度與性能，且減少了晶粒破裂的問題。
綜上所述，本發明所形成的封裝結構中藉由絕緣密封體保護半導體晶粒的背面。此外，藉由介電層密封或藉由介電層以及絕緣密封體密封多個導電凸塊。因此，可改善封裝的可靠度及性能，且減少了晶粒破裂的問題。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10、20:封裝結構
101:載板
103:黏著層
105:半導體晶粒
105a:半導體基板
105b:接觸接墊
105c:保護層
105d:後保護層
105e:導電凸塊
105T、108T、110T:頂面
108:絕緣密封體
110、112A:介電層
112:重佈線路層
112B:導電層
112C:導電接墊
114:導電端子
AS:主動面
BS:背面
SW:側表面
DL:切割線
圖1A至圖1H是依據本發明一實施例的封裝結構的製造方法的剖面示意圖。 圖2A至圖2F是依據本發明另一實施例的封裝結構的製造方法的剖面示意圖。
10:封裝結構
105:半導體晶粒
108:絕緣密封體
110、112A:介電層
112:重佈線路層
112B:導電層
112C:導電接墊
114:導電端子
BS:背面
SW:側表面

Claims (9)

  1. 一種封裝結構，包括：半導體晶粒，具有主動面、相對於所述主動面的背面以及配置於所述主動面上的多個導電凸塊；絕緣密封體，密封所述半導體晶粒，其中所述絕緣密封體完全覆蓋所述半導體晶粒的所述背面；重佈線路層，配置於所述絕緣密封體上且電性連接至所述多個導電凸塊；以及介電層，配置於所述絕緣密封體與所述重佈線路層之間，其中所述介電層密封每一所述多個導電凸塊的至少一部分。
  2. 如申請專利範圍第1項所述的封裝結構，其中所述介電層的頂面與所述多個導電凸塊的頂面共面。
  3. 如申請專利範圍第1項所述的封裝結構，其中所述絕緣密封體更覆蓋所述半導體晶粒的所述主動面。
  4. 如申請專利範圍第1項所述的封裝結構，其中所述絕緣密封體的頂面與所述半導體晶粒的所述主動面共面。
  5. 一種封裝結構的製造方法，包括：提供載板；形成黏著層於所述載板上；接合半導體晶粒於所述黏著層上，其中所述半導體晶粒具有主動面、相對於所述主動面的背面以及配置於所述主動面上的多 個導電凸塊，且所述半導體晶粒以面朝下的方式接合於所述黏著層上，以使所述多個導電凸塊面向所述黏著層；形成絕緣密封體於所述黏著層上且密封所述半導體晶粒；剝離所述載板，藉由從所述半導體晶粒以及所述絕緣密封體上分離所述黏著層；形成介電層以覆蓋所述半導體晶粒的所述主動面且覆蓋所述絕緣密封體，其中所述介電層密封每一所述多個導電凸塊的至少一部分；以及形成重佈線路層於所述介電層及所述半導體晶粒上，其中所述重佈線路層電性連接至所述多個導電凸塊。
  6. 如申請專利範圍第5項所述的製造方法，其中接合所述半導體晶粒於所述黏著層期間，所述多個導電凸塊部分陷入所述黏著層中。
  7. 如申請專利範圍第6項所述的製造方法，其中所述絕緣密封體被形成以填充所述黏著層與所述半導體晶粒的所述主動面之間的多個間隙，以使所述多個導電凸塊藉由所述絕緣密封體密封。
  8. 如申請專利範圍第5項所述的製造方法，其中接合所述半導體晶粒於所述黏著層期間，所述多個導電凸塊完全陷入所述黏著層中。
  9. 如申請專利範圍第5項所述的製造方法，其中所述多個導電凸塊藉由所述介電層密封或藉由所述介電層以及所述絕緣密封體密封。
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