TWI722893B - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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TWI722893B
TWI722893B TW109115254A TW109115254A TWI722893B TW I722893 B TWI722893 B TW I722893B TW 109115254 A TW109115254 A TW 109115254A TW 109115254 A TW109115254 A TW 109115254A TW I722893 B TWI722893 B TW I722893B
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package
sub
semiconductor
bumps
dummy
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TW109115254A
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TW202137427A (zh
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施信益
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南亞科技股份有限公司
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Abstract

一種半導體封裝包含第一子封裝及第二子封裝。第一子封裝堆疊於第二子封裝上。第一子封裝以及第二子封裝各包含：至少二個第一半導體晶片、第二半導體晶片、多個塑模件、銲墊層、多個重分佈層、以及多個凸塊。第一子封裝的凸塊附接至第二子封裝的銲墊層。

Description

半導體封裝及其製造方法
本發明有關一種半導體封裝，特別有關多個晶片堆疊的半導體封裝。
半導體製造旨在廉價地製造小型化、多功能和高容量的半導體元件。半導體封裝技術是有助於實現各目標的技術之一。特別是使用多個晶片堆疊的半導體封裝被建議用來實現及達到上述目的。
半導體封裝通常包括多個子封裝，其中一個子封裝堆疊在另一個子封裝上。半導體封裝中不同材料之間的熱膨脹係數的匹配不佳，會在製造和組裝期間，因為熱負荷而產生較高的界面應力。所述的應力可能導致各子封裝之間的表面發生界面分離(interfacial delamination) 。
根據本發明的多個實施例，一種半導體封裝包含第一子封裝及第二子封裝。第一子封裝堆疊於第二子封裝上。第一子封裝以及第二子封裝各包含：第一半導體晶片、第二半導體晶片、塑模件、銲墊層、重分佈層、凸塊。至少二個第一半導體晶片，以及設置於第一半導體晶片之間的第二半導體晶片，其中第一半導體晶片各包含多個矽通孔(Through Silicon Vias;TSVs)；塑模件設置於各第一半導體晶片以及第二半導體晶片之間，其中矽通孔的多個上表面、塑模件的多個上表面、第一半導體晶片的多個上表面，以及第二半導體晶片的上表面為共平面；銲墊層，設置覆蓋於矽通孔的上表面，塑模件的上表面、第一半導體晶片的上表面，以及第二半導體晶片的上表面；重分佈層 (Redistribution Layers; RDLs)，在矽通孔的多個下表面、塑模件的多個下表面、第一半導體晶片的多個下表面，以及第二半導體晶片的下表面之下方設置；以及凸塊連結至重分佈層。第一子封裝的凸塊附接至第二子封裝的銲墊層。
在一些實施例中，第一子封裝以及第二子封裝的各銲墊層包含多個有效墊以及多個虛設墊，各有效墊設置在矽通孔的上表面的相應一者上，虛設墊設置在第二半導體晶片上。
在一些實施例中，銲墊層包含鈍化材料。
在一些實施例中，第一子封裝以及第二子封裝的各重分佈層電性連結至矽通孔。
在一些實施例中，重分佈層在各第一半導體晶片以及第二半導體晶片之間電性連結。
在一些實施例中，第一子封裝以及第二子封裝的凸塊各包含多個有效凸塊以及多個虛設凸塊，有效凸塊設置在各第一半導體晶片下方，以及虛設凸塊設置在第二半導體晶片下方。
在一些實施例中，從上視圖，虛設凸塊設置在第二半導體晶片的多個拐角處。
在一些實施例中，第一子封裝的有效凸塊附接至第二子封裝的有效墊的對應一者，以及第一子封裝的虛設凸塊附接至第二子封裝的虛設墊的對應一者。
在一些實施例中，有效凸塊電性連結至矽通孔，以及虛設凸塊未電性連結至矽通孔。
在一些實施例中，第一子封裝以及第二子封裝的各凸塊包含：多個有效凸塊、多個第一虛設凸塊，以及多個第二虛設凸塊，有效凸塊以及第一虛設凸塊設置在第一半導體晶片下方，以及第二虛設凸塊設置在第二半導體晶片下方。
在一些實施例中，有效凸塊電性連結至矽通孔，並且第一虛設凸塊以及第二虛設凸塊未電性連結至矽通孔。
根據本發明的多個實施例，一種半導體封裝的製造方法，包含：形成第一子封裝以及第二子封裝，其中形成第一子封裝及第二子封裝各包含下列步驟：(a)提供設置於第一支撐基板上至少二個第一半導體晶片以及第一半導體晶片之間的第二半導體晶片，其中第一半導體晶片各包含實質上垂直於第一支撐基板的多個矽通孔，以及各矽通孔具有連接至第一支撐基板的第一端，以及嵌入至第一半導體晶片的第二端；(b)形成塑模層，覆蓋第一支撐基板、第一半導體晶片以及第二半導體晶片；(c)薄化塑模層、第一半導體晶片以及第二半導體晶片，其中矽通孔的第二端從第一半導體晶片暴露出來，其中矽通孔的多個上表面、薄化的塑模層的多個上表面、薄化的第一半導體晶片的多個上表面以及薄化的第二半導體晶片的上表面為共平面；(d)形成銲墊層覆蓋在矽通孔的上表面以及薄化的第二半導體晶片的上表面；(e)從矽通孔的多個下表面、塑模層的多個下表面、第一半導體晶片的多個下表面以及第二半導體晶片的下表面移除第一支撐基板； (f)形成多個重分佈層在矽通孔的下表面、塑模層的下表面、第一半導體晶片的下表面以及第二半導體晶片的下表面的下方；以及(g)形成多個凸塊，連結至重分佈層。藉由附接第一子封裝的凸塊至第二子封裝的銲墊層，堆疊第一子封裝在第二子封裝上方。
在一些實施例中，形成第一子封裝及第二子封裝更包含：在步驟(e)之前，附著第二支撐基板至銲墊層。
在一些實施例中，形成第一子封裝及第二子封裝更包含：在步驟(g)之後，從銲墊層移除第二支撐基板。
在一些實施例中，第一子封裝及第二子封裝的各銲墊層包含：多個有效墊以及多個虛設墊，各有效墊設置在矽通孔的上表面的對應一者上，以及虛設墊設置在第二半導體晶片上。
在一些實施例中，第一子封裝及第二子封裝的各重分佈層係電性連結至矽通孔。
在一些實施例中，重分佈層在各第一半導體晶片以及第二半導體晶片之間電性連結。
在一些實施例中，第一子封裝及第二子封裝的各凸塊包含：多個有效凸塊以及多個虛設凸塊，有效凸塊設置於各第一半導體晶片下方，以及虛設凸塊設置於第二半導體晶片下方。
在一些實施例中，有效凸塊電性連結至矽通孔，以及虛設凸塊未電性連結至矽通孔。
在一些實施例中，第一子封裝的有效凸塊附接至第二子封裝的有效墊的對應一者，以及第一子封裝的虛設凸塊附接至第二子封裝的虛設墊的對應一者。
為了使本發明的描述更加詳細和完整，可以參考附圖以及以下描述的各種實現方式或示例。
除非在本揭露中有其他清楚的指示，否則本文所使用的單數包括複數。透過引用例如「實施例」之類的特定參考，在本發明的至少一個實施例中，它表示特定的特徵、結構或特性。當出現特別參考時，不需要參考相同的實施例。此外，在一個或多個實施例中，這些特殊特徵、結構或特性可以適當地彼此組合。
本揭露提供了一種製造半導體封裝的方法，所述的半導體封裝配備有虛設凸塊和虛設墊以減少每個子封裝之間的表面的界面分離。
第1圖繪示根據本發明一些實施例的半導體封裝。
半導體封裝500包含至少二個子封裝，舉例來說，第一子封裝301以及第二子封裝302。本揭露提供一種製造半導體封裝500的方法，包含形成第一子封裝301以及第二子封裝302，接著，將第一子封裝 301堆疊在第二子封裝 302上方。製造半導體封裝500的第一子封裝301或第二子封裝302的子方法將在下文詳細地描述。
第2圖為根據本發明一些實施例之製造半導體封裝500的第一子封裝301或第二子封裝302的子方法M100之流程圖。如第2圖所示，子方法M100包含操作S102、操作S104、操作S106、操作S108、操作S110、操作S112以及操作S114。
第3-10圖繪示根據本發明一些實施例之子方法M100的製程之各階段剖面圖。
參照操作S102，如第3圖所示，提供第一支撐基板 100，其上具有至少二個第一半導體晶片12以及第二半導體晶片13。第二半導體晶片13 設置在第一半導體晶片12之間。具體而言，各第一半導體晶片12及第二半導體晶片13的有效側(active side)朝向下地固定(mounted facedown)在第一支撐基板 100上。
在一些實施列中，第一半導體晶片12包含記憶體電路，以及第二半導體晶片13 包含邏輯電路。在其他實施例中，第一半導體晶片12 實質上為記憶體晶片，並且第二半導體晶片13實質上為邏輯晶片。
儘管圖示繪示一組晶片，包含二個第一半導體晶片12以及一個第二半導體晶片13，但本發明不限於此。即，二個或更多組晶片可依矩陣方式設置在第一支撐基板 100上。
在一些實施例中，第一支撐基板100由矽、玻璃、具有適當熱膨脹係數（Coefficient of thermal expansion ; CTE）的複合材料或其他能夠支持超過200°C的製程溫度之材料製成。第一支撐基板100是暫時的犧牲支撐晶片基板。
在一些實施例中，形成附著劑14在第一支撐基板100及第一、第二半導體晶片12、13之間。在其他實施例中，附著劑14實質上為熱解膠帶。在特定的實施例中，附著劑14實質上為UV光固化解膠膜(UV-release tape)。
在一些實施例中，各第一半導體晶片12包含多個矽通孔(Through Silicon Vias; TSVs)15，實質上垂直於第一支撐基板100。各矽通孔15具有第一端151及第二端152，第一端151連結至第一支撐基板100以及第二端152嵌入第一半導體晶片12。在一些實施例中，矽通孔15由銅、金、銀、鈀或其等同物製成，但材料不在此限。
參照操作S104，如第4圖所示，形成塑模層16覆蓋第一支撐基板100、第一半導體晶片12以及第二半導體晶片13。換句話說，各第一半導體晶片12與第二半導體晶片13被塑模層16所隔開。
在一些實施例中，塑模層16實質上由包括環氧樹脂或任何適當材料的密封劑(encapsulant)或模制化合物(molding compound)所製成。
參照操作S106，如第5圖所示，薄化塑模層16、第一半導體晶片以及第二半導體晶片13，從而矽通孔15的各第二端152從薄化的第一半導體晶片12’曝露出。
在一些實施例中，藉由使用拋光或研磨製程，例如化學機械拋光（chemical mechanical polishing ;CMP）或任何合適的製程，施加薄化製程於塑模層16、第一半導體晶片12以及第二半導體晶片13。
在一些實施例中，如第5圖所示，矽通孔15的上表面15’T、薄化的塑模層16’的上表面16’T、薄化的第一半導體晶片12’的上表面12’T、以及薄化的第二半導體晶片13’的上表面13’T為共平面。
參照操作S108，如第6圖所示，形成銲墊層18覆蓋在塑模層16’的上表面16’T、第一半導體晶片12’的上表面12’T、以及第二半導體晶片13’的上表面13’T。
在一些實施例中，銲墊層18包含有效墊18A以及虛設墊18D。各有效墊18A設置在矽通孔15的上表面15’T的對應一者上，以及虛設墊18D設置在第二半導體晶片13’上。在一些實施例中，有效墊18A以及虛設墊18D由金屬製成，例如，鋁。
在一些實施例中，銲墊層18包含用以絕緣的鈍化材料18P。舉例而言，鈍化材料18P由氧化矽、氮化矽、聚醯亞胺（PI），聚苯並噁唑（PBO）、苯並環丁烯（BCB）、環氧樹脂或其他具有類似絕緣和結構特性的材料製成。
在一些實施例中，銲墊層18使用物理氣相沉積、化學氣相沉積、印刷、層壓、旋塗、噴塗、燒結或熱氧化形成。舉例來說，分別形成有效墊18A以及虛設墊18D在第一半導體晶片12’以及第二半導體晶片13’上，然後，形成鈍化材料18P覆蓋有效墊18A及虛設墊18D。接著，這裡使用研磨製程以從鈍化材料18P暴露出有效墊18A及虛設墊18D。
參照操作S110，如第7圖所示，從矽通孔15的下表面15L、塑模層16’的下表面16’L、第一半導體晶片12’的下表面12’L、以及第二半導體晶片13’的下表面13’L移除第一支撐基板100。具體來說，執行剝離製程(de-bonding)以將第一支撐基板100從塑模層16’、第一及第二半導體晶片12’ 13’卸下。在一些實施例中，施加電射、UV或熱能以激發第一支撐基板100與第一及第二半導體晶片12’、13’之間的表面剝離。
在一些實施例中，參照第7圖，在執行操作S110之前，附接第二支撐基板102至銲墊層18。具體而言，執行壓接製程以附接第二支撐基板102至銲墊層18，接著第一支撐基板100被卸下。
在一些實施例中，第二支撐基板102由矽、玻璃、具有適當熱膨脹係數的複合材料或其他能夠支撐超過200°C的製程溫度的材料製成。第二支撐基板102是暫時的犧牲支撐晶圓基板。在一些實施例中，使用熱解黏膠帶或UV光固化解膠膜帶來附接第二支撐基板102至銲墊層18。
參照操作S112，如第8圖所示，在矽通孔15的下表面15L、塑模層16’的下表面16’L、第一半導體晶片12’的下表面12’L、以及第二半導體晶片13’的下表面13’L下方形成多個重分佈層20 (Redistribution Layers; RLS)。
重分佈層20為一或多層晶圓級內連線結構。重分佈層20包含一或多個導電層20C以及絕緣層20I，例如，BCB重分佈層、PI重分佈層、以及PI/BCB鈍化保護。形成重分佈層20的製程溫度一般大於200°C，也可較低。重分佈層20提供了第一半導體晶片12’與第二半導體晶片13’的完整晶圓級內連線，更多細節將在下文描述。
在一些實施例中，如第8圖所示，重分佈層20在各第一半導體晶片12'以及第二半導體晶片13'之間電性連結。換句話說，來自第一半導體晶片12’的電性訊號可以傳送至第二半導體晶片13’，反之亦然。在一些實施例中，如第8圖所示，重分佈層20係電性連結至矽通孔15。
參照操作S114，如第9圖所示，形成多個凸塊22，並且連接至重分佈層20。在一些實施例中，凸塊22包含有效凸塊22A以及虛設凸塊22D。有效凸塊22A設置在各第一半導體晶片12’下方，以及虛設凸塊22D設置在第二半導體晶片13’下方。
使用電鍍方法形成凸塊22。在一些實施例中，凸塊22由一般的焊料、銅、鎳、金、銀或其等同物製成，但材料不限於此。
在此所使用的術語「虛設」指的是，墊以及凸塊形成非用以電性連結，而為了機械性的連結，並且術語「有效」指的是，墊以及凸塊形成用以提供電性連結。藉由虛設凸塊22D和虛設墊18D來增加第一半導體封裝301與第二半導體封裝302之間的機械結合強度，增加了如第1圖所示之半導體封裝500的可靠性。如此，第一子封裝301與第二子封裝302之間的界面分離(interfacial delamination)可以被抑制。
在一些實施例中，如第9圖所示，有效凸塊22A電性連結至矽通孔15，以及虛設凸塊22D未電性連結至矽通孔15。詳細地說，有效凸塊22A連結至重分佈層20，並且重分佈層20連結至矽通孔15，從而達到有效凸塊22A與矽通孔15之間的電性連結。如此，第一半導體晶片12’的電性訊號可以藉由有效凸塊22A電性地傳送至外部裝置。另一方面，虛設凸塊22D連結至重分佈層20的部20P，但部20P未連接至矽通孔15，因此，虛設凸塊22D未電性連結至矽通孔15。
參照第10圖，從銲墊層18移除第二支撐基板102。藉由執行與操作S110中所進行類似的剝離製程(de-bonding)，將第二支撐基板102從焊墊層18上分離。
再次參照第9圖，從銲墊層18移除第二支撐基板102之後，形成組裝結構250，接著將其切單(sigulation)為獨立的子封裝結構，即，如第9圖所示的第一子封裝301或第二子封裝302。第一子封裝301及第二子封裝302各包含二個第一半導體晶片12’、設置在二個第一半導體晶片12’之間的第二半導體晶片13’、塑模層16、銲墊層18、重分佈層20、以及凸塊22。舉例而言，在切單的製程中，使用金剛石砂輪將組裝結構250切割成單獨的子封裝。
使用根據本發明一些實施例之如第2圖所示的子方法M100，來形成第一子封裝301與第二子封裝302之後，藉由附接第一子封裝301的凸塊22至第二子封裝302的銲墊層18，將第一子封裝301堆疊在第二子封裝上，從而形成如第1圖所示的晶圓級半導體封裝500。
再次參照第1圖，在一些實施例中，使用堆疊黏合劑層30來附接第一子封裝301至第二子封裝302。在其他實施例中，如第1圖所示，堆疊黏合劑層30包覆各凸塊22。
圖式繪示晶圓級堆疊半導體封裝500，其中雖僅繪示二個子封裝301、302彼此堆疊，但本發明不限於此。即，二個或更多子封裝可以彼此堆疊。
在一些實施列中，如第１圖所示，將第一子封裝301堆疊在第二子封裝302上，第一子封裝301的各有效凸塊22A附接至第二子封裝302的有效墊18A的相應一者，以及第一子封裝301的各虛設凸塊22D附接至第二子封裝302的虛設墊的相應一者。
藉由在第一子封裝301以及第二子封裝302之間設置虛設凸塊22D，可以穩定第一子封裝301以及第二子封裝302的界面，而不會有界面分離或者剝離。
第11圖繪示根據本發明一些實施例之各第一子封裝301及各第二子封裝302上的有效凸塊22A及虛設凸塊22D的佈置圖。
如第11圖所示，從上視圖，虛設凸塊22D設置在第二半導體晶片13上，以及有效凸塊22A設置在第一半導體晶片12上。在一實施例中，虛設凸塊22D設置在第二半導體晶片13的多個拐角處。在其他實施例中，虛設凸塊22D設置在第二半導體晶片13的中心區域。在特定的實施例中，虛設凸塊22D沿著第二半導體晶片13的多個邊緣(edge)設置。
在一些實施例中，如第11圖所示，從上視圖，虛設凸塊22D設置在第一半導體晶片12的多個拐角處。
如第1圖所示，根據本發明一些實施例提供的半導體封裝500，包含將第一子封裝301堆疊在第二子封裝302上，使用如第1圖所示的方法M100來形成各第一子封裝301以及各第二子封裝302。
如第1圖所示，第一子封裝301與第二子封裝302實質上具有相同的結構。簡明的說，第一子封裝301與第二子封裝302各包含至少二個第一半導體晶片12以及設置在二個第一半導體晶片之間的第二半導體晶片13。多個塑模件40設置在各第一半導體晶片12以及第二半導體晶片13之間。
在一些實施例中，各第一半導體晶片12包含多個矽通孔15。在一些實施例中，矽通孔15的多個上表面15T、塑模件40的多個上表面40T、第一半導體晶片12的多個上表面12T，以及第二半導體晶13片的上表面13T為共平面。
在一些實施例中，各第一子封裝301以及各第二子封裝302的銲墊層18設置覆蓋在矽通孔15的多個上表面15T、塑模件40的多個上表面40T、第一半導體晶片12的多個上表面12T，以及第二半導體晶13片的上表面12T。
在一些實施例中，銲墊層18包含多個有效墊18A以及多個虛設墊18D，各有效墊18A設置在矽通孔15的上表面15T的相應一者上，以及虛設墊18D設置在第二半導體晶片13上。在一些實施例中，銲墊層18包含鈍化材料18P。
在一些實施例中，在矽通孔15的多個下表面15L、塑模件40的多個下表面40L、第一半導體晶片的12多個下表面12L、以及第二半導體晶片13的下表面13L之下方設置多個重分佈層20。在一些實施例中，各第一子封裝301以及各第二子封裝302的重分佈層20電性連結至矽通孔15。在一些實施例中，重分佈層20在各第一半導體晶片12以及第二半導體晶片13之間電性連結。
在一些實施例中，多個凸塊22連結至重分佈層20。在一些實施例中，各第一子封裝301以及各第二子封裝302的凸塊22包含多個有效凸塊22A以及多個虛設凸塊22D，有效凸塊22A設置在各第一半導體晶片12下方，以及虛設凸塊22D設置在第二半導體晶片13下方。
在一些實施例中，虛設凸塊22D設置在第二半導體晶片13的多個拐角處。
在一些實施例中，第一子封裝301的有效凸塊22A附接至第二子封裝302的有效墊18A的對應一者，以及第一子封裝301的虛設凸塊22D附接至第二子封裝302的虛設墊18D的對應一者。在一些實施例中，有效凸塊22A電性連結至矽通孔15，以及虛設凸塊22D未電性連結至矽通孔15。
在一些實施例中，第一子封裝301的凸塊22附接至第二子封裝302的銲墊層18。
本發明提供一種半導體封裝，藉由在子封裝之間的界面設置虛設凸塊及虛設墊，達到減少界面分離。
儘管已經在上述實施例中公開了本發明，但並不意圖限製本發明。在不脫離本發明的精神和範圍的情況下，本領域技術人員可以進行各種修改和修飾。因此，本發明的保護範圍應由所附的專利申請範圍來確定。
13，13’:第二半導體晶片 15，15’:矽通孔 14:附著劑 16，16’:塑模層 18:銲墊層 18A:有效墊 18D:虛設墊 18P:鈍化材料 20:重分佈層 20P:部 22:凸塊 22A:有效凸塊 22D:虛設凸塊 30:堆疊黏合劑層 40:塑模件 100:第一支撐基板 102:第二支撐基板 151:第一端 152:第二端 250:組裝結構 250:組裝結構 301:第一子封裝 302:第二子封裝 500:半導體封裝 12，12’:第一半導體晶片 12L，12’L，13L，13’L，15L，15’L，16’L，40L:下表面 12T，12’T，13T，15T，15’T，16’T，40T:上表面 M100:子方法 S102，S104，S106，S108，S110，S112，S114:操作
為了使本發明的上述和其他目的，特徵，優點和實施例更容易理解，附圖的詳細描述如下。 第1圖繪示根據本發明一些實施例的半導體封裝。 第2圖為根據本發明一些實施例之製造半導體封裝的第一子封裝或第二子封裝的子方法之流程圖。 第3-10圖繪示根據本發明一些實施例之子方法的製程之各階段剖面圖。 第11圖繪示根據本發明一些實施例之各第一子封裝及各第二子封裝上的有效凸塊及虛設凸塊的佈置圖。
無
13:第二半導體晶片
15:矽通孔
18:銲墊層
18A:有效墊
18D:虛設墊
18P:鈍化材料
20:重分佈層
22:凸塊
22A:有效凸塊
22D:虛設凸塊
30:堆疊黏合劑層
40:塑模件
301:第一子封裝
302:第二子封裝
500:半導體封裝
12:第一半導體晶片
12L，13L，15L，40L:下表面
12T，13T，15T，40T:上表面

Claims (19)

  1. 一種半導體封裝，包含：一第一子封裝堆疊於一第二子封裝上，該第一子封裝以及該第二子封裝各包含：至少二個第一半導體晶片，以及設置於該些第一半導體晶片之間的一第二半導體晶片，其中該第一半導體晶片各包含多個矽通孔(Through Silicon Vias；TSVs)；多個塑模件，設置於各該第一半導體晶片以及該第二半導體晶片之間，其中該些矽通孔的多個上表面、該些塑模件的多個上表面、該些第一半導體晶片的多個上表面，以及該第二半導體晶片的一上表面為共平面；一銲墊層，設置覆蓋於該些矽通孔的該些上表面，該些塑模件的該些上表面、該些第一半導體晶片的該些上表面，以及該第二半導體晶片的該上表面，其中該銲墊層包含多個有效墊以及多個虛設墊，各該有效墊設置在該些矽通孔的該些上表面的相應一者上，該些虛設墊設置在該第二半導體晶片的該上表面上；多個重分佈層(Redistribution Layers；RDLs)，在該些矽通孔的多個下表面、該些塑模件的多個下表面、該些第一半導體晶片的多個下表面，以及該第二半導體晶片的一下表面之下方設置；以及多個凸塊，連結至該些重分佈層，其中該第一子封裝藉由一堆疊黏合劑層附接至該第二 子封裝，且該第一子封裝的該些凸塊附接至該第二子封裝的該銲墊層。
  2. 如請求項1所述的半導體封裝，其中該銲墊層包含鈍化材料。
  3. 如請求項1所述的半導體封裝，其中該第一子封裝以及該第二子封裝的各該重分佈層電性連結至該些矽通孔。
  4. 如請求項3所述的半導體封裝，其中該些重分佈層在各該第一半導體晶片以及該第二半導體晶片之間電性連結。
  5. 如請求項1所述的半導體封裝，其中該第一子封裝以及該第二子封裝的該些凸塊各包含多個有效凸塊以及多個虛設凸塊，該些有效凸塊設置在各該第一半導體晶片下方，以及該些虛設凸塊設置在該第二半導體晶片下方。
  6. 如請求項5所述的半導體封裝，其中，從上視圖，該些虛設凸塊設置在該第二半導體晶片的多個拐角處。
  7. 如請求項5所述的半導體封裝，其中該第一子封裝的該些有效凸塊附接至該第二子封裝的該些有效墊的對應一者，以及該第一子封裝的該些虛設凸塊附接至該第二子封裝的該些虛設墊的對應一者。
  8. 如請求項5所述的半導體封裝，其中該些有效凸塊電性連結至該些矽通孔，以及該些虛設凸塊未電性連結至該些矽通孔。
  9. 如請求項1所述的半導體封裝，其中該第一子封裝以及該第二子封裝的各該凸塊包含：多個有效凸塊、多個第一虛設凸塊，以及多個第二虛設凸塊，該些有效凸塊以及該些第一虛設凸塊設置在該些第一半導體晶片下方，以及該些第二虛設凸塊設置在第二半導體晶片下方。
  10. 如請求項9所述的半導體封裝，其中該些有效凸塊電性連結至該些矽通孔，並且該些第一虛設凸塊以及該些第二虛設凸塊未電性連結至該些矽通孔。
  11. 一種半導體封裝的製造方法，包含：形成一第一子封裝以及一第二子封裝，其中形成該第一子封裝及該第二子封裝各包含下列步驟：(a)提供設置於一第一支撐基板上至少二個第一半導體晶片以及該些第一半導體晶片之間的一第二半導體 晶片，其中該些第一半導體晶片各包含實質上垂直於該第一支撐基板的多個矽通孔，以及各該矽通孔具有連接至該第一支撐基板的一第一端，以及嵌入至該第一半導體晶片的一第二端；(b)形成一塑模層，覆蓋該第一支撐基板、該些第一半導體晶片以及該第二半導體晶片；(c)薄化該塑模層、該些第一半導體晶片以及該第二半導體晶片，其中該些矽通孔的該些第二端從該些第一半導體晶片暴露出來，其中該些矽通孔的多個上表面、該薄化的該塑模層的多個上表面、該薄化的該第一半導體晶片的多個上表面以及該薄化的該第二半導體晶片的一上表面為共平面；(d)形成一銲墊層覆蓋在該些矽通孔的該些上表面以及該薄化的該第二半導體晶片的該上表面；(e)從該些矽通孔的多個下表面、該塑模層的多個下表面、該些第一半導體晶片的多個下表面以及該第二半導體晶片的一下表面移除該第一支撐基板；以及(f)形成多個重分佈層在該些矽通孔的該些下表面、該塑模層的該些下表面、該些第一半導體晶片的該些下表面以及該第二半導體晶片的該下表面的下方；(g)形成多個凸塊，連結至該些重分佈層；以及藉由附接該第一子封裝的該些凸塊至該第二子封裝的該銲墊層，堆疊該第一子封裝在該第二子封裝上方，其中該第一子封裝藉由一堆疊黏合劑層附接至該第二子封 裝。
  12. 如請求項11所述的製造方法，其中形成該第一子封裝及該第二子封裝更包含：在步驟(e)之前，附著一第二支撐基板至該銲墊層。
  13. 如請求項12所述的製造方法，其中形成該第一子封裝及該第二子封裝更包含：在步驟(g)之後，從該銲墊層移除該第二支撐基板。
  14. 如請求項11所述的製造方法，其中該第一子封裝及該第二子封裝的各該銲墊層包含：多個有效墊以及多個虛設墊，各該有效墊設置在該些矽通孔的該些上表面的對應一者上，以及該些虛設墊設置在該第二半導體晶片上。
  15. 如請求項11所述的製造方法，其中該第一子封裝及該第二子封裝的各該重分佈層係電性連結至該些矽通孔。
  16. 如請求項15所述的製造方法，其中該些重分佈層在各該第一半導體晶片以及該第二半導體晶片之間電性連結。
  17. 如請求項14所述的製造方法，其中該第一子封裝及該第二子封裝的各該凸塊包含：多個有效凸塊以及多個虛設凸塊，該些有效凸塊設置於各該第一半導體晶片下方，以及該些虛設凸塊設置於該第二半導體晶片下方。
  18. 如請求項17所述的製造方法，其中該些有效凸塊電性連結至該些矽通孔，以及該些虛設凸塊未電性連結至該些矽通孔。
  19. 如請求項17所述的製造方法，其中該第一子封裝的該些有效凸塊附接至該第二子封裝的該些有效墊的對應一者，以及該第一子封裝的該些虛設凸塊附接至該第二子封裝的該些虛設墊的對應一者。
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