TWI660435B - 使用暫時載體將多層結構平坦化之晶片封裝方法 - Google Patents

使用暫時載體將多層結構平坦化之晶片封裝方法 Download PDF

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TWI660435B
TWI660435B TW106139131A TW106139131A TWI660435B TW I660435 B TWI660435 B TW I660435B TW 106139131 A TW106139131 A TW 106139131A TW 106139131 A TW106139131 A TW 106139131A TW I660435 B TWI660435 B TW I660435B
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layer
dielectric layer
redistribution layer
redistribution
conductive
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TW106139131A
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TW201842593A (zh
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徐宏欣
林南君
張簡上煜
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力成科技股份有限公司
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Abstract

一種晶片封裝方法，包含於一第一暫時載體上形成一第一重佈層及一第一介電層，從而產生複數個第一導電介面於該第一暫時載體上，每對相鄰之第一導電介面具有一第一間距；於該第一重佈層之一第一部份及該第一介電層上形成一第二介電層，從而覆蓋該第一重佈層之該第一部份，及露出該第一重佈層之一第二部份；於該第二介電層之上方形成一第二重佈層及一第三介電層，從而產生複數個第二導電介面及一電路，其中該電路係至少由該第一重佈層及該第二重佈層形成。每對相鄰之第二導電介面具有一第二間距，且該第二間距大於該第一間距。

Description

使用暫時載體將多層結構平坦化之晶片封裝方法
本發明係關於一種晶片封裝方法，尤指一種使用暫時載體將多層結構平坦化之晶片封裝方法。
在先前技術，包含一組介電層及一組重佈層之多層結構係從底側形成，在底側，可形成具有較大間距的導電介面。舉例來說，第1圖係先前技術中，具有較大間距之複數個導電介面的封裝結構100的示意圖。在封裝結構100中，晶片單元110可設置於多層結構120上。多層結構120可包含介電層120p1-120p2及兩金屬層120r1-120r2。藉由圖案化介電層120p1-120p2及金屬層120r1-120r2，可設計及形成電路。晶片單元110可包含晶片100c、及一組焊凸塊1101-1104，其係用以存取晶片100c。
如第1圖所示，金屬層120r2係被圖案化以形成具有較小間距的複數個導電介面1301-1304，金屬層120r1係被圖案化以形成具有較大間距的導電介面140。金屬層120r1比金屬層120r2更先被圖案化。當載體在沒有任何結構形成於其上之前，可為平坦狀態，所以當第一層材料形成於載體上時，可不致發生翹曲問題之困擾，但當堆疊形成於載體上的層數增加時，會造成載體翹曲，且 越加嚴重，因此，越後續形成的結構就越容易受到翹曲問題的干擾，從而有害於製程良率。
由於具有較小間距的導電介面1301-1304係用以連接晶片單元110，導電介面1301-1304比導電介面140更為關鍵。然而，若金屬層120r1及介電層120p1先被形成，則後續形成的導電介面1301-1304則不甚理想。如第1圖所示，導電介面1301及1304比導電介面1302及1303位置更高，這是因為介電層120p1-120p2及金屬層120r1-120r2之分佈，使介電層120p2的上表面不均勻所致。如第1圖所示，導電介面1301至1304的高度變化， 導致當設置晶片單元110於多層結構120上時，導電介面1302、1303無法接觸對應之焊凸塊1102、1103，故使封裝結構100的良率下降。
本發明實施例提供一種晶片封裝方法，包含於一第一暫時載體上形成一第一重佈層及一第一介電層，從而產生複數個第一導電介面於該第一暫時載體上，每對相鄰之第一導電介面具有一第一間距；於該第一重佈層之一第一部份及該第一介電層上形成一第二介電層，從而覆蓋該第一重佈層之該第一部份，及露出該第一重佈層之一第二部份；於該第二介電層之上方形成一第二重佈層及一第三介電層，從而產生複數個第二導電介面及一電路，其中該電路係至少由該第一重佈層及該第二重佈層形成，每對相鄰之第二導電介面具有一第二間距，且該第二間距大於該第一間距。
100‧‧‧封裝結構
110‧‧‧晶片單元
120、255‧‧‧多層結構
120r1-120r2‧‧‧金屬層
120p1-120p2‧‧‧介電層
1101-1104‧‧‧焊凸塊
100c‧‧‧晶片
140‧‧‧導電介面
20‧‧‧封裝結構
T1、T2‧‧‧暫時載體
2101-2106‧‧‧第一導電介面
2201-2204‧‧‧第二導電介面
L1‧‧‧第一間距
L2‧‧‧第二間距
R1‧‧‧第一重佈層
R2‧‧‧第二重佈層
P1‧‧‧第一介電層
A1‧‧‧脫模層
255c‧‧‧電路
S1‧‧‧平面
R11‧‧‧第一部份
R12‧‧‧第二部份
510‧‧‧晶片
5101-5106‧‧‧導電凸塊
5201-5206‧‧‧焊點
530‧‧‧底部填充層
610‧‧‧模塑層
D‧‧‧距離
7101-7104‧‧‧焊球
800‧‧‧方法
810-830、8101-8104、810a-810d‧‧‧步驟
第1圖係先前技術的封裝結構的示意圖。
第2至7圖係實施例中，形成封裝結構的製程示意圖。
第8圖係實施例中，形成封裝結構的方法流程圖。
第9圖係第8圖之實施例的細節步驟圖。
第10圖係第8圖之實施例的細節步驟圖。
第2至7圖係實施例中，形成封裝結構20的製程示意圖。封裝結構20可見於第7圖。
第2圖中，可如下述形成多層結構255。於暫時載體T1上可形成第一重佈層R1及第一介電層P1，從而產生複數個第一導電介面2101-2106。第一導電介面2101-2106係於暫時載體T1上實質上共平面。第一導電介面2101-2106中，兩相鄰之第一導電介面的距離可至少為第一間距L1。第2圖顯示具有六個第一導電介面2101-2106，此僅為舉例，並非用以限制本發明之範圍。根據實施例，可在暫時載體T1及第一介電層P1形成的平面S1之間，形成脫模層A1。
於第一重佈層R1及第一介電層P1上方可形成第二介電層P2。當形成第二介電層P2時，可於第一重佈層R1及第一介電層P1上方形成一介電層，且移除該介電層中無用的部份，以圖案化該介電層。第二介電層P2可覆蓋第一重佈層R1之第一部份R11，及露出第二部份R12。第二部份R12可填入導電材料，從而電性連接第一重佈層R1及另一重佈層(例如第2圖所示的第二重佈層R2)。
第2圖之實施例中，多層結構255可包含三層介電層P1-P3及兩層重 佈層R1-R2，因此，第二重佈層R2可為最上層之重佈層，第三介電層P3可為最上層之介電層。然而，根據另一實施例，於暫時載體T1上形成之多層結構可包含更多介電層及重佈層。舉例而言，可用四層介電層及三層重佈層形成多層結構。
第2圖中，第一重佈層R1及第二重佈層R2可形成電路255c，第二重佈層R2及第三介電層P3可產生複數個第二導電介面2201-2204。每對相鄰之第二導電介面(例如2203及2204)之間的距離可至少為第二間距L2，且第二間距L2大於該第一間距。同理，第2圖之第二導電介面的數量係四個，此數量僅為舉例。
如上述，多層結構255可包含比第2圖更多的介電層及重佈層。舉例而言，可於第二介電層P2及第三介電層P3之間另形成第四介電層，或更多介電層亦可，並可移除第四介電層之一部分，以圖案化第四介電層。於第二重佈層R2及第一重佈層R1之間可形成第三重佈層，或更多重佈層亦可，並可移除第三重佈層之一部份以圖案化第三重佈層。第三介電層P3之一部份亦可被移除，以圖案化第三介電層P3。當多層結構255包含上述的第四介電層及第三重佈層，電路255c可至少由第一重佈層R1、第二重佈層R2及第一重佈層R1與第二重佈層R2之間的第三重佈層形成。同理，當多層結構255包含第四重佈層，電路255c可由第一至第四重佈層形成，以此類推。
第3圖中，暫時載體T2可被置放在第二重佈層R2及第三介電層P3上，以當第一暫時載體T1被移除後支撐多層結構255。在暫時載體T2、第二重佈層R2及第三介電層P3之間，可形成黏著層A2。黏著層A2可為黏著材料形成 之塗層，或黏附薄膜。如第3圖所示，第二導電介面2201-2204可由圖案化第三介電層P3以露出第二重佈層R2之一部份而形成。使用具彈性的黏著層A2，可降低暫時載體T2與多層結構255之間的應力。
藉由將多層結構255設置於暫時載體T1上，平面S1可為平坦表面。第4圖係導電介面2101-2106及2201-2204形成後，移除暫時載體T1的示意圖。當移除暫時載體T1時，可將脫模層A1用特定之光線曝照、加熱、或以適合的方式處理。
第5圖中，多層結構255可翻轉，以使導電介面2101-2106朝上，且晶片510可對應電性連接於導電介面2101-2106。根據實施例，複數個焊點5201-5206可設置於導電介面2101-2106上，然後晶片510之複數個導電凸塊5101-5106可設置於焊點5201-5206上。根據另一實施例，焊點5201-5206之第一側可設置於導電凸塊5101-5106，且焊點5201-5206之第二側可設置於導電介面2101-2106。另可將底部填充材料填充於焊點5201-5206周圍以形成底部填充層530，以提高可靠度。
第6圖中，可填充模塑材料以形成模塑層610。模塑層610可包覆晶片510。第7圖中，暫時載體T2可被移除，複數個焊球7101-7104可被設置於導電介面2201-2204上。相比於第6圖，第7圖中，包含多層結構255與模塑層610之結構可被翻轉，使導電介面2201-2204朝上，以置放焊球7101-7104。根據實施例，模塑層610可被削薄以減少從晶片510到模塑層610之表面的距離D，以減低封裝結構20的厚度。
根據實施例，第5圖之導電凸塊5101-5106可為導電柱體凸塊，例如銅柱體凸塊。關於導電凸塊5101-5106及焊點5201-5206所形成的凸塊結構，每個凸塊結構中，較厚部份可為銅柱體，中段部份可為鎳，近似於球面之部份可為焊點。上述的重佈層可用導電材料(例如銅)以電鍍製造。上述的介電層如P1-P3，可用聚亞醯胺製造。形成介電層時，可使用光感應介電材料，以使介電層被圖案化時，可用具有適當波長的光線曝照，且可執行顯影(develop)製程與固化(cure)製程，以使圖案化後的介電層可被固定。
根據實施例，前述的暫時載體T1及T2可用剛性材料製造，例如玻璃、陶瓷或矽等。如上述，靠近導電介面2201-2204的暫時載體T2可被選擇性使用。因此，在一實施例中，當未使用暫時載體T2時，移除暫時載體T2的步驟可予以省略。
第8圖係實施例中，產生晶片結構20之晶片封裝方法800的流程圖。第2圖可對應於第8圖之步驟810-830。方法800可包含： 步驟810：於第一暫時載體T1上形成第一重佈層R1及第一介電層P1，從而產生複數個第一導電介面2101-2106於第一暫時載體T1上，每對相鄰之第一導電介面具有第一間距L1； 步驟820：於第一重佈層R1之第一部份R11及第一介電層P1上形成第二介電層P2，從而覆蓋第一重佈層R1之第一部份R11，及露出第一重佈層R1之第二部份R12；及 步驟830：於第二介電層P2之上方形成第二重佈層R2及第三介電層P3，從而產生複數個第二導電介面2201-2204及電路255c，其中電路255c係至少由第一重佈層R1及第二重佈層R2形成，每對相鄰之第二導電介面具有第二間 距L2，且第二間距L2大於第一間距L1。
根據實施例，步驟810可包含下列的步驟8101-8104。第9圖可對應於步驟8101-8104，其包含：步驟8101：於第一暫時載體T1上形成第一介電層P1；步驟8102：移除第一介電層P1之一部份，從而圖案化第一介電層P1；步驟8103：於第一暫時載體T1及第一介電層P1上形成第一重佈層R1，從而形成複數個第一導電介面2101-2106；及步驟8104：移除第一重佈層R1之一部份，從而圖案化第一重佈層R1。
根據第9圖之實施例，可於形成及圖案化第一重佈層R1之前，先形成及圖案化第一介電層P1。
根據另一實施例，步驟810可包含下列步驟810a-810d。第10圖係第8圖之步驟810包含之步驟810a-810d的流程圖，其包含：步驟810a：於第一暫時載體T1上形成第一重佈層R1；步驟810b：移除第一重佈層R1之一部份，從而圖案化第一重佈層R1，以形成複數個第一導電介面2101-2106；步驟810c：於第一暫時載體T1及第一重佈層R1之剩餘部份上形成第一介電層P1；及步驟810d：移除第一介電層P1之一部份，從而圖案化第一介電層P1。
根據第10圖之實施例，可先形成及圖案化第一重佈層R1，再形成及 圖案化第一介電層P1。
綜上，根據實施例，本發明可形成平坦的平面S1，故當晶片510被結合至多層結構255時，所有的導電介面2101-2106可被連接到晶片510之焊點5201-5206，從而可改善封裝結構20的良率，且可使覆晶接合製程有更大的調整範圍。以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。

Claims (7)

  1. 一種晶片封裝方法，包含：於一第一暫時載體上形成一第一重佈層及一第一介電層，所述第一介電層具有最靠近所述第一暫時載體的一第一表面，所述第一重佈層包含與所述第一表面共平面之複數個第一導電介面，每對相鄰之第一導電介面具有一第一間距；於該第一重佈層之一第一部份及該第一介電層上形成一第二介電層，從而覆蓋該第一重佈層之該第一部份，及露出該第一重佈層之一第二部份；於該第二介電層之上方形成一第二重佈層及一第三介電層，從而產生複數個第二導電介面及一電路，其中該電路係至少由該第一重佈層及該第二重佈層形成，每對相鄰之第二導電介面具有一第二間距，且該第二間距大於該第一間距；於該第二重佈層及該第三介電層上置放一第二暫時載體，從而當該第一暫時載體被移除後，支撐該第一重佈層、該第二重佈層、及該第一介電層至該第三介電層；移除該第一暫時載體，以暴露出該複數個第一導電介面；翻轉具有該第一介電層、該第一重佈層、該第二介電層、該第二重佈層及該第三介電層之一多層結構，從而使該複數個第一導電介面朝向上方；以及將一晶片接附於該複數個第一導電介面上，其中包括於該複數個第一導電介面上直接設置該晶片之複數個焊點，且該複數個焊點的每一個係該晶片之一導電凸塊之一部份。
  2. 如請求項1所述之方法，其中於該第一暫時載體上形成該第一重佈層及該第一介電層，包含：於該第一暫時載體上形成該第一介電層；移除該第一介電層之一部份，從而圖案化該第一介電層；於該第一暫時載體及該第一介電層上形成該第一重佈層，從而形成該複數個第一導電介面；及移除該第一重佈層之一部份，從而圖案化該第一重佈層。
  3. 如請求項1所述之方法，其中於該第一暫時載體上形成該第一重佈層及該第一介電層，包含：於該第一暫時載體上形成該第一重佈層；移除該第一重佈層之一部份，從而圖案化該第一重佈層，以形成該複數個第一導電介面；於該第一暫時載體及該第一重佈層之一剩餘部份上形成該第一介電層；及移除該第一介電層之一部份，從而圖案化該第一介電層。
  4. 如請求項1所述之方法，另包含：於該第二介電層及該第三介電層之間形成一第四介電層；移除該第四介電層之一部份，從而圖案化該第四介電層；於該第二重佈層及該第一重佈層之間形成一第三重佈層；及移除該第三重佈層之一部份以圖案化該第三重佈層；其中該電路係至少由該第一重佈層、該第二重佈層及該第三重佈層形成。
  5. 如請求項1所述的方法，其中將該晶片接附於該複數個第一導電介面上，另包含：將一底部填充材料填充於該晶片之該導電凸塊周圍以形成一底部填充層。
  6. 如請求項1所述的方法，另包含：填充一模塑材料以形成一模塑層，該模塑層包覆該晶片。
  7. 如請求項1所述的方法，另包含：移除該第二暫時載體；及於該複數個第二導電介面上設置複數個焊球。
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