TWI741207B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

Info

Publication number
TWI741207B
TWI741207B TW107129211A TW107129211A TWI741207B TW I741207 B TWI741207 B TW I741207B TW 107129211 A TW107129211 A TW 107129211A TW 107129211 A TW107129211 A TW 107129211A TW I741207 B TWI741207 B TW I741207B
Authority
TW
Taiwan
Prior art keywords
rdl
semiconductor die
encapsulant
semiconductor device
semiconductor
Prior art date
Application number
TW107129211A
Other languages
English (en)
Other versions
TW201921532A (zh
Inventor
全炫錫
雪姆斯 Ｕ 阿利霏恩
辰 Ｈ 游
翠西 Ｎ 特南
Original Assignee
美商美光科技公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商美光科技公司 filed Critical 美商美光科技公司
Publication of TW201921532A publication Critical patent/TW201921532A/zh
Application granted granted Critical
Publication of TWI741207B publication Critical patent/TWI741207B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一種半導體裝置具有一半導體晶粒、一重佈層(RDL)及一囊封劑。該RDL層可形成於該半導體晶粒之一第一表面上。該囊封劑可圍封該半導體晶粒之一第二表面及側表面。該囊封劑可圍封該RDL之側部。

Description

半導體裝置
本發明大體上係關於半導體裝置及方法。
一積體電路(IC)可為半導體材料(例如，矽)之一個小平片(「晶片」)上之一組電子電路。IC可包含整合至一小晶片中之較大數目個微型電晶體，以獲得可小於且快於由離散電路組件構成之電路的電路。與在自一晶圓切割個別單元之後將其等組裝於封裝中之一程序相比，可在一晶圓級封裝IC。在IC最終形式中，IC可為具有按與電路板組裝程序相容之一輸入/輸出(I/O)間距附接之凸塊或焊球之一陣列圖案之一晶粒。
一半導體晶粒總成可包含複數個記憶體晶粒，且與複數個記憶體晶粒相關聯之基板可為一有機或無機基板。半導體晶粒總成可用於各種電子應用中，諸如個人電腦、蜂巢式電話、數位相機及其他半導體裝置。半導體裝置可包含透過複數個導電結構(例如，金屬、線、導電線、銲料凸塊等)耦合至一基板之至少一個半導體晶粒。複數個導電結構可在幫助半導體晶粒連接至基板之一重佈層內。重佈層可曝露至來自半導體裝置外部之條件，此可在一組裝程序期間及/或使用期間導致界面脫層、引起破裂之機械應力、水分影響及其他問題。半導體晶粒可包含功能構件，諸如記憶體胞、處理器電路、成像器組件及互連電路。
一種半導體裝置可包含一半導體晶粒、一重佈層(RDL)及一囊封劑。RDL層可形成於半導體晶粒之一第一表面上且圍封第一表面。囊封劑可圍封半導體晶粒之一第二表面及側表面。囊封劑可圍封RDL之側部。
一種用於形成一半導體裝置之程序可導致附接至一重佈層(RDL)之一晶粒。在至少一項實施例中，RDL可為可直接製造於一半導體晶粒上或建造於一載體上之一組合層。接著可將RDL轉移至晶粒而非使用一預形成基板。晶粒可圍封於包圍晶粒之一囊封劑(例如，一有機材料層、一環氧樹脂模塑料(EMC)等)中。數個互連結構(例如，一互連結構、一銅柱凸塊、一金凸塊等)及/或額外連接組件可耦合至RDL且用於將半導體裝置電連接至數個其他半導體裝置及/或一半導體裝置之其他組件。互連結構可用於將一晶粒上之一電路連接至一封裝晶片上之一接針。互連結構可為一電鍍結構。例如，可使用銅、鎳、錫銀、銀、廢金屬或另一金屬(包含所列金屬之合金)之一電解沈積形成一塗層以形成一互連結構及/或一柱凸塊。
在一些先前做法中，RDL之一邊緣可曝露(例如，未圍封於囊封劑內)至來自半導體裝置外部之條件，此可在一組裝程序期間及/或使用期間導致界面脫層、引起破裂之機械應力及水分影響及其他問題。如下文進一步描述，在至少一項實施例中，RDL之邊緣可圍封於一囊封劑(例如，一有機材料層、一EMC)層內。藉由將RDL層之邊緣圍封於囊封劑(例如，一有機材料層、一EMC層)內，RDL可受到保護以防形成程序期間及/或使用期間的各種不利條件。
在至少一項實施例中，可在耦合至RDL層之數個互連結構(例如，焊球)之間形成囊封劑。例如，一第一互連結構與一第二互連結構之間的一囊封劑可沿著第一互連結構及第二互連結構之各者之互連結構之至少一部分且沿著RDL在其等之間的空間中形成。互連結構之間的囊封劑可保護互連結構之一接頭以防故障(例如，在半導體裝置之測試期間)。
在一些先前做法中，在一扇出晶圓級封裝程序(FOWLP)期間，附接至RDL之一互連結構(例如，一焊球)可直接耦合至印刷電路板(PCB)。此可引起在一板級測試期間產生之熱機械應力。歸因於封裝與PCB之間的一硬度差異，可在一墜落測試期間發生一接頭故障，且可歸因於封裝與PCB之間的一熱膨脹係數(CTE)差異而發生一銲料接頭故障。在下文描述之至少一項實施例中，藉由用囊封劑填充互連結構之間的空間，可最小化CTE差異之效應且減小熱機械應力。
一半導體裝置可包含數個製造物品，包含例如積體電路(IC)晶粒、成像器晶粒、感測器晶粒及/或具有其他半導體構件之晶粒。雖然圖1A至圖4H中繪示半導體裝置之數個實例，但實例不限於此。可以數種方式更改及/或修改組件及/或半導體構件。
在本發明之以下詳細描述中，參考形成本發明之一部分且其中藉由繪示展示可如何實踐本發明之一或多項實施例之隨附圖式。充分詳細描述此等實施例以使一般技術者能夠實踐本發明之實施例，且應理解，可在不脫離本發明之範疇之情況下利用其他實施例且可做出程序、電及/或結構改變。
本文中之圖遵循一編號慣例，其中首位數字或前幾位數字對應於圖式圖號且其餘數字識別圖式中之一元件或組件。可藉由使用類似數字識別不同圖之間的類似元件或組件。例如，114可指代圖1A中之元件「14」，且一類似元件可在圖2A中指代為214。而且，如本文中使用，「數個」特定元件及/或構件可指代此等元件及/或構件之一或多者。
圖1A係根據本發明之數項實施例之一半導體裝置101之一實例。半導體裝置101可包含一記憶體晶片110。記憶體晶片110可為例如包含半導體材料之一單一平片上之一組電子電路之一積體電路。半導體材料可為矽、玻璃或其他材料。
半導體裝置101可包含一重佈層112，其係一介電質。一重佈層(RDL) 112指代記憶體晶片110上之一額外金屬層，其與額外半導體裝置(諸如額外位置中之一積體電路)進行輸入/輸出接觸。RDL 112可為記憶體晶片110上之一額外佈線層，其使記憶體晶片110能夠自記憶體晶片110上之不同位置向外接合，從而使晶片對晶片接合更容易。RDL 112之佈線118可電耦合至一額外電接觸件(諸如互連結構120-5，如繪示)。
半導體裝置101可包含圍封(例如，包圍、覆蓋等)記憶體晶片110之一囊封劑(例如，一有機材料層、一環氧樹脂模塑料(EMC)) 114。囊封劑114之一第一側部116-1可圍封RDL 112之一第一邊緣，且囊封劑114之一第二側部116-2可圍封RDL 112之一第二邊緣。歸因於囊封劑114包含高機械強度及高生產率之性質，囊封劑114可用於囊封半導體裝置101之部分。囊封劑114係固態環氧樹脂聚合物，其等經加熱至一液體且接著可注射於一電路上方以保護電路。藉由用第一側部116-1及第二側部116-2覆蓋RDL 112，RDL 112之邊緣受到此等性質保護且可避免界面脫層、由水分引起之破裂且減小RDL 112之邊緣上之熱機械應力之效應。圍封RDL 112之邊緣之囊封劑114防止透過RDL 112之一側壁之水分吸收。
記憶體晶片110可透過RDL 112電耦合至數個互連結構(諸如焊球)。如繪示，記憶體晶片110電耦合至互連結構120-1、120-2、120-3、120-4、120-5，如藉由將記憶體晶片110電耦合至互連結構120-5之佈線118繪示。
圖1B係根據本發明之數項實施例之一半導體裝置101之一部分之一實例。圖1B係一記憶體晶片(諸如圖1A中繪示之記憶體晶片110)之一仰視圖之一實例。雖然圖1A中繪示五(5)個互連結構(例如，焊球) (展示為互連結構120-1至120-5)，但圖1B中繪示更大數目個互連結構，為易於繪示，其等之一第一者標記為互連結構120。半導體裝置101包含一重佈層112及一囊封劑(例如，EMC) 114。如自圖1B中之一仰視圖繪示，囊封劑114延伸超出RDL 112之一邊緣以提供對RDL 112之邊緣之保護。
圖2A係根據本發明之數項實施例之一半導體裝置202之一實例。半導體裝置202包含由一囊封劑(例如，一有機材料層、一環氧樹脂模塑料(EMC)) 214圍封之一半導體晶粒210及一重佈層(RDL) 212。一重佈層(RDL) 212指代記憶體晶片210上之一額外金屬層，其與額外半導體裝置(諸如額外位置中之一積體電路)進行輸入/輸出接觸。RDL 212可為記憶體晶片210上之一額外佈線層，其使記憶體晶片210能夠自記憶體晶片210之不同位置向外接合，從而使晶片對晶片接合更容易。RDL 212可耦合至數個互連結構(例如，焊球) 220-1、220-2、220-3、220-4、220-5、220-6、220-7 (本文中稱為互連結構220)，其等透過RDL 212及互連結構220將半導體晶粒210耦合至一印刷電路板(PCB) 222。
囊封劑214圍封半導體晶粒210、RDL 212且在互連結構220之間。以此方式，圍封RDL 212之兩個邊緣以保護RDL 212以防熱機械應力及由水分引起之界面脫層/破裂。RDL 212之下側上之互連結構220之間的部分由囊封劑214圍封且保護RDL 212面向PCB 222之一側且覆蓋銲料接頭，此改良板級可靠性(BLR)統計。取代一底填充(UF)材料，囊封劑214圍封RDL 212面向PCB 222之側。歸因於囊封劑214覆蓋RDL 212面向PCB 222之側，RDL 212之翹曲減小。出於闡釋性目的在圖2B中擴展半導體裝置202之一部分211。
圖2B係根據本發明之數項實施例之一半導體裝置之一部分211之一實例。半導體裝置之部分211包含由一囊封劑(例如，一有機材料層EMC) 214圍封之一半導體晶片210。半導體晶片210耦合至由其側上之一囊封劑214圍封之一重佈層(RDL) 212。囊封劑214包覆RDL 212之側且圍封RDL 212之一下側直至囊封劑214與一互連結構220-7相遇。囊封劑214在RDL 212之一下側上之互連結構220-6及220-7之間。以此方式，囊封劑214保護RDL 212之側及下側且在結構上支撐互連結構220-6、220-7且將其等保持在適當位置。
圖3A至圖3H係根據本發明之數項實施例之形成一半導體裝置之一方法之一實例。圖3A係形成半導體裝置之方法之一初始步驟之一實例，其可包含隨後在方法中使一半導體晶粒210耦合至一重佈層。圖3B係一隨後步驟之一實例，其可包含在一載體基板326上形成一重佈層312。載體基板326可包含一玻璃載體、一矽載體及其他材料。
圖3C係形成半導體裝置之方法之一隨後步驟之一實例，其可包含在RDL 312上方形成一囊封劑(例如，一有機材料層、一EMC層) 314，使得囊封劑314圍封RDL 312之一第一側(繪示為RDL 312之頂部)及RDL 312之側部315-1及315-2。如圖3C中繪示，RDL 312之邊緣可圍封於囊封劑314內。藉由將RDL 312之邊緣圍封於囊封劑314內，RDL 312可受到保護以防界面脫層、引起破裂之機械應力及水分影響。在一組裝程序期間及/或使用期間，在邊緣315-1、315-2處不具有囊封劑314之情況下，界面脫層、引起破裂之機械應力及/或水分影響可沿著RDL 312之邊緣發生。
圖3D係形成半導體裝置之方法之一隨後步驟之一實例，其可包含自RDL 312之一側移除囊封劑314之部分。可藉由用一雷射選擇性蝕刻而執行部分之移除。部分之移除可沿著RDL 312產生可用於插入額外半導體組件(例如，互連結構)之位置。如繪示，RDL 312附接至一載體基板326。圖3E係形成半導體裝置之方法之一隨後步驟之一實例，其可包含移除一載體基板(諸如圖3D中之載體基板326)。圖3E繪示旋轉180度之RDL 312及囊封劑314，使得囊封劑314之移除部分面向下，如繪示。
圖3F係形成半導體裝置之方法之一隨後步驟之一實例，其可包含將一半導體晶粒310 (諸如圖3A中描述之半導體晶粒310)耦合至一RDL 312。半導體晶粒310可在RDL 312之與囊封劑314之移除部分相對之一側上耦合至RDL 312。
如圖3F中(且亦在圖3G至圖3H中)繪示，RDL 312延伸超出半導體晶粒310之側，此容許一扇出晶圓級封裝(FOWLP)程序中之「扇出」特性，如此實例中使用。FOWLP容許較大數目個外部輸入/輸出(I/O)及系統級封裝方法，此係因為外部I/O具有RDL 312之一較大表面以附接至超出半導體晶粒310之邊緣。可使用先晶片(chip-first)或後晶片(chip-last)方法執行形成半導體裝置之程序。一先晶片方法包含將一晶粒附接至一臨時或永久材料結構，隨後製成將自晶粒延伸至一BGA (球柵陣列)介面之一RDL。BGA係用於積體電路之一種類型之表面安裝封裝(一晶片載體)。BGA封裝可用於永久安裝裝置(諸如微處理器)。一BGA可提供可置於一雙行或扁平封裝上之更多互連接針。以此方式，良率損失與在安裝晶粒之後產生RDL相關聯，從而使晶粒經受潛在損失。
在一後晶片程序中，首先產生RDL且接著安裝晶粒。在此後晶片程序中，可電測試或視覺檢測RDL結構之良率損失，藉此避免將一良好晶粒放置於損壞位置上。對於低I/O晶粒(其中RDL最小且良率為高)，一先晶片程序可為較佳的。對於一高值晶粒(大I/O) (如在一扇出佈局中，如繪示)，一後晶片程序可為較佳的。
圖3G係形成半導體裝置之方法之一隨後步驟之一實例，其可包含形成圍封半導體晶粒310且與先前形成之囊封劑314-1連接之一囊封劑(例如，一EMC層) 314-2。囊封劑314-2可為在囊封劑314-1之一第一部分之後形成的囊封劑之一第二部分。
圖3H係形成半導體裝置之方法之一隨後步驟之一實例，其可包含將數個互連結構320-1、320-2、320-3、320-4、320-5、320-6、320-7 (本文中稱為互連結構320)在移除囊封劑314-1之部分之位置處附接至RDL 312。以此方式，互連結構320可附接至RDL 312及囊封劑314-1之部分，使得互連結構320藉由囊封劑314-1保持在適當位置以導致一較強銲料接頭。互連結構320可具有較強銲料接頭而無需將底填充材料添加至互連結構320及RDL 312之下側。
圖4A至圖4H係根據本發明之數項實施例之形成一半導體裝置之一方法之一實例。圖4A係形成半導體裝置之方法之一初始步驟之一實例，其可包含隨後在方法中使一半導體晶粒410耦合至一重佈層。圖4B係形成半導體裝置之方法之一隨後步驟之一實例，其可包含在一載體基板426上形成一重佈層412。載體基板426可包含一玻璃載體、一矽載體及其他材料。圖4C係形成半導體裝置之方法之一隨後步驟之一實例，其可包含將數個互連結構(例如，焊球) 420-1、420-2、420-3、420-4、420-5、420-6、420-7 (本文中稱為互連結構420)附接至RDL 412。
圖4D係形成半導體裝置之方法之一隨後步驟之一實例，其可包含使用注射模製在互連結構420之各者之間及RDL 412之端部415-1、415-2處形成一囊封劑(例如，一EMC層) 414。
圖4E係形成半導體裝置之方法之一隨後步驟之一實例，其替代圖4D中描述之隨後步驟。替代步驟可包含使用壓縮模製(繪示為壓縮箭頭430) (相對於如圖4D中描述之注射模製)在互連結構420之各者之間及RDL 412之端部415-1、415-2處形成EMC層414。圖4D及圖4E中繪示之步驟之任一者可用於形成囊封劑414，如繪示。如圖4D及圖4E中繪示，RDL 412之邊緣可圍封於EMC層414內。藉由將RDL 412之邊緣圍封於囊封劑層414內，RDL 412可受到保護以防界面脫層、引起破裂之機械應力及水分影響。在一組裝程序期間及/或使用期間，在邊緣415-1、415-2處不具有囊封劑414之情況下(或當RDL 412邊緣不具有囊封劑時)，界面脫層、引起破裂之機械應力及/或水分影響可沿著RDL 412之邊緣發生。
圖4F係形成半導體裝置之方法之一隨後步驟之一實例，其可包含移除一載體基板(諸如圖4A至圖4E中繪示之載體基板426)。圖4G係形成半導體裝置之方法之一隨後步驟之一實例。圖4G繪示旋轉180度之RDL 412、囊封劑414及互連結構420。圖4G中繪示之步驟可包含將一半導體晶粒410 (諸如圖4A中描述之半導體晶粒410)耦合至RDL 412。半導體晶粒410可在RDL 412之與互連結構420相對之一側上耦合至RDL 412。如圖4G中繪示，RDL 412延伸超出半導體晶片410之側，此容許一扇出晶圓級封裝(FOWLP)程序中之「扇出」特性，如此實例中使用。FOWLP容許較大數目個外部輸入/輸出(I/O)及系統級封裝方法，如上文進一步描述。
圖4H係形成半導體裝置之方法之一隨後步驟之一實例，其可包含形成圍封半導體晶粒410且與先前形成之囊封劑414-1連接之一囊封劑414-2。囊封劑414-2可為在囊封劑414-1之一第一部分之後形成的囊封劑之一第二部分。
儘管在本文中已繪示及描述特定實施例，然一般技術者將瞭解，經計算以達成相同結果之一配置可替代所展示之特定實施例。本發明意欲涵蓋本發明之各種實施例之調適或變化。
應理解，已以一闡釋性方式且非一限制性方式作出上文描述。熟習此項技術者在檢視上文描述之後將明白在本文中未具體描述之上述實施例之組合及其他實施例。本發明之各種實施例之範疇包含其中使用上文結構及方法之其他應用。因此，應參考隨附發明申請專利範圍連同涵括此等發明申請專利範圍之等效物之全部範圍判定本發明之各種實施例之範疇。
在前述實施方式中，出於簡化本發明之目的而將各種特徵共同分組於一單一實施例中。本發明之此方法不應解釋為反映本發明之所揭示實施例必須使用多於每一請求項中明確敘述之特徵之一意圖。
實情係，如以下發明申請專利範圍反映，本發明標的在於少於一單一所揭示實施例之所有特徵。因此，以下發明申請專利範圍特此併入[實施方式]中，其中每一請求項自身獨立地作為一單獨實施例。
101‧‧‧半導體裝置110‧‧‧記憶體晶片112‧‧‧重佈層(RDL)114‧‧‧囊封劑116-1‧‧‧第一側部116-2‧‧‧第二側部118‧‧‧佈線120‧‧‧互連結構120-1至120-5‧‧‧互連結構202‧‧‧半導體裝置210‧‧‧半導體晶粒/記憶體晶片/半導體晶片211‧‧‧部分212‧‧‧重佈層(RDL)214‧‧‧囊封劑220-1至220-7‧‧‧互連結構222‧‧‧印刷電路板(PCB)310‧‧‧半導體晶粒312‧‧‧重佈層(RDL)314‧‧‧囊封劑314-1‧‧‧囊封劑314-2‧‧‧囊封劑315-1‧‧‧側部/邊緣315-2‧‧‧側部/邊緣320-1至320-7‧‧‧互連結構326‧‧‧載體基板410‧‧‧半導體晶粒412‧‧‧重佈層(RDL)414‧‧‧囊封劑414-1‧‧‧囊封劑414-2‧‧‧囊封劑415-1‧‧‧端部/邊緣415-2‧‧‧端部/邊緣420-1至420-7‧‧‧互連結構426‧‧‧載體基板430‧‧‧壓縮箭頭
圖1A係根據本發明之數項實施例之一半導體裝置之一實例。
圖1B係根據本發明之數項實施例之一半導體裝置之一部分之一實例。
圖2A係根據本發明之數項實施例之一半導體裝置之一實例。
圖2B係根據本發明之數項實施例之一半導體裝置之一部分之一實例。
圖3A至圖3H係根據本發明之數項實施例之形成一半導體裝置之一方法之一實例。
圖4A至圖4H係根據本發明之數項實施例之形成一半導體裝置之一方法之一實例。
101‧‧‧半導體裝置
110‧‧‧記憶體晶片
112‧‧‧重佈層(RDL)
114‧‧‧囊封劑
116-1‧‧‧第一側部
116-2‧‧‧第二側部
118‧‧‧佈線
120-1至120-5‧‧‧互連結構

Claims (18)

  1. 一種半導體裝置，其包括：一半導體晶粒包括複數個相對側邊；一重佈層(RDL)，其形成於該半導體晶粒之一第一表面上並耦合至一印刷電路板(PCB)，其中：該RDL包括一第一表面及一第二表面，該第一表面接觸該半導體晶粒，該第二表面相對於該第一表面及該半導體晶粒；該重佈層之複數個相對側邊完全延伸超出該半導體晶粒之該等相對側邊；及沒有半導體晶粒延伸超出該重佈層之該等相對側邊；複數個互連結構附接至相對於該半導體晶粒之該重佈層之一側邊並且對應該重佈層之該延伸以本質上附接超出該半導體晶粒之該等相對側邊；一囊封劑，其圍封：該半導體晶粒之一第二表面以及複數個側表面；及在該等互連結構之間及在該RDL之該第二表面上相對於該半導體晶粒的該RDL之複數個部分；及其中該等互連結構之至少一部分從該囊封劑曝露(exposed)。
  2. 如請求項1之半導體裝置，其中該囊封劑圍封該RDL未與該半導體晶粒接觸之一部分。
  3. 如請求項1之半導體裝置，其中該RDL延伸超出該半導體晶粒之一邊緣。
  4. 如請求項1至3中任一項之半導體裝置，其中互連結構附接至與該半導體晶粒相對的該RDL之一側。
  5. 如請求項4之半導體裝置，其中該囊封劑圍封在該等互連結構之間的該RDL之部分。
  6. 一種半導體裝置，其包括：一半導體晶粒包括複數個相對側邊；一重佈層(RDL)，其形成於該半導體晶粒之一第一表面上並耦合至一印刷電路板(PCB)，其中：該RDL包括一第一表面及一第二表面，該第一表面接觸該半導體晶粒，該第二表面相對於該第一表面及該半導體晶粒；及該RDL完全延伸超出該半導體晶粒之該等相對側邊；互連結構，其等形成於該RDL之一第二表面上並且沿著該RDL完全形成超出該半導體晶粒之該等相對側邊；及一囊封劑，其圍封：該半導體晶粒之一第二表面以及複數個側表面；及在該等互連結構之間及在該晶粒之該第二表面上相對於該半導體晶粒的該RDL之複數個部分；其中該等互連結構之至少一部分從該 囊封劑曝露。
  7. 如請求項6之半導體裝置，其中該RDL延伸超出該半導體晶粒之該等相對側邊之一者之一邊緣。
  8. 如請求項6之半導體裝置，其中該囊封劑圍封該RDL之側部。
  9. 如請求項6之半導體裝置，其中該等互連結構未由底填充材料覆蓋。
  10. 如請求項6至9中任一項之半導體裝置，其中圍封在該等互連結構之間的該RDL之該等部分之該囊封劑經構形以將該等互連結構保持在適當位置且抵靠該RDL。
  11. 一種形成一半導體裝置之方法，其包括：在一載體基板上形成一重佈層(RDL)；在該重佈層上形成一第一囊封劑；將數個部分移出該第一囊封劑；卸離該載體基板；將一半導體晶粒附接至該RDL之一第一表面以取代該卸離載體基板，其中：該RDL之一第二表面相對於該第一表面及該半導體晶粒；該半導體晶粒包括複數個相對側邊，並且該重佈層完全延伸超出該半導體晶粒之該等相對側邊；及 沒有半導體晶粒延伸超出該重佈層之複數個相對側邊；形成一第二囊封劑，該第二囊封劑圍封：該半導體晶粒；在該等互連結構之間及在該RDL之該第二表面上相對於該半導體晶粒之該重佈層之複數個部分；及面向該半導體晶粒但未與該半導體晶粒接觸的該RDL之部分；及將數個互連結構附接至相對該半導體晶粒之該重佈層之一側上的自該第一囊封劑移除之該數個部分之各者中，其中該等互連結構之至少一部分從該囊封劑曝露(exposed)，其中該等互連結構之至少一者完全附接超出該半導體晶粒之該等相對側邊。
  12. 如請求項11之方法，其中該RDL形成於其上之該載體基板包括玻璃及矽之至少一者。
  13. 如請求項11之方法，其包含經由雷射蝕刻移除該數個部分。
  14. 如請求項11至13中任一項之方法，其包含在不用底填充材料填充該數個互連結構之間的一區域及該RDL背向該半導體晶粒之一部分之情況下形成該半導體裝置。
  15. 一種用於形成一半導體裝置之方法，其包括：在一載體基板上形成一重佈層(RDL)；將數個互連結構附接至該RDL之與該載體基板相對之一表面上； 模製一第一囊封劑至該重佈層之該第一表面上並且位於每一該等互連結構之間，其中該等互連結構之至少一部分從該囊封劑曝露(exposed)；卸離該載體基板；將一半導體晶粒附接至該RDL之一第二表面以取代該卸離載體基板，其中：該第一表面相對於該RDL之該第二表面；該半導體晶粒包括複數個相對側邊；該重佈層延伸超出該半導體晶粒之該等相對側邊，並且該等互連結構之至少一者完全延伸超出該半導體晶粒之該等相對側邊；該RDL之邊緣之間只有囊封劑並且完全延伸超出該半導體晶粒之該等相對側邊與該囊封劑之一頂部，並且該半導體晶粒係位於該RDL與該囊封劑之該頂部之間；及該重佈層係位於該半導體晶粒與一印刷電路板(PCB)之間；及形成圍封該半導體晶粒之一第二囊封劑。
  16. 如請求項15之方法，其中將該第一囊封劑模製至該RDL層上包含使用一注射模製程序。
  17. 如請求項15之方法，其中將該第一囊封劑模製至該RDL層上包含使用一壓縮模製程序。
  18. 如請求項15之方法，其中該數個互連結構經附接超出該半導體晶粒之該等邊緣並且相關聯於該半導體晶粒之該等相對側邊。
TW107129211A 2017-08-22 2018-08-22 半導體裝置 TWI741207B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/683,059 US20190067145A1 (en) 2017-08-22 2017-08-22 Semiconductor device
US15/683,059 2017-08-22

Publications (2)

Publication Number Publication Date
TW201921532A TW201921532A (zh) 2019-06-01
TWI741207B true TWI741207B (zh) 2021-10-01

Family

ID=65437381

Family Applications (2)

Application Number Title Priority Date Filing Date
TW110115790A TW202133287A (zh) 2017-08-22 2018-08-22 半導體裝置
TW107129211A TWI741207B (zh) 2017-08-22 2018-08-22 半導體裝置

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW110115790A TW202133287A (zh) 2017-08-22 2018-08-22 半導體裝置

Country Status (4)

Country Link
US (2) US20190067145A1 (zh)
CN (1) CN111108597A (zh)
TW (2) TW202133287A (zh)
WO (1) WO2019040384A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111627867A (zh) * 2019-02-28 2020-09-04 富泰华工业（深圳）有限公司 芯片封装结构及其制作方法
KR20210007692A (ko) * 2019-07-12 2021-01-20 삼성전자주식회사 재배선 층을 포함하는 반도체 패키지 및 이를 제조하기 위한 방법
US11310911B2 (en) * 2020-07-14 2022-04-19 Qualcomm Incorporated Three-dimensional (3D) integrated circuit (IC) integration of an embedded chip and a preformed metal routing structure
TWI772140B (zh) * 2021-08-11 2022-07-21 汎銓科技股份有限公司 一種將故障分析用特殊大型封裝ic從印刷電路板卸下的方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160284620A1 (en) * 2015-03-26 2016-09-29 Dyi-chung Hu Low profile ic package
US20160315071A1 (en) * 2015-04-23 2016-10-27 Apple Inc. Three layer stack structure
CN106571344A (zh) * 2015-10-08 2017-04-19 胡迪群 封装胶体包裹的封装基材

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6011314A (en) 1999-02-01 2000-01-04 Hewlett-Packard Company Redistribution layer and under bump material structure for converting periphery conductive pads to an array of solder bumps
US6756671B2 (en) 2002-07-05 2004-06-29 Taiwan Semiconductor Manufacturing Co., Ltd Microelectronic device with a redistribution layer having a step shaped portion and method of making the same
US7646087B2 (en) 2005-04-18 2010-01-12 Mediatek Inc. Multiple-dies semiconductor device with redistributed layer pads
US7550857B1 (en) 2006-11-16 2009-06-23 Amkor Technology, Inc. Stacked redistribution layer (RDL) die assembly package
US7776649B1 (en) * 2009-05-01 2010-08-17 Powertech Technology Inc. Method for fabricating wafer level chip scale packages
US8937381B1 (en) * 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9385095B2 (en) * 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8816404B2 (en) * 2011-09-16 2014-08-26 Stats Chippac, Ltd. Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant
US8772058B2 (en) 2012-02-02 2014-07-08 Harris Corporation Method for making a redistributed wafer using transferrable redistribution layers
US9881894B2 (en) * 2012-03-08 2018-01-30 STATS ChipPAC Pte. Ltd. Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration
US8889484B2 (en) * 2012-10-02 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for a component package
US9553059B2 (en) 2013-12-20 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Backside redistribution layer (RDL) structure
US9735134B2 (en) 2014-03-12 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with through-vias having tapered ends
US9941207B2 (en) * 2014-10-24 2018-04-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of fabricating 3D package with short cycle time and high yield
US9659907B2 (en) * 2015-04-07 2017-05-23 Apple Inc. Double side mounting memory integration in thin low warpage fanout package
US9679801B2 (en) * 2015-06-03 2017-06-13 Apple Inc. Dual molded stack TSV package
US10872879B2 (en) * 2015-11-12 2020-12-22 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor package and manufacturing method thereof
US9570369B1 (en) * 2016-03-14 2017-02-14 Inotera Memories, Inc. Semiconductor package with sidewall-protected RDL interposer and fabrication method thereof
US10797025B2 (en) * 2016-05-17 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced INFO POP and method of forming thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160284620A1 (en) * 2015-03-26 2016-09-29 Dyi-chung Hu Low profile ic package
US20160315071A1 (en) * 2015-04-23 2016-10-27 Apple Inc. Three layer stack structure
CN106571344A (zh) * 2015-10-08 2017-04-19 胡迪群 封装胶体包裹的封装基材

Also Published As

Publication number Publication date
US11688658B2 (en) 2023-06-27
TW201921532A (zh) 2019-06-01
US20190067145A1 (en) 2019-02-28
CN111108597A (zh) 2020-05-05
TW202133287A (zh) 2021-09-01
US20210202337A1 (en) 2021-07-01
WO2019040384A1 (en) 2019-02-28

Similar Documents

Publication Publication Date Title
JP5566161B2 (ja) 回路パターンの浮き上がり現象を抑制するパッケージオンパッケージ及びその製造方法
KR101476883B1 (ko) 3차원 패키징을 위한 응력 보상층
TWI741207B (zh) 半導體裝置
US7772685B2 (en) Stacked semiconductor structure and fabrication method thereof
US9520304B2 (en) Semiconductor package and fabrication method thereof
US20140197530A1 (en) Semiconductor device with chip having low-k-layers
US9466546B2 (en) Semiconductor device and method of forming the same
US20110074037A1 (en) Semiconductor device
US9899307B2 (en) Fan-out chip package with dummy pattern and its fabricating method
US20160049345A1 (en) Low-stress dual underfill packaging
JP2001320013A (ja) 半導体装置およびその製造方法
TW201903992A (zh) 封裝結構及其製造方法
KR102391517B1 (ko) 반도체 디바이스 패키지 및 그 제조 방법
TWI503928B (zh) 半導體封裝件及其製法與中介板結構
TWI300261B (en) Chip package structur
TWI488270B (zh) 半導體封裝件及其製法
US20110316150A1 (en) Semiconductor package and method for manufacturing semiconductor package
JP2010263108A (ja) 半導体装置及びその製造方法
US9418874B2 (en) Method of fabricating semiconductor package
US8829687B2 (en) Semiconductor package and fabrication method thereof
KR20080061969A (ko) 반도체 패키지 및 이의 제조 방법
KR20080044518A (ko) 반도체 패키지 및 이의 제조 방법
KR20110137060A (ko) 반도체 패키지
KR100818090B1 (ko) 반도체 패키지
KR20100020771A (ko) 반도체 패키지의 제조 방법