TWI651824B - 半導體結構及方法 - Google Patents

半導體結構及方法 Download PDF

Info

Publication number
TWI651824B
TWI651824B TW106136027A TW106136027A TWI651824B TW I651824 B TWI651824 B TW I651824B TW 106136027 A TW106136027 A TW 106136027A TW 106136027 A TW106136027 A TW 106136027A TW I651824 B TWI651824 B TW I651824B
Authority
TW
Taiwan
Prior art keywords
substrate
carrier
semiconductor package
thermal expansion
expansion coefficient
Prior art date
Application number
TW106136027A
Other languages
English (en)
Other versions
TW201838118A (zh
Inventor
余振華
林詠淇
邱文智
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/674,388 external-priority patent/US11304290B2/en
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201838118A publication Critical patent/TW201838118A/zh
Application granted granted Critical
Publication of TWI651824B publication Critical patent/TWI651824B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/073—Apertured devices mounted on one or more rods passed through the apertures
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3494—Heating methods for reflowing of solder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/211—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/8321—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/19011—Structure including integrated passive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09136—Means for correcting warpage
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/163—Monitoring a manufacturing process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/166—Alignment or registration; Control of registration
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0067—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto an inorganic, non-metallic substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

本發明實施例提供一種方法包括將基板貼合到載體；使第一半導體封裝的第一表面上的外部連接件對準基板的背對所述載體的第一表面上的第一導電接墊；以及執行回焊製程，其中基板與載體之間的熱膨脹係數差異使得在回焊製程期間基板的第一表面為第一形狀，其中第一半導體封裝的各材料的熱膨脹係數差異使得在回焊製程期間第一半導體封裝的第一表面為第二形狀，且其中第一形狀實質上匹配所述第二形狀。所述方法進一步包括在回焊製程之後，從基板移除載體。

Description

半導體結構及方法
本發明的實施例是有關於一種製造方法，且特別是有關於一種半導體結構的製造方法。
半導體行業已因各種電子元件(例如電晶體、二極體、電阻器、電容器等)的整合密度持續提高而經歷快速增長。在很大程度上，整合密度的此種提高起因於最小特徵大小的反覆減小，此種反覆減小使得能夠將更多元件整合到給定區域中。隨著使電子裝置縮小這一需求的增長，出現了對用於半導體晶粒的更小型且更具創造性的封裝技術的需要。此類封裝系統的實例是堆疊封裝(Package-on-Package，PoP)技術。在堆疊封裝裝置中，將頂部半導體封裝堆疊在底部半導體封裝的頂部上，以提供高整合度及高元件密度。堆疊封裝技術通常使得能夠製作具有增強的功能及小的佔用面積(footprints)的半導體裝置。另一實例是基板上晶圓貼覆晶片(Chip-On-Wafer-On-Substrate，CoWoS)結構，其中將半導體晶片貼合到晶圓(例如中介層)以形成晶圓上晶片(Chip-On-Wafer，CoW)結構。接著，將所述晶圓上晶片結構貼 合到基板(例如印刷電路板)以形成基板上晶圓貼覆晶片結構。
本發明的實施例提供一種半導體結構的製造方法，包括以下步驟。將基板貼合到載體。使第一半導體封裝的第一表面上的外部連接件對準所述基板的背對所述載體的第一表面上的第一導電接墊。執行回焊製程，其中所述基板與所述載體之間的熱膨脹係數差異使得在所述回焊製程期間所述基板的所述第一表面為第一形狀，其中所述第一半導體封裝的各材料的熱膨脹係數差異使得在所述回焊製程期間所述第一半導體封裝的所述第一表面為第二形狀，且其中所述第一形狀實質上匹配所述第二形狀。在所述回焊製程之後，從所述基板移除所述載體。
本發明的實施例提供一種半導體結構的製造方法，包括以下步驟。對載體的熱膨脹係數進行微調。將基板的第一側貼合到所述載體，所述基板在所述基板的與所述第一側相對的第二側上具有導電接墊。將半導體封裝放置在所述基板的所述第二側上，其中位於所述半導體封裝的與所述基板面對的第一側上的外部連接件對準所述基板的各個所述導電接墊。加熱所述基板、所述載體及所述半導體封裝，其中所述半導體封裝的所述第一側在所述加熱期間具有第一彎曲形狀，其中所述載體的所述熱膨脹係數被相對於所述基板的熱膨脹係數微調成使得所述基板的所述第二側在所述加熱期間具有第二彎曲形狀，且其中所述第一彎曲形 狀實質上匹配所述第二彎曲形狀。
本發明的實施例提供一種半導體結構的製造方法，包括以下步驟。將基板的第一側貼合到載體。在結合溫度下將半導體封裝結合到所述基板的與所述第一側相對的第二側，其中所述半導體封裝的與所述基板面對的第一側在所述結合溫度下具有第一彎曲形狀，其中所述載體與所述基板之間的熱膨脹係數差異使得所述基板的所述第二側在所述結合溫度下為第二彎曲形狀，且其中所述第一彎曲形狀匹配所述第二彎曲形狀。
100‧‧‧半導體裝置
101、301‧‧‧載體
101A‧‧‧第一段/第一層
101B‧‧‧第二段/中間段/第二層
101B1、101B2、101B3‧‧‧層
101C‧‧‧第三段/第三層
101U‧‧‧載體101的上表面
103‧‧‧粘合層
105、213‧‧‧基板
105U‧‧‧基板105的上表面
107、318‧‧‧導電接墊
109、315‧‧‧鈍化層
109U‧‧‧鈍化層109的上表面
201‧‧‧半導體晶粒
203、313‧‧‧模製材料
205‧‧‧晶粒連接件
211‧‧‧中介層
213L‧‧‧基板213的下表面
215‧‧‧導電路徑
217、335‧‧‧外部連接件
250‧‧‧半導體封裝/晶圓上晶片封裝
280‧‧‧區域
305‧‧‧介電層
307‧‧‧晶粒貼合膜
309‧‧‧晶粒
311‧‧‧接觸接墊
316、317、323‧‧‧通孔
320‧‧‧重佈線結構
321‧‧‧導電線
325‧‧‧介電層
331‧‧‧凸塊下金屬結構
333‧‧‧電子元件
350‧‧‧整合型扇出封裝/半導體封裝
1000、1010、1020、1030、1040‧‧‧步驟
H‧‧‧高度
H1‧‧‧第一高度
H2‧‧‧第二高度
H3‧‧‧第三高度
W‧‧‧寬度
W1‧‧‧第一寬度
W2‧‧‧第二寬度
W3‧‧‧第三寬度
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1至圖4說明根據實施例的半導體裝置在各種製作階段的剖視圖。
圖5至圖8說明根據實施例的半導體裝置在各種製作階段的剖視圖。
圖9至圖13說明根據實施例的半導體裝置在各種製作階段的剖視圖。
圖14至圖17說明根據實施例的半導體裝置在各種製作階段的剖視圖。
圖18至圖21說明在各種實施例中載體的剖視圖。
圖22說明根據一些實施例製造半導體裝置的方法的流程圖。
以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，但自身並不表示所論述的各種實施例及/或配置之間的關係。
另外，為了易於描述圖中所示的一個元件或特徵與另一元件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「上覆」、及「上部」等空間相對用語。除了圖中所繪示的取向之外，所述空間相對用語亦旨在涵蓋裝置在使用或操作時的不同取向。設備可被另外取向(旋轉90度或在其他取向)，而本文所用的空間相對描述語可同樣相應地作出解釋。
本發明的實施例是在半導體製造的背景中且具體來說在形成三維(three-dimensional，3D)半導體結構的背景中進行論述。 在一些實施例中，所述三維半導體結構包括半導體封裝，所述半導體封裝貼合到基板的第一側上的導電接墊。所述基板的與第一側相對的第二側貼合到載體。在一些實施例中，在回焊製程(reflow process)期間，半導體封裝及基板因熱膨脹係數的不匹配(mismatch)而發生翹曲(warpage)。根據一些實施例，所述載體被設計成在基板中引發預定程度的翹曲，使得基板的第一側的第一翹曲實質上匹配半導體封裝的下表面的第二翹曲。本發明的實施例減少或防止冷焊(cold joints)的出現，且製程良率得以提高。
圖1至圖4說明半導體裝置100在各種製作階段的剖視圖。參照圖1，經由粘合層103將基板105貼合到載體101。基板105可由雙馬來醯亞胺三嗪(bismaleimide triazine，BT)樹脂、FR-4(一種由編織玻璃纖維布與環氧樹脂粘結劑構成的耐燃複合材料)、陶瓷、玻璃、塑膠、膠帶、膜或其他支撐材料製成。如圖1中所說明，在基板105的上表面上形成導電接墊107，例如鋁接墊或銅接墊。導電接墊107可電性連接到在基板105中形成的導電特徵(例如導電線或通孔(vias)，圖中未示出)。導電接墊107可用於將基板105電性耦合(例如通過焊接)到與基板105結合的其他電子裝置或元件(例如半導體晶粒、半導體封裝、電容器、電感器、電阻器、二極體等)。在一些實施例中，基板105可包括電子元件，例如電阻器、電容器、信號分配電路系統、這些的組合等。這些電子元件可為主動電子元件、被動電子元件或其組合。在其他實施例中，基板105中不含主動電子元件及被動電子元件。 所有此類組合完全旨在被包含在各實施例的範圍內。
在一些實施例中，基板105是印刷電路板(printed circuit board，PCB)，例如單層式印刷電路板或多層式印刷電路板。在所述印刷電路板中/上形成有包括金屬線及通孔的金屬內連線(圖中未示出)，且所述金屬內連線電性耦合到導電接墊107。舉例來說，在單層式印刷電路板中，可在印刷電路板的一側或兩側上形成金屬線，且可形成延伸穿過印刷電路板並將印刷電路板的兩側上的金屬線連接的通孔。雖然圖1中未示出，但在基板105的與載體101面對的下側上也可形成導電接墊107。在其中基板105是多層式印刷電路板的實施例中，在基板105的兩個相對側之間基板105的一個或多個層中進一步形成金屬線及通孔。如圖1中所說明，在基板105之上及導電接墊107之上形成鈍化層109(例如阻焊劑)。在鈍化層109中形成開口，以暴露出導電接墊107。在示例性的實施例中，基板105是尺寸為約30mm×約30mm或更大的印刷電路板，但也可存在其他尺寸。
載體101包含剛性材料，且具有上表面101U。上表面101U在例如室溫下可為平整的。基板105的下表面貼合到載體101的上表面101U。載體101是用於在後續處理(例如結合製程)中支撐基板105的臨時載體。此後，在一些實施例中，一旦結合製程完成，便從基板105移除載體101。
載體101可包含可為基板105提供結構性支撐的任何適合的材料。舉例來說，載體101可包含金屬(例如鋼)、玻璃、陶 瓷、矽(例如塊狀矽)、其組合、其多層體等。在一些實施例中，載體101的熱膨脹係數(coefficient of thermal expansion，CTE)被微調成使得在基板105貼合到載體101之後且在回焊製程期間，載體101的熱膨脹係數與基板105的熱膨脹係數之間的不匹配(例如差異)會對基板105引發預定(例如所設計(designed))程度的翹曲。將在下文中論述此種情形的細節。
在一些實施例中，僅將一個基板105貼合到載體101，且不將其他基板貼合到載體101。換句話說，一個載體101僅支撐一個基板105。在其他實施例中，將多於一個基板105貼合到載體101，因此，一個載體101支撐多個基板105。載體101在平面圖(圖中未示出)中的形狀可為任何適於容置一個或多個基板105的形狀。舉例來說，載體101可具有矩形形狀、正方形形狀、多邊形形狀或圓形形狀。在一些實施例中，載體101的大小(例如表面積)等於或大於貼合到載體101的一個或多個基板105的大小(例如表面積)。在其中一個載體101支撐一個基板105的實施例中，載體101的形狀與基板105的形狀相同或類似。舉例來說，在平面圖中，載體101及基板105兩者可具有相同矩形形狀或類似矩形形狀。應注意，由於載體101的表面積等於或大於基板105的表面積，因而基板105被載體101從下方完全支撐。舉例來說，在平面圖中，基板105設置在載體101的外周邊(exterior perimeters)內。
在圖1所示實例中，基板105通過粘合層103貼合到載 體101。在一些實施例中，粘合層103是聚合物粘合層。舉例來說，粘合層103可為光熱轉換(light-to-heat conversion，LTHC)膜，其在被暴露於輻射源(例如紫外(ultra-violet，UV)光或雷射)中時降低或失去其粘合度。因此，為在後續處理中從基板105移除載體101，可向粘合層103(例如光熱轉換膜)上照射紫外(UV)光或雷射，以輕易地從基板105移除載體101及粘合層103。還可使用其他適合的粘合層，例如晶粒貼合膜(die attaching film，DAF)，並且載體101的移除製程可包括機械剝離製程、研磨製程或蝕刻製程且可包括額外清潔製程。在一些實施例中，通過向粘合層103施加水來移除粘合層103。
接下來，如圖2中所說明，在基板105之上設置半導體封裝250。使半導體封裝250的外部連接件217對準基板105的各個導電接墊107，以為後續結合製程(例如回焊製程)作好準備。可在導電接墊107上施配焊料膏(solder paste)(圖中未示出)，以將半導體封裝250臨時貼合到基板105。
作為實例，半導體封裝250可為單晶片系統(System-On-Chip，SoC)、整合型扇出(Integrated-Fan-Out，InFO)封裝、晶圓上晶片(Chip-On-Wafer，CoW)封裝。在圖2所示實例中，半導體封裝250是晶圓上晶片(Chip-On-Wafer，CoW)封裝，其將在後續處理中與基板105結合以形成基板上晶圓貼覆晶片(CoWoS)封裝。
如圖2中所說明，半導體封裝250包括通過晶粒連接件 205與中介層(interposer)211的上側貼合的半導體晶粒(semiconductor die)(也被稱為晶粒)201。半導體封裝250進一步包括位於中介層211的上側之上及位於晶粒201周圍的模製材料203、以及與中介層211的下側電性耦合的外部連接件217。
在下文中闡述半導體封裝250的細節。半導體晶粒201可包括基板(圖中未個別地說明)、位於基板上的電子元件(圖中未個別地說明)、位於基板之上的金屬化層(圖中未個別地說明)、位於金屬化層之上的鈍化層(圖中未個別地說明)、位於鈍化層之上的導電接墊(圖中未個別地說明)、以及晶粒連接件205。在一實施例中，所述基板可包含經摻雜或未經摻雜的塊狀矽，或者包含絕緣層上矽(silicon-on-insulator，SOI)基板的主動層。一般來說，絕緣層上矽基板包含一層半導體材料，例如矽、鍺、矽鍺、絕緣層上矽、絕緣層上矽鍺(silicon germanium on insulator，SGOI)或其組合等。可使用的其他基板包括多層式基板、梯度式(gradient)基板或混合定向(hybrid orientation)基板。
所述電子元件包括各種各樣的主動裝置(例如電晶體)及被動裝置(例如電容器、電阻器、電感器)等，其可用於產生半導體晶粒201的設計的所需結構性要求及功能性要求。可使用任何適合的方法在晶粒201的基板內或晶粒201的基板上的其他地方形成所述電子元件。
所述金屬化層形成在基板及電子元件之上且被設計成連接各種電子元件以形成功能性電路系統。在一實施例中，所述金 屬化層由介電材料與導電材料的交替層形成，且可通過任何適合的製程(例如沉積、鑲嵌、雙重鑲嵌(dual damascene)等)來形成。在一實施例中，可存在四個通過至少一個層間介電層(interlayer dielectric layer，ILD)與基板分隔開的金屬化層，但金屬化層的確切數目取決於半導體晶粒201的設計。
所述鈍化層可形成在金屬化層之上，以為底層結構提供一定程度的保護。所述鈍化層可由一種或多種適合的介電材料(例如氧化矽、氮化矽、低介電常數(low-k)電介質(例如摻碳氧化物)、極低介電常數電介質(例如多孔摻碳二氧化矽)、這些的組合等)製成。可通過例如化學氣相沉積(chemical vapor deposition，CVD)等製程來形成所述鈍化層，但可利用任何適合的製程。
所述導電接墊可形成在所述金屬化層上且電接觸所述金屬化層。所述導電接墊可包含鋁，但作為另一選擇，可使用其他材料，例如銅。可通過使用例如濺鍍或鍍覆等沉積製程形成一層材料(圖中未示出)來形成導電接墊，且接著可通過適合的製程(例如光刻掩蔽及蝕刻)來移除所述層材料的某些部分以形成導電接墊。然而，可利用任何其他適合的製程來形成導電接墊。
晶粒連接件205可形成在導電接墊上，以在晶粒201的金屬化層與例如中介層211的導電路徑215之間提供用於接觸的導電區。在一實施例中，晶粒連接件205可為例如微凸塊等接觸凸塊，且可包含例如錫或其他適合的材料(例如銀或銅)等材料。在其中晶粒連接件205是錫焊料凸塊的實施例中，可通過首先通 過任何適合的方法(例如蒸鍍、電鍍、印刷、焊料轉移、植球)形成一層錫來形成晶粒連接件205。一旦已在結構上形成一層錫，便執行回焊以將所述材料成形為直徑是例如約10μm至100μm的所需凸塊形狀，但另一選擇為，可利用任何適合的大小。
然而，如所屬領域中的一般技術人員將認識到，儘管上文已將晶粒連接件205闡述為微凸塊，但這些微凸塊僅旨為說明而非旨在限制各實施例。實際上，作為另一選擇，可利用任何適合類型的外部觸點，例如受控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、銅柱、銅層、鎳層、無鉛(lead free，LF)層、無電鍍鎳鈀浸金(electroless nickel electroless palladium immersion gold，ENEPIG)層、Cu/無鉛層、Sn/Ag層、Sn/Pb、這些的組合等。可針對晶粒連接件205利用任何適合的外部連接件及任何適合的用於形成外部連接件的製程，且所有此類外部連接件完全旨在被包含在各實施例的範圍內。
參看中介層211，其包括基板213及導電路徑215(例如基板穿孔(through substrate vias，TSVs))。基板213可例如為經摻雜或未經摻雜的矽基板，或者可為絕緣層上矽(SOI)基板的主動層。然而，作為另一選擇，基板213可為玻璃基板、陶瓷基板、聚合物基板或者可提供適合保護及/或內連功能的任何其他基板。作為另一選擇，可針對基板213使用這些及任何其他適合的材料。
在一些實施例中，基板213可包括電子元件，例如電阻器、電容器、信號分配電路系統、這些的組合等。這些電子元件 可為主動元件、被動元件或其組合。在其他實施例中，基板213中不含主動電子元件及被動電子元件。所有此類組合完全旨在被包含在各實施例的範圍內。
另外，在一些實施例中，基板213是半導體晶圓。因此，當將一個或多個半導體晶粒(例如晶粒201)結合到基板213時，組合結構可形成晶圓上晶片(CoW)配置。
導電路徑215可為基板穿孔(TSVs)或任何其他適合的導電路徑。在其中導電路徑215是基板穿孔的實施例中，可通過以下操作來形成所述基板穿孔：首先形成局部穿過基板213的導電路徑，接著將基板213薄化以暴露出所述導電路徑。在其他實施例中，首先導電路徑215在被形成時，即延伸穿過基板213，且不需要將基板213薄化。可通過以下操作來形成導電路徑215：在基板213上形成適合的光阻(photoresist)或硬罩幕(hard mask)，將所述光阻或所述硬罩幕圖案化，並接著蝕刻基板213以產生開口(例如基板穿孔開口)。
一旦已形成導電路徑215的開口，便可以例如襯層(liner)(圖2中未單獨地說明)、障壁層(圖2中也未單獨地說明)及導電材料來填充所述開口。在一實施例中，所述襯層可為通過例如化學氣相沉積、氧化、物理氣相沉積、原子層沉積等製程形成的介電材料，例如氮化矽、氧化矽、介電聚合物、這些的組合等。
所述障壁層可包含例如氮化鈦等導電材料，但另一選擇為，可利用其他材料，例如氮化鉭、鈦、另一種電介質等。可使 用化學氣相沉積製程(例如離子增強化學氣相沉積(plasma-enhanced CVD，PECVD))來形成所述障壁層。然而，另一選擇為，可使用其他替代製程，例如濺鍍或金屬有機化學氣相沉積(metal organic chemical vapor deposition，MOCVD)、原子層沉積(atomic layer deposition，ALD)。所述障壁層可被形成為覆形(contour)於導電路徑215的開口的基礎形狀(underlying shape)。
所述導電材料可包括銅，但作為另一選擇，可利用其他適合的材料，例如鋁、鎢、合金、經摻雜多晶矽、其組合等。可通過沉積晶種層並接著向所述晶種層上電鍍銅、填充及過量填充(overfilling)導電路徑215的開口來形成所述導電材料。一旦已填充導電路徑215的開口，便可通過例如化學機械拋光(chemical mechanical polishing，CMP)等研磨製程來移除位於開口以外的過量障壁層及過量導電材料，但可使用任何適合的移除製程。
雖然圖2中未示出，但可在基板213的與晶粒201面對的上側上形成重佈線結構，以在導電路徑215、晶粒連接件205及半導體晶粒201之間提供電性內連接。所述重佈線結構包括設置在所述重佈線結構的一個或多個介電層中的重佈線層(redistribution layer，RDL)(例如導電線及/或通孔)。可使用用於在積體電路中形成內連接結構的常見方法來形成重佈線結構，此處不再對細節予以贅述。
一旦已形成重佈線結構，便可在基板213的上側上所述 重佈線層之上且與所述重佈線層電性連接地形成導電接墊(圖中未說明)。所述導電接墊可包含鋁，但作為另一選擇，可使用其他材料，例如銅。可通過使用沉積製程(例如濺鍍)形成一層材料(圖中未示出)來形成導電接墊，且接著可通過適合的製程(例如光刻掩蔽及蝕刻)來移除所述層材料的某些部分以形成導電接墊。然而，可利用任何其他適合的製程來形成導電接墊。
接下來，可在基板213的下側上形成外部連接件217，且外部連接件217可經由例如導電路徑215電性耦合到重佈線層。在後續處理(參見圖3A及圖3B)中例如通過回焊製程將外部連接件217實體地(physically)及電性地耦合到基板105，以形成基板上晶圓貼覆晶片(CoWoS)結構。外部連接件217可為銅柱、受控塌陷晶片連接(C4)凸塊、微凸塊、銅層、鎳層、無鉛(LF)層、無電鍍鎳鈀浸金(ENEPIG)層、Cu/無鉛層、Sn/Ag層、Sn/Pb、這些的組合等。可針對外部連接件217利用任何適合的外部連接件及任何適合的用於形成外部連接件的製程，且所有此類外部連接件完全旨在被包含在各實施例的範圍內。
一旦準備好，便可使用例如結合製程將半導體晶粒201結合到中介層211。舉例來說，可執行回焊製程，以將晶粒連接件205與基板213的上側上的各個接觸接墊(圖中未示出)結合。
一旦結合，便可在中介層211與半導體晶粒201之間的空間中注入或以其他方式形成底部填充材料(圖中未示出)。所述底部填充材料可例如包括在半導體晶粒201與基板213之間施配 且接著進行固化以硬化的液體環氧樹脂(liquid epoxy)。在其他實施例中，不使用底部填料(underfill)。而是，通過下文中所述的模製材料203來填充晶粒201與基板213之間的間隙。
接下來，在基板213的上側上形成模製材料203。在一些實施例中，模製材料203環繞半導體晶粒201。作為實例，模製材料203可包括環氧樹脂、有機聚合物、添加有或未添加有二氧化矽系(silica-based)填料或玻璃填料的聚合物或其他材料。在一些實施例中，模製材料203包括在被施加時是凝膠型液體的液體模製化合物(liquid molding compound，LMC)。在被施加時，模製材料203也可包括液體或固體。作為另一選擇，模製材料203可包括其他絕緣及/或密封材料。在一些實施例中，使用晶圓級模製製程來施加模製材料203。可使用例如壓縮模製、轉移模製、模製底部填充(molded underfill，MUF)或其他方法來模製出模製材料203。
接下來，在一些實施例中，使用固化製程將模製材料203固化。所述固化製程可包括使用退火製程(anneal process)或其他加熱製程將模製材料203加熱至預定溫度達預定時間段。所述固化製程還可包括紫外(UV)光曝光製程、紅外(infrared，IR)能量曝光製程、其組合或其與加熱製程的組合。作為另一選擇，可使用其他方法來將模製材料203固化。在一些實施例中，並不包括固化製程。接下來，可執行平坦化製程(planarization process)(例如化學機械拋光製程)，以將已固化模製材料203的上表面平 坦化。因此，形成半導體封裝250。
接下來，如圖3A中所說明，通過結合製程(例如回焊製程)將半導體封裝250實體地及電性地耦合到基板105。在結合製程中，使半導體封裝250的外部連接件217對準基板105的各個導電接墊107。在一些實施例中，使用例如焊料噴射印刷處理在導電接墊107上施配焊料膏。接下來，使半導體封裝250的外部連接件217接觸基板105的各個導電接墊107。接著，可執行回焊製程，以將半導體封裝250的外部連接件217與基板105的各個導電接墊107結合。可在約220℃或更高的溫度下執行所述回焊製程。
在回焊製程之後，可在導電接墊107與導電路徑215之間形成焊料區(圖中未個別地說明)。在其中外部連接件217包括銅柱的實施例中，可在所述銅柱與導電接墊107之間形成焊料區。在其中外部連接件217是焊料凸塊(例如受控塌陷晶片連接凸塊)的實施例中，外部連接件217的焊料在回焊製程期間熔化且在導電接墊107與導電路徑215之間形成焊料區的至少某些部分。
現在參照圖3B，其顯示圖3A中的區域280的放大視圖。如圖3B中所說明及下文所論述，基板105及半導體封裝250可在回焊溫度下翹曲。圖3B中出於說明目的擴大了翹曲的程度。因半導體封裝250的不同材料的熱膨脹係數不匹配，半導體封裝250可在回焊溫度(例如220℃或更高)下發生翹曲。舉例來說，模製材料203可具有比基板213的熱膨脹係數更高的熱膨脹係數。因 此，半導體封裝250的下表面213L發生翹曲(例如彎曲)而非為平整的。具體來說，基板213的下表面213L的中心高於下表面213L的兩個端部部分(例如遠離載體101延伸得更遠)。圖3B中基板213的彎曲下表面213L也被闡述為向上拱曲(bow)。圖3B所示實施例僅為實例。在其他實施例中，半導體封裝250的各材料之間的熱膨脹係數不匹配可使得基板213的下表面213L向下拱曲，例如基板213的下表面213L的中心低於下表面213L的端部部分(例如延伸得更靠近載體101)。
類似地，基板105的熱膨脹係數與載體101的熱膨脹係數之間的不匹配可使得基板105在回焊製程期間發生翹曲。因此，基板105的上表面105U可向上拱曲或向下拱曲，此視基板105的熱膨脹係數及載體101的熱膨脹係數而定。由於外部連接件217貼合到基板213的下表面213L，因而基板213的拱曲使外部連接件217的底表面(例如圖3B中外部連接件217的最下部分)位於彎曲平面上。如果基板105的上面形成有導電接墊107的上表面105U是平整的或具有與外部連接件217的彎曲平面不同的形狀及/或不同的曲率，則僅由於在回焊製程期間某些外部連接件217將不接觸各個導電接墊107就會非常難以將所有外部連接件217結合到各個導電接墊107。此可在外部連接件217與導電接墊107之間產生冷焊。冷焊導致半導體裝置的缺陷且降低半導體製造的良率。
如圖3B中所說明，在一些實施例中，本發明的實施例通 過以下方式來減少或防止冷焊的出現：在回焊製程期間對基板105引發預定程度的翹曲，以使基板105的上表面105U的形狀(例如向上拱曲或向下拱曲)及/或曲率(例如拱曲程度)實質上匹配半導體封裝250的下表面213L的形狀及/或曲率。由於鈍化層109具有實質上均勻的厚度，因而鈍化層109的上表面109U可具有與基板105的上表面105U相同的形狀及/或相同的曲率。類似地，各導電接墊107的上表面處於彎曲平面中，所述彎曲平面也可具有與上表面105U相同的形狀及/或相同的曲率。
仍參照圖3B，通過使基板105的翹曲匹配半導體封裝250的翹曲，在回焊製程期間(例如當半導體封裝250及基板105兩者均翹曲時)，半導體封裝250的所有外部連接件217均接觸各個導電接墊107，因此在半導體封裝250與基板105之間形成可靠的結合(例如電性連接)。
在一些實施例中，對基板105引發預定程度的翹曲包括分析半導體封裝250在回焊溫度下的翹曲、確定半導體封裝250的翹曲下表面213L在回焊溫度下的第一形狀、以及將載體101的熱膨脹係數調整成使載體101的熱膨脹係數與基板105的熱膨脹係數之間的不匹配會使得基板105在回焊製程期間發生翹曲，其中在回焊製程期間，基板105的翹曲上表面105U的第二形狀實質上匹配半導體封裝250的翹曲下表面213L的第一形狀。
在一些實施例中，分析半導體封裝250的翹曲包括通過電腦模擬來估計半導體封裝250的翹曲。舉例來說，可輸入半導 體封裝250的尺寸、結構、材料、以及回焊溫度作為電腦模擬程式的輸入參數，且接著通過所述電腦程式來產生關於半導體封裝250翹曲的細節(例如形狀、曲率)。
在一些實施例中，通過使用缺陷檢驗器(defect inspector)測量並分析莫列波紋(moiré patterns)來獲得半導體封裝250的翹曲。可使用此項技術中已知的方法來產生莫列波紋。舉例來說，可將在低膨脹石英玻璃上蝕刻的參考圖案投影到半導體封裝250的翹曲表面上。當從石英玻璃上方觀察時，在參考圖案與半導體封裝250的翹曲表面上的所投影的圖案之間進行幾何推理(geometric inference)便會產生莫列波紋。可使用缺陷檢驗器(例如來自科天公司(KLA-Tencor Corporation)的ICOS光學缺陷檢驗器)來測量翹曲的程度。
作為對半導體封裝250的翹曲進行分析的結果，獲得例如半導體封裝250的下表面213L的形狀及/或曲率等細節。如下文所論述，可使用這些細節作為對基板105引發的翹曲的目標。
在一些實施例中，對基板105引發預定程度的翹曲包括將載體101的熱膨脹係數相對於基板105的熱膨脹係數微調成使得在回焊溫度下，基板105與載體101之間的熱膨脹係數不匹配會得到與半導體封裝250的彎曲下表面213L實質上匹配的彎曲上表面105U。作為實例，考慮其中如圖3B中所說明下表面213L(例如因模製材料203的熱膨脹係數大於基板213的熱膨脹係數)向上拱曲的情況，載體101的熱膨脹係數被微調成小於基板105的 熱膨脹係數，使得基板105與載體101之間的熱膨脹係數不匹配會使基板105的上表面105U向上拱曲，因此匹配於彎曲下表面213L。作為另一實例，考慮其中下表面213L向下拱曲的情況。在此種情況中，載體101的熱膨脹係數被微調成大於基板105的熱膨脹係數，使得基板105與載體101之間的熱膨脹係數不匹配會使基板105的上表面105U也向下拱曲，因此匹配於彎曲下表面213L。
所屬領域中的技術人員將瞭解，“實質上匹配”在本文是指在誤差容限(error margin)之內的匹配。舉例來說，彎曲下表面213L與彎曲上表面105U之間的距離可具有相對於預期值(例如與外部連接件217的高度與鈍化層109的厚度之和相等的值)的偏差(例如大於或小於預期值)小於約20%的值。舉例來說，鈍化層109的厚度可為20μm，外部連接件217的高度可為80μm，且彎曲下表面213L與彎曲上表面105U之間的距離可具有相對於預期值100μm的偏差為例如約10%至約20%的值。作為在回焊製程期間使彎曲上表面105U與彎曲下表面213L匹配的結果，半導體封裝250的所有外部連接件217均接觸基板105的各個導電接墊107，且因此實體地及電性地耦合各個導電接墊107。
應注意，在其中在回焊製程期間半導體封裝250具有平整下表面213L的情況中，載體101的熱膨脹係數及結構被設計成使得基板105具有平整上表面105U以匹配平整下表面213L，在此種情況中，載體101用於確保使基板105發生很少或不發生翹 曲或者至少使基板105的上表面105U發生很少或不發生翹曲。因此，在本文的論述中，對基板105引發預定程度的翹曲以使基板105的翹曲實質上匹配基板213的翹曲包括在基板105與基板213均平整(例如翹曲為零)時出現的特殊情況，在此情況中，載體101的熱膨脹係數被微調成(例如等於基板105的熱膨脹係數)為基板105維持平整上表面105U以匹配平整下表面213L。另外，由於載體101及基板105可各自包含多於一種材料(例如多於一種熱膨脹係數)，因而載體101的熱膨脹係數及基板105的熱膨脹係數可分別是指載體101的整體(例如平均)熱膨脹係數及基板105的整體熱膨脹係數。
在一些實施例中，對載體101的熱膨脹係數進行微調包括將載體101的熱膨脹係數改變成使得在回焊製程期間，基板105的上表面105U實質上匹配半導體封裝250的下表面213L。可使用例如載體101的尺寸、基板105的尺寸、基板105的熱膨脹係數及結構等因數來確定載體101的熱膨脹係數。可使用電腦模式及模擬來針對載體101的給定熱膨脹係數估計關於基板105翹曲的細節。另外，可通過針對載體101使用不同材料(及不同熱膨脹係數)來進行實驗，且可通過缺陷檢驗器來測量及分析莫列波紋。在一些實施例中，使用電腦模式及模擬來確定載體101的潛在的熱膨脹係數值或載體101的熱膨脹係數值範圍。接著，使用有不同的熱膨脹係數值的不同材料來進行實驗，且執行莫列波紋測量及分析以對載體101的熱膨脹係數值進行確認及/或細調(fine tune)，直至使基板105的翹曲實現目標細節為止。
圖3A及圖3B示出載體101具有單層式結構。載體101可具有多段式結構及/或多層式結構，如圖18至圖21中所說明。與由單一塊狀材料製成的載體相比，多段式結構及多層式結構(參見圖18至圖21)使得能夠在選擇用於構成載體101的結構及材料時提高靈活性。由於在載體101的設計中可對更多參數進行微調，實現了設計靈活性的提高，此使得能夠在對載體101進行設計時具有更多自由度以滿足在回焊溫度下對基板105所引發的翹曲的目標細節。舉例來說，可通過使用多段式及/或多層式結構來實現以複雜形狀(例如非對稱的彎曲上表面105U)對基板105所引發的翹曲，而所述複雜形狀在先前可能無法實現。
參照圖18，其說明載體101的剖視圖。載體101具有多段式結構，其包括第一段101A、第二段101B及第三段101C。第一段101A具有第一寬度W1及第一熱膨脹係數值，第二段101B具有第二寬度W2及第二熱膨脹係數值，且第三段101C具有第三寬度W3及第三熱膨脹係數值。在所說明實施例中，第一段101A、第二段101B及第三段101C具有相同高度H。
可將載體101的不同段(例如101A、101B及101C)的寬度(例如W1、W2及W3)及熱膨脹係數值(例如第一熱膨脹係數值、第二熱膨脹係數值及第三熱膨脹係數值)彼此獨立地進行選擇，因此使得能夠在對載體101進行設計時具有大的靈活性。在一些實施例中，寬度W1、W2及W3具有不同值。在一些實施 例中，第一熱膨脹係數值、第二熱膨脹係數值及第三熱膨脹係數值具有不同值。在另一實施例中，第一段101A與第三段101C具有相同寬度及相同熱膨脹係數值，且第二段101B具有與第一段101A(及第三段101C)不同的寬度及不同的熱膨脹係數值。
圖19說明在一些實施例中載體101的剖視圖。載體101具有多層式結構，其包括第一層101A、第二層101B及第三層101C。第一層101A具有第一高度H1及第一熱膨脹係數值，第二層101B具有第二高度H2及第二熱膨脹係數值，且第三層101C具有第三高度H3及第三熱膨脹係數值。在所說明的實施例中，第一層101A、第二層101B及第三層101C具有相同寬度W。
仍參照圖19，可將載體101的不同層(例如101A、101B及101C)的高度(例如H1、H2及H3)以及熱膨脹係數值(例如第一熱膨脹係數值、第二熱膨脹係數值及第三熱膨脹係數值)彼此獨立地進行選擇，因此使得能夠在對載體101進行設計時具有大的靈活性。在一些實施例中，高度H1、H2及H3具有不同值。在一些實施例中，第一熱膨脹係數值、第二熱膨脹係數值及第三熱膨脹係數值具有不同值。在另一實施例中，第一層101A的第一熱膨脹係數值大於第二層101B的第二熱膨脹係數值，且第二層101B的第二熱膨脹係數值大於第三層101C的第三熱膨脹係數值。
可將圖18中的多段式結構與圖19中的多層式結構組合來構成載體101，如圖20及圖21中所說明。參照圖20，載體101類似於圖18中的載體101，只不過中間段101B具有與圖19所說 明多層式結構類似的多層式結構。在圖20所說明的實例中，層101B1、101B2及101B3分別具有高度H1、H2及H3且具有共同寬度W2。在一些實施例中，高度H1、H2及H3之和等於其他段101A及101C的高度H。可將載體101的不同段/層的尺寸(例如高度、寬度)及熱膨脹係數值彼此獨立地進行調整，以實現基板105在回焊溫度下的翹曲的目標細節。
圖21說明載體101的又一實施例。圖21中的載體101類似於圖20中的載體101，但其中多層式段(由101C表示)的位置是在載體101的右側處。其他細節可類似於圖20所示細節，因此不再予以贅述。
圖18至圖21僅為非限制性實例。可作出其他修改及變化，且其完全旨在被包含在本發明的實施例的範圍內。舉例來說，多段式結構中，段的數目可為多於或少於三個。類似地，多層式結構中，層的數目可為多於或少於三個。另外，在其中將多段式結構與多層式結構組合的實施例中，載體101的多於一個段可具有多層式結構，且具有多層式結構的段的位置可為載體101的任何適合的段。
本發明的實施例的優點包括裝置故障率(failure)得以降低及製造良率得以提高。通過在回焊溫度下使基板105的上表面105U的翹曲匹配半導體封裝250的下表面213L的翹曲，半導體封裝250的外部連接件217均接觸基板105的上表面105U上的各個導電接墊107，因此防止或減少冷焊的出現。在其中在回焊製程 期間使用夾具來夾持半導體封裝250的左側及右側以減少半導體封裝250的翹曲的先前方法中，半導體封裝250的被夾持部分經受高應力且可能在回焊製程期間破裂，並且半導體封裝250的未被夾持的中間部分仍可能出現翹曲且具有冷焊問題。相比之下，本發明的實施例並不夾持半導體封裝250，因此避免了與夾持相關聯的問題。此外，載體101完全支撐基板105的下表面，因此能夠使基板105的應力跨越大的區域(例如基板105的下表面)分佈且防止或減少對基板105的損壞。載體101的多層式結構及多段式結構使得能夠在為載體101選擇結構及材料時具有大的靈活性。可實現使基板105的翹曲具有複雜形狀，而這是使用現有載體設計不可能實現的。
現在參照圖4，在結合製程之後，例如在半導體裝置100冷卻至室溫之後，移除載體101。可通過例如穿過載體101向粘合層103(參見圖3A)施加紫外(UV)光或雷射來移除載體101，載體101對於紫外光或雷射可為透明的。在一些實施例中，通過向粘合層103施加水來移除所述粘合層。還可使用其他適合的方法，例如機械剝除、蝕刻、研磨等。在載體101被移除之後，可通過額外清潔製程來移除粘合層103的殘留物(如果有)。因此，在一些實施例中，圖4所示半導體裝置100形成基板上晶圓貼覆晶片(CoWoS)封裝。
圖5至圖8說明在另一實施例中半導體裝置100在各種製作階段的剖視圖。圖5至圖8中的類似編號表示與圖1至圖4 中類似的組件。圖5至圖8所示實施例類似於圖1至圖4中所說明的實施例，只不過基板105不使用粘合層103貼合到載體101。在示例性的實施例中，圖5至圖8中的載體101是靜電吸盤(electro-static chuck)。通過對靜電吸盤供應電壓，基板105通過相反電荷的吸引力而貼合到所述靜電吸盤。通過使電場停止(例如通過停止對靜電吸盤供應電壓)，可輕易地從載體101移除基板105。由於不存在要移除的粘合層，因而製程步驟的數目及處理時間得以減少。
在圖5中，通過對載體101(靜電吸盤)供應電壓將基板105貼合到載體101。在圖6中，在基板105之上設置半導體封裝250，其中外部連接件217對準基板105的上表面上的各個導電接墊107。可在導電接墊107之上形成焊料膏(圖中未示出)。在圖7中，在結合製程(例如回焊製程)中，將半導體封裝250的外部連接件217實體地及電性地結合到各個導電接墊107。在一些實施例中，載體101被設計成在回焊溫度下對基板105引發預定程度的翹曲，使得在回焊製程期間外部連接件217接觸各個導電接墊107，因此避免或減少冷焊的出現。載體101的細節可類似於上文參照圖1至圖4及圖18至圖21所述的細節，因此不再予以贅述。在圖8中，在結合製程之後，通過停止對載體101供應電壓而從基板105移除載體101。
圖9至圖13說明在另一實施例中半導體裝置100在各種製作階段的剖視圖。圖9至圖13所示實施例類似於圖1至圖4所 示實施例，只不過並非晶圓上晶片(CoW)封裝250，而是將整合型扇出(InFO)封裝350貼合到基板105的導電接墊107。圖9至圖13中的類似編號表示與圖1至圖4中類似的組件。
在圖9中，將基板105貼合到載體101。基板105及載體101的細節類似於上文參照圖1所述的細節，因此不再予以贅述。
圖10說明集成扇出型封裝350的剖視圖。如圖10中所說明，在載體301之上形成背側介電層305。背側介電層305可為背側鈍化層，且可包含通過物理氣相沉積、化學氣相沉積或其他適合的沉積方法而形成的聚合物、聚醯亞胺(polyimide)、氧化矽、氮化矽或其他適合的材料。載體301可含有基底材料，例如矽、聚合物、聚合物複合物、金屬箔(metal foil)、陶瓷、玻璃、玻璃環氧樹脂、氧化鈹(beryllium oxide)、膠帶或其他適於作為結構性支撐的材料。可在背側介電層305與載體301之間形成粘合層，例如光熱轉換(LTHC)膜。
經由例如晶粒貼合膜307將晶粒309貼合到背側介電層305。參看晶粒309，在晶粒309的上表面之上形成接觸接墊311，且在接觸接墊311之上形成鈍化層315。通孔316延伸穿過鈍化層315且電連接到接觸接墊311。導電接墊318形成在鈍化層315之上且電連接到通孔316。關於晶粒309的形成細節可類似於圖2中晶粒201的形成細節，因此不再予以贅述。
通孔317形成在背側介電層305之上且與晶粒309橫向間隔開。通孔317可包含導電材料(例如銅、鎢)，且可通過以下 操作來形成：在背側介電層305之上形成晶種層、在晶種層之上形成經圖案化光阻(photoresist)、進行鍍覆以填充經圖案化光阻層的開口、以及移除所述光刻膠並移除晶種層的位於通孔317的邊界以外的部分。通孔317可在晶粒309被貼合到介電層305之前或之後形成。
接下來，在背側介電層305之上形成模製材料313。模製材料313環繞晶粒309及通孔317。模製材料313可為模製化合物、環氧樹脂等，且可通過壓縮模製、轉移模製等來施加。在固化之後，模製材料313可經歷研磨製程(例如化學機械平坦化(chemical mechanical planarization，CMP)製程)，以暴露出晶粒309的通孔317的上表面及導電接墊318的上表面。
接下來，在模製材料313及晶粒309之上形成重佈線結構320。重佈線結構320可包括在一個或多個介電層325中形成的一個或多個重佈線層(例如導電線321、通孔323)。穿孔317電耦合到重佈線結構320的重佈線層。重佈線結構320的重佈線層也電耦合到晶粒309。重佈線結構320的重佈線層可由金屬(例如鋁、銅、鎢、鈦或其組合)形成，且可通過物理氣相沉積(PVD)、化學氣相沉積(CVD)、鍍覆或其他適合的沉積方法來形成。重佈線結構320的一個或多個介電層325可包含氧化矽、氮化矽、低介電常數電介質(例如摻碳氧化物)、極低介電常數電介質(例如多孔摻碳二氧化矽)、這些的組合等，且可通過例如化學氣相沉積、物理氣相沉積或任何其他適合的沉積方法等製程來形成。
接下來，如圖10中所說明，在重佈線結構320的頂表面之上形成凸塊下金屬(under-bump metallurgy，UBM)結構331。可通過在重佈線結構320之上沉積導電材料(例如銅、金或鋁)並將所述導電材料圖案化來形成凸塊下金屬結構331。可將電子元件333(例如整合型被動裝置(integrated-passive device，IPD))耦合到凸塊下金屬結構331。可在凸塊下金屬結構331上形成外部連接件335，例如球柵陣列封裝(ball-grid-array，BGA)、導電柱(例如銅柱)或頂部上具有焊料區的導電柱。接下來，圖中未示出，將圖10中的整合型扇出封裝350上下翻轉，且將外部連接件335貼合到例如切割膠帶(dicing tape)等膠帶。接著，通過脫離製程從整合型扇出封裝350移除載體301。在一些實施例中，在載體101被移除之前將多個整合型扇出封裝(圖中未示出)一起形成在載體101上，因此，可在載體101被移除之後執行切割以產生多個個別的整合型扇出封裝350。
在圖11中，在基板105之上設置整合型扇出封裝350。使整合型扇出封裝350的外部連接件335對準基板105的各個導電接墊107。可使用例如焊料噴射印刷製程在基板105的導電接墊107之上形成焊料膏(圖中未示出)。
在圖12中，執行結合製程(例如回焊製程)，以將整合型扇出封裝350的外部連接件335實體地及電性地耦合到基板105的導電接墊107。在一些實施例中，載體101被設計成在回焊溫度下對基板105引發預定程度的翹曲，使得在回焊製程期間外部連 接件335接觸各個導電接墊107，因此避免或減少冷焊。在一些實施例中，載體101的熱膨脹係數被微調成使得由載體101與基板105之間的熱膨脹係數不匹配引起的基板105的第一翹曲(例如彎曲上表面)實質上匹配集成扇出型封裝350的第二翹曲(例如彎曲下表面)。載體101的細節可類似於上文參照圖1至圖4及圖18至圖21所述的細節，因此不再予以贅述。
在圖13中，使用與上文參照圖4所述的處理步驟類似的處理步驟來移除載體101。不再對細節予以贅述。
圖14至圖17說明在另一實施例中半導體裝置100在各種製作階段的剖視圖。圖14至圖17中的類似編號表示與圖9至圖13中類似的組件。圖14至圖17所示實施例類似於圖9至圖13所示實施例，只不過基板105不使用粘合層103貼合到載體101。在示例性的實施例中，載體101是靜電吸盤。通過對靜電吸盤供應電壓，基板105被貼合到所述靜電吸盤。通過使電場停止，可輕易地從載體101移除基板105。由於不存在要移除的粘合層，因而處理步驟的數目及處理時間得以減少。
在圖14中，通過對載體101(靜電吸盤)供應電壓將基板105貼合到載體101。在圖15中，在基板105之上設置半導體封裝350(例如整合型扇出封裝)，其中使外部連接件335對準基板105的上表面上的各個導電接墊107。可在導電接墊107之上形成焊料膏(圖中未示出)。在圖16中，在結合製程(例如回焊製程)期間，將半導體封裝350的外部連接件335實體地及電性地 結合到各個導電接墊107。在一些實施例中，載體101被設計成在回焊溫度下對基板105引發預定程度的翹曲，使得在回焊製程期間外部連接件335接觸各個導電接墊107，因此避免或減少冷焊。載體101的細節可類似於上文參照圖1至圖4及圖18至圖21所述的細節，因此不再予以贅述。在圖17中，在回焊製程之後，通過停止對載體101供應電壓而從基板105移除載體101。
本發明的實施例可實現許多優點。舉例來說，通過對載體101進行恰當設計，可在回焊製程期間對基板105引發預定翹曲，以匹配半導體裝置(例如圖3A中的250及圖12中的350)的翹曲。避免冷焊的出現，且提高了生產良率。本發明的實施例不需要使用夾具來夾持半導體裝置，因此避免與應力的不均勻分佈有關的對半導體封裝的損壞。另外，載體101的多層式結構及多段式結構使得能夠在對載體101進行設計時具有大的靈活性。可實現使基板105的翹曲具有複雜形狀，而這在先前是不可能實現的。
圖22說明根據一些實施例製作半導體結構的方法的流程圖。應理解，圖22所示實施例方法僅為許多可能實施例方法的實例。所屬領域中的一般技術人員將認識到許多變化、替代方案及修改。舉例來說，可添加、去除、替換、重新安排及重複圖22中所說明的各種步驟。
參照圖22，在步驟1010，將基板貼合到載體。在步驟1020，使第一半導體封裝的外部連接件對準所述基板的背對所述 載體的第一表面上的第一導電接墊。在步驟1030，執行回焊製程，其中基板與載體之間的第一熱膨脹係數(CTE)不匹配使得在回焊製程期間所述基板發生第一翹曲，其中第一半導體封裝的各材料之間的第二熱膨脹係數不匹配使得在回焊製程期間所述第一半導體封裝發生第二翹曲，且其中第一翹曲實質上匹配第二翹曲。在步驟1040，在回焊製程之後，從基板移除載體。
在一實施例中，一種半導體結構製造方法包括：將基板貼合到載體；使第一半導體封裝的第一表面上的外部連接件對準所述基板的背對所述載體的第一表面上的第一導電接墊；執行回焊製程，其中所述基板與所述載體之間的熱膨脹係數(CTE)差異使得在所述回焊製程期間所述基板的所述第一表面為第一形狀，其中所述第一半導體封裝的各材料的熱膨脹係數差異使得在所述回焊製程期間所述第一半導體封裝的所述第一表面為第二形狀，且其中所述第一形狀實質上匹配所述第二形狀；以及在所述回焊製程之後，從所述基板移除所述載體。在一實施例中，將所述基板貼合到所述載體包括使用粘合層將所述基板貼合到所述載體。在一實施例中，所述載體是靜電吸盤，其中將所述基板貼合到所述載體包括對所述靜電吸盤供應電壓。在一實施例中，所述基板是印刷電路板(PCB)。在一實施例中，所述第一形狀及所述第二形狀是彎曲形狀。在一實施例中，執行所述回焊製程會將所述第一半導體封裝實體地及電性地耦合到所述基板。在一實施例中，所述方法進一步包括：在執行所述回焊製程之前，將第二半導體 封裝的外部連接件對準所述基板的所述第一表面上的第二導電接墊，其中所述回焊製程將所述第一半導體封裝及所述第二半導體封裝實體地及電性地耦合到所述基板。在一實施例中，所述基板具有矩形形狀、正方形形狀、多邊形形狀或圓形形狀。
在一實施例中，一種半導體結構製造方法包括：對載體的熱膨脹係數(CTEs)進行微調；將基板的第一側貼合到所述載體，所述基板在所述基板的與所述第一側相對的第二側上具有導電接墊；將半導體封裝放置在所述基板的所述第二側上，其中位於所述半導體封裝的與所述基板面對的第一側上的外部連接件對準所述基板的各個所述導電接墊；以及加熱所述基板、所述載體及所述半導體封裝，其中所述半導體封裝的所述第一側在所述加熱期間具有第一彎曲形狀，其中所述載體的所述熱膨脹係數被相對於所述基板的熱膨脹係數微調成使得所述基板的所述第二側在所述加熱期間具有第二彎曲形狀，且其中所述第一彎曲形狀實質上匹配所述第二彎曲形狀。在一實施例中，所述方法進一步包括在加熱所述基板、所述載體及所述半導體封裝之後從所述基板移除所述載體。在一實施例中，在所述加熱期間，所述半導體封裝的所述外部連接件接觸所述基板的各個所述導電接墊。在一實施例中，所述方法進一步包括：分析所述半導體封裝在加熱溫度下的翹曲；以及確定所述半導體封裝的所述第一側在所述加熱溫度下的所述第一彎曲形狀。在一實施例中，所述基板是印刷電路板。在一實施例中，所述半導體封裝包括：半導體晶粒；模製材料， 位於所述半導體晶粒周圍；導電特徵，電耦合到所述半導體晶粒且延伸超過所述半導體晶粒的邊界；以及所述外部連接件，電耦合到所述導電特徵，其中所述導電特徵位於所述半導體晶粒與所述外部連接件之間。在一實施例中，所述導電特徵是位於所述半導體晶粒與所述外部連接件之間的重佈線結構的重佈線層(RDL)。在一實施例中，所述導電特徵是位於所述半導體晶粒與所述外部連接件之間的中介層的通孔。
在一實施例中，一種半導體結構製造方法包括：將基板的第一側貼合到載體；以及在結合溫度下將半導體封裝結合到所述基板的與所述第一側相對的第二側，其中所述半導體封裝的與所述基板面對的第一側在所述結合溫度下具有第一彎曲形狀，其中所述載體與所述基板之間的熱膨脹係數(CTE)差異使得所述基板的所述第二側在所述結合溫度下為第二彎曲形狀，且其中所述第一彎曲形狀匹配所述第二彎曲形狀。在一實施例中，結合所述半導體封裝包括將所述半導體封裝的外部連接件結合到設置在所述基板的所述第二側上的導電接墊，其中在所述結合期間所述半導體封裝的所述外部連接件接觸所述基板的各個所述導電接墊。在一實施例中，所述方法進一步包括分析所述半導體封裝在所述結合溫度下的翹曲。在一實施例中，所述分析包括測量及分析所述半導體封裝的莫列波紋。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本發明的各個態樣。熟習此項技術者應知，其可容易 地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替、及變更。

Claims (10)

  1. 一種半導體結構的製造方法，包括：將基板貼合到載體；使第一半導體封裝的第一表面上的外部連接件對準所述基板的背對所述載體的第一表面上的第一導電接墊；執行回焊製程，其中所述基板與所述載體之間的熱膨脹係數差異使得在所述回焊製程期間所述基板的所述第一表面為第一形狀，其中所述第一半導體封裝的各材料的熱膨脹係數差異使得在所述回焊製程期間所述第一半導體封裝的所述第一表面為第二形狀，且其中所述第一形狀實質上匹配所述第二形狀；以及在所述回焊製程之後，從所述基板移除所述載體。
  2. 如申請專利範圍第1項所述的方法，其中將所述基板貼合到所述載體包括使用粘合層將所述基板貼合到所述載體，或者對所述載體供應電壓，其中所述載體是靜電吸盤。
  3. 如申請專利範圍第1項所述的方法，其中執行所述回焊製程將所述第一半導體封裝實體地及電性地耦合到所述基板。
  4. 一種半導體結構的製造方法，包括：對載體的熱膨脹係數進行微調；將基板的第一側貼合到所述載體，所述基板在所述基板的與所述第一側相對的第二側上具有導電接墊；將半導體封裝放置在所述基板的所述第二側上，其中位於所述半導體封裝的與所述基板面對的第一側上的外部連接件對準所述基板的各個所述導電接墊；以及加熱所述基板、所述載體及所述半導體封裝，其中所述半導體封裝的所述第一側在所述加熱期間具有第一彎曲形狀，其中所述載體的所述熱膨脹係數被相對於所述基板的熱膨脹係數微調成使得所述基板的所述第二側在所述加熱期間具有第二彎曲形狀，且其中所述第一彎曲形狀實質上匹配所述第二彎曲形狀。
  5. 如申請專利範圍第4項所述的方法，其中在所述加熱期間，所述半導體封裝的所述外部連接件接觸所述基板的各個所述導電接墊。
  6. 如申請專利範圍第4項所述的方法，還包括：分析所述半導體封裝在加熱溫度下的翹曲；以及確定所述半導體封裝的所述第一側在所述加熱溫度下的所述第一彎曲形狀。
  7. 一種半導體結構的製造方法，包括：將基板的第一側貼合到載體；以及在結合溫度下將半導體封裝結合到所述基板的與所述第一側相對的第二側，其中所述半導體封裝的與所述基板面對的第一側在所述結合溫度下具有第一彎曲形狀，其中所述載體與所述基板之間的熱膨脹係數差異使得所述基板的所述第二側在所述結合溫度下為第二彎曲形狀，且其中所述第一彎曲形狀匹配所述第二彎曲形狀。
  8. 如申請專利範圍第7項所述的方法，其中結合所述半導體封裝包括將所述半導體封裝的外部連接件結合到設置在所述基板的所述第二側上的導電接墊，其中在所述結合期間所述半導體封裝的所述外部連接件接觸所述基板的各個所述導電接墊。
  9. 如申請專利範圍第7項所述的方法，還包括：分析所述半導體封裝在所述結合溫度下的翹曲。
  10. 如申請專利範圍第9項所述的方法，其中所述分析包括測量及分析所述半導體封裝的莫列波紋。
TW106136027A 2017-04-07 2017-10-20 半導體結構及方法 TWI651824B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762483198P 2017-04-07 2017-04-07
US62/483,198 2017-04-07
US15/674,388 US11304290B2 (en) 2017-04-07 2017-08-10 Semiconductor structures and methods
US15/674,388 2017-08-10

Publications (2)

Publication Number Publication Date
TW201838118A TW201838118A (zh) 2018-10-16
TWI651824B true TWI651824B (zh) 2019-02-21

Family

ID=63711435

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106136027A TWI651824B (zh) 2017-04-07 2017-10-20 半導體結構及方法

Country Status (3)

Country Link
KR (1) KR102051055B1 (zh)
CN (1) CN108695175B (zh)
TW (1) TWI651824B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115700916A (zh) * 2019-01-15 2023-02-07 泉州三安半导体科技有限公司 发光二极管封装器件及发光装置
US11195823B2 (en) * 2019-02-01 2021-12-07 Nanya Technology Corporation Semiconductor package and manufacturing method thereof
US11031353B2 (en) 2019-08-23 2021-06-08 Micron Technology, Inc. Warpage control in microelectronic packages, and related assemblies and methods
US11410968B2 (en) 2019-10-18 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming the same
US11569156B2 (en) 2019-10-27 2023-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device, electronic device including the same, and manufacturing method thereof
JP2022046249A (ja) * 2020-09-10 2022-03-23 キオクシア株式会社 半導体記憶装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120217287A1 (en) * 2011-02-28 2012-08-30 International Business Machines Corporation Flip chip assembly method employing post-contact differential heating
US20120292375A1 (en) * 2009-09-01 2012-11-22 International Business Machines Corporation Method of joining a chip on a substrate
TW201519404A (zh) * 2013-11-14 2015-05-16 Taiwan Semiconductor Mfg Co Ltd 三維積體電路結構及其製造方法
US20150243642A1 (en) * 2011-10-24 2015-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and Methods for Forming the Same
US20160307815A1 (en) * 2014-09-15 2016-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Packaging Having Warpage Control and Methods of Forming Same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6177728B1 (en) * 1998-04-28 2001-01-23 International Business Machines Corporation Integrated circuit chip device having balanced thermal expansion
CN1753160A (zh) * 2004-09-21 2006-03-29 中华映管股份有限公司 芯片－玻璃接合工艺、热压工艺及其装置
JPWO2007037055A1 (ja) * 2005-09-29 2009-04-02 日本電気株式会社 半導体パッケージ、基板、この半導体パッケージ又は基板を用いた電子機器、半導体パッケージの反り矯正方法
JP2010103270A (ja) * 2008-10-23 2010-05-06 Nec Corp 半導体装置および半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120292375A1 (en) * 2009-09-01 2012-11-22 International Business Machines Corporation Method of joining a chip on a substrate
US20120217287A1 (en) * 2011-02-28 2012-08-30 International Business Machines Corporation Flip chip assembly method employing post-contact differential heating
US20150243642A1 (en) * 2011-10-24 2015-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and Methods for Forming the Same
TW201519404A (zh) * 2013-11-14 2015-05-16 Taiwan Semiconductor Mfg Co Ltd 三維積體電路結構及其製造方法
US20160307815A1 (en) * 2014-09-15 2016-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Packaging Having Warpage Control and Methods of Forming Same

Also Published As

Publication number Publication date
TW201838118A (zh) 2018-10-16
CN108695175B (zh) 2020-06-26
CN108695175A (zh) 2018-10-23
KR20180113901A (ko) 2018-10-17
KR102051055B1 (ko) 2019-12-02

Similar Documents

Publication Publication Date Title
US11508695B2 (en) Redistribution layers in semiconductor packages and methods of forming same
TWI651824B (zh) 半導體結構及方法
US10461036B2 (en) Multi-stacked package-on-package structures
US11456257B2 (en) Semiconductor package with dual sides of metal routing
US10304801B2 (en) Redistribution layers in semiconductor packages and methods of forming same
US10062648B2 (en) Semiconductor package and method of forming the same
US20180374824A1 (en) Semiconductor Packages with Thermal-Electrical-Mechanical Chips and Methods of Forming the Same
US11062978B2 (en) Semiconductor package and method
US11304290B2 (en) Semiconductor structures and methods
KR102453507B1 (ko) 반도체 die 패키지 및 제조 방법
TW201924014A (zh) 半導體封裝及其形成方法
US11158619B2 (en) Redistribution layers in semiconductor packages and methods of forming same
US11121089B2 (en) Integrated circuit package and method
TWI770609B (zh) 半導體結構及其形成方法
TWI723793B (zh) 半導體元件及其形成方法
KR102611254B1 (ko) 반도체 다이 패키지 및 제조 방법
US20240063083A1 (en) Redistribution Structure with Warpage Tuning Layer
TW202249200A (zh) 半導體結構以及形成半導體結構的方法