CN108695175A - 半导体结构的制造方法 - Google Patents

半导体结构的制造方法 Download PDF

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Publication number
CN108695175A
CN108695175A CN201711157377.8A CN201711157377A CN108695175A CN 108695175 A CN108695175 A CN 108695175A CN 201711157377 A CN201711157377 A CN 201711157377A CN 108695175 A CN108695175 A CN 108695175A
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China
Prior art keywords
substrate
carrier
semiconductor packages
coefficient
thermal expansion
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CN201711157377.8A
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CN108695175B (zh
Inventor
余振华
林咏淇
邱文智
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US15/674,388 external-priority patent/US11304290B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN108695175A publication Critical patent/CN108695175A/zh
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  • Engineering & Computer Science (AREA)
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  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明实施例提供一种半导体结构的制造方法包括将衬底贴合到载体；使第一半导体封装的第一表面上的外部连接件对准衬底的背对所述载体的第一表面上的第一导电接垫；以及执行回流工艺，其中衬底与载体之间的热膨胀系数(CTE)差异使得在回流工艺期间衬底的第一表面为第一形状，其中第一半导体封装的各材料的热膨胀系数差异使得在回流工艺期间第一半导体封装的第一表面为第二形状，且其中第一形状实质上匹配所述第二形状。所述方法进一步包括在回流工艺之后，从衬底移除载体。

Description

半导体结构的制造方法
技术领域
本发明的实施例是有关于一种制造方法，且特别是有关于一种半导体结构的制造方法。
背景技术
半导体行业已因各种电子组件(例如晶体管、二极管、电阻器、电容器等)的集成密度持续提高而经历快速增长。在很大程度上，集成密度的此种提高起因于最小特征大小的反复减小，此种反复减小使得能够将更多组件集成到给定区域中。随着使电子装置缩小这一需求的增长，出现了对用于半导体管芯的更小型且更具创造性的封装技术的需要。此类封装系统的实例是叠层封装(Package-on-Package，PoP)技术。在叠层封装装置中，将顶部半导体封装堆叠在底部半导体封装的顶部上，以提供高集成度及高组件密度。叠层封装技术通常使得能够制作具有增强的功能及小的占用面积(footprints)的半导体装置。另一实例是衬底芯片上芯片(Chip-On-Wafer-On-Substrate，CoWoS)结构，其中将半导体芯片贴合到芯片(例如中介层)以形成芯片上芯片(Chip-On-Wafer，CoW)结构。接着，将所述芯片上芯片结构贴合到衬底(例如印刷电路板)以形成衬底上芯片上芯片结构。
发明内容
本发明的实施例提供一种半导体结构的制造方法，包括以下步骤。将衬底贴合到载体。使第一半导体封装的第一表面上的外部连接件对准所述衬底的背对所述载体的第一表面上的第一导电接垫。执行回流工艺，其中所述衬底与所述载体之间的热膨胀系数差异使得在所述回流工艺期间所述衬底的所述第一表面为第一形状，其中所述第一半导体封装的各材料的热膨胀系数差异使得在所述回流工艺期间所述第一半导体封装的所述第一表面为第二形状，且其中所述第一形状实质上匹配所述第二形状。在所述回流工艺之后，从所述衬底移除所述载体。
此外，本发明的其他实施例提供一种半导体结构的制造方法，包括以下步骤。对载体的热膨胀系数进行微调。将衬底的第一侧贴合到所述载体，所述衬底在所述衬底的与所述第一侧相对的第二侧上具有导电接垫。将半导体封装放置在所述衬底的所述第二侧上，其中位于所述半导体封装的与所述衬底面对的第一侧上的外部连接件对准所述衬底的各个所述导电接垫。加热所述衬底、所述载体及所述半导体封装，其中所述半导体封装的所述第一侧在所述加热期间具有第一弯曲形状，其中所述载体的所述热膨胀系数被相对于所述衬底的热膨胀系数微调成使得所述衬底的所述第二侧在所述加热期间具有第二弯曲形状，且其中所述第一弯曲形状实质上匹配所述第二弯曲形状。
另外，本发明的其他实施例提供一种半导体结构的制造方法，包括以下步骤。将衬底的第一侧贴合到载体。在结合温度下将半导体封装结合到所述衬底的与所述第一侧相对的第二侧，其中所述半导体封装的与所述衬底面对的第一侧在所述结合温度下具有第一弯曲形状，其中所述载体与所述衬底之间的热膨胀系数差异使得所述衬底的所述第二侧在所述结合温度下为第二弯曲形状，且其中所述第一弯曲形状匹配所述第二弯曲形状。
附图说明
结合附图阅读以下详细说明，会最佳地理解本发明的各方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为使论述清晰起见，可任意增大或减小各种特征的尺寸。
图1至图4说明根据实施例的半导体装置在各种制作阶段的剖视图。
图5至图8说明根据实施例的半导体装置在各种制作阶段的剖视图。
图9至图13说明根据实施例的半导体装置在各种制作阶段的剖视图。
图14至图17说明根据实施例的半导体装置在各种制作阶段的剖视图。
图18至图21说明在各种实施例中载体的剖视图。
图22说明根据一些实施例制造半导体装置的方法的流程图。
[符号的说明]
100：半导体装置
101、301：载体
101A：第一段/第一层
101B：第二段/中间段/第二层
101B1、101B2、101B3：层
101C：第三段/第三层
101U：载体101的上表面
103：粘合层
105、213：衬底
105U：衬底105的上表面
107、318：导电接垫
109、315：钝化层
109U：钝化层109的上表面
201：半导体管芯
203、313：模制材料
205：管芯连接件
211：中介层
213L：衬底213的下表面
215：导电路径
217、335：外部连接件
250：半导体封装/芯片上芯片封装
280：区域
305：介电层
307：管芯贴合膜
309：管芯
311：接触接垫
316、317、323：通孔
320：重布线结构
321：导电线
325：介电层
331：凸块下金属结构
333：电子组件
350：集成扇出型封装/半导体封装
1010、1020、1030、1040：步骤
H：高度
H1：第一高度
H2：第二高度
H3：第三高度
W：宽度
W1：第一宽度
W2：第二宽度
W3：第三宽度
具体实施方式
以下公开内容提供用于实作本发明的不同特征的许多不同的实施例或实例。下文阐述组件及排列的具体实例以简化本发明。当然，这些仅为实例且不旨在进行限制。例如，以下说明中将第一特征形成在第二特征之上或第二特征上可包括其中第一特征与第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有额外特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。
此外，为易于说明，本文中可能使用例如“在...下方(beneath)”、“在...下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所说明的一个组件或特征与另一(些)组件或特征的关系。所述空间相对性用语旨在除图中所绘示的定向外还囊括装置在使用或操作中的不同定向。设备可具有其他定向(旋转90度或其他定向)，且本文中所用的空间相对性描述语可同样相应地进行解释。
本发明的实施例是在半导体制造的背景中且具体来说在形成三维(three-dimensional，3D)半导体结构的背景中进行论述。在一些实施例中，所述三维半导体结构包括半导体封装，所述半导体封装贴合到衬底的第一侧上的导电接垫。所述衬底的与第一侧相对的第二侧贴合到载体。在一些实施例中，在回流工艺(reflow process)期间，半导体封装及衬底因热膨胀系数的失配(mismatch)而发生翘曲(warpage)。根据一些实施例，所述载体被设计成在衬底中引发预定程度的翘曲，使得衬底的第一侧的第一翘曲实质上匹配半导体封装的下表面的第二翘曲。本发明的实施例减少或防止冷焊(cold joints)的出现，且工艺良率得以提高。
图1至图4说明半导体装置100在各种制作阶段的剖视图。参照图1，经由粘合层103将衬底105贴合到载体101。衬底105可由双马来酰亚胺三嗪(bismaleimide triazine，BT)树脂、FR-4(一种由编织玻璃纤维布与环氧树脂粘结剂构成的耐燃复合材料)、陶瓷、玻璃、塑料、胶带、膜或其他支撑材料制成。如图1中所说明，在衬底105的上表面上形成导电接垫107，例如铝接垫或铜接垫。导电接垫107可电连接到在衬底105中形成的导电特征(例如导电线或通孔(vias)，图中未显示)。导电接垫107可用于将衬底105电耦合(例如通过焊接)到与衬底105结合的其他电子装置或组件(例如半导体管芯、半导体封装、电容器、电感器、电阻器、二极管等)。在一些实施例中，衬底105可包括电子组件，例如电阻器、电容器、信号分配电路系统、这些的组合等。这些电子组件可为有源电子组件、无源电子组件或其组合。在其他实施例中，衬底105中不含有源电子组件及无源电子组件。所有此类组合完全旨在被包含在各实施例的范围内。
在一些实施例中，衬底105是印刷电路板(printed circuit board，PCB)，例如单层式印刷电路板或多层式印刷电路板。在所述印刷电路板中/上形成有包括金属线及通孔的金属内连线(图中未示出)，且所述金属内连线电耦合到导电接垫107。举例来说，在单层式印刷电路板中，可在印刷电路板的一侧或两侧上形成金属线，且可形成延伸穿过印刷电路板并将印刷电路板的两侧上的金属线连接的通孔。虽然图1中未示出，但在衬底105的与载体101面对的下侧上也可形成导电接垫107。在其中衬底105是多层式印刷电路板的实施例中，在衬底105的两个相对侧之间衬底105的一个或多个层中进一步形成金属线及通孔。如图1中所说明，在衬底105之上及导电接垫107之上形成钝化层109(例如阻焊剂)。在钝化层109中形成开口，以暴露出导电接垫107。在示例性的实施例中，衬底105是尺寸为约30mm×约30mm或更大的印刷电路板，但也可存在其他尺寸。
载体101包含刚性材料，且具有上表面101U。上表面101U在例如室温下可为平整的。衬底105的下表面贴合到载体101的上表面101U。载体101是用于在后续处理(例如结合工艺)中支撑衬底105的临时载体。此后，在一些实施例中，一旦结合工艺完成，便从衬底105移除载体101。
载体101可包含可为衬底105提供结构性支撑的任何适合的材料。举例来说，载体101可包含金属(例如钢)、玻璃、陶瓷、硅(例如块状硅)、其组合、其多层体等。在一些实施例中，载体101的热膨胀系数(coefficient of thermal expansion，CTE)被微调成使得在衬底105贴合到载体101之后且在回流工艺期间，载体101的热膨胀系数与衬底105的热膨胀系数之间的失配(例如差异)会对衬底105引发预定(例如所设计(designed))程度的翘曲。将在下文中论述此种情形的细节。
在一些实施例中，仅将一个衬底105贴合到载体101，且不将其他衬底贴合到载体101。换句话说，一个载体101仅支撑一个衬底105。在其他实施例中，将多于一个衬底105贴合到载体101，因此，一个载体101支撑多个衬底105。载体101在平面图(图中未示出)中的形状可为任何适于容置一个或多个衬底105的形状。举例来说，载体101可具有矩形形状、正方形形状、多边形形状或圆形形状。在一些实施例中，载体101的大小(例如表面积)等于或大于贴合到载体101的一个或多个衬底105的大小(例如表面积)。在其中一个载体101支撑一个衬底105的实施例中，载体101的形状与衬底105的形状相同或类似。举例来说，在平面图中，载体101及衬底105两者可具有相同矩形形状或类似矩形形状。应注意，由于载体101的表面积等于或大于衬底105的表面积，因而衬底105被载体101从下方完全支撑。举例来说，在平面图中，衬底105设置在载体101的外周边(exterior perimeters)内。
在图1所示实例中，衬底105通过粘合层103贴合到载体101。在一些实施例中，粘合层103是聚合物粘合层。举例来说，粘合层103可为光热转换(light-to-heat conversion，LTHC)膜，其在被暴露于辐射源(例如紫外(ultra-violet，UV)光或激光)中时降低或失去其粘合度。因此，为在后续处理中从衬底105移除载体101，可向粘合层103(例如光热转换膜)上照射紫外(UV)光或激光，以轻易地从衬底105移除载体101及粘合层103。还可使用其他适合的粘合层，例如管芯贴合膜(die attaching film，DAF)，并且载体101的移除工艺可包括机械剥离工艺、研磨工艺或蚀刻工艺且可包括额外清洁工艺。在一些实施例中，通过向粘合层103施加水来移除粘合层103。
接下来，如图2中所说明，在衬底105之上设置半导体封装250。使半导体封装250的外部连接件217对准衬底105的各个导电接垫107，以为后续结合工艺(例如回流工艺)作好准备。可在导电接垫107上施配焊料膏(solder paste)(图中未示出)，以将半导体封装250临时贴合到衬底105。
作为实例，半导体封装250可为系统芯片(System-On-Chip，SoC)、集成扇出型(Integrated-Fan-Out，InFO)封装、芯片上芯片(CoW)封装。在图2所示实例中，半导体封装250是芯片上芯片(CoW)封装，其将在后续处理中与衬底105结合以形成衬底芯片上芯片(CoWoS)封装。
如图2中所说明，半导体封装250包括通过管芯连接件205与中介层(interposer)211的上侧贴合的半导体管芯(semiconductor die)(也被称为管芯)201。半导体封装250进一步包括位于中介层211的上侧之上及位于管芯201周围的模制材料203、以及与中介层211的下侧电耦合的外部连接件217。
在下文中阐述半导体封装250的细节。半导体管芯201可包括衬底(图中未个别地说明)、位于衬底上的电子组件(图中未个别地说明)、位于衬底之上的金属化层(图中未个别地说明)、位于金属化层之上的钝化层(图中未个别地说明)、位于钝化层之上的导电接垫(图中未个别地说明)、以及管芯连接件205。在一实施例中，所述衬底可包含经掺杂或未经掺杂的块状硅，或者包含绝缘层上硅(silicon-on-insulator，SOI)衬底的有源层。一般来说，绝缘层上硅衬底包含一层半导体材料，例如硅、锗、硅锗、绝缘层上硅、绝缘层上硅锗(silicon germanium on insulator，SGOI)或其组合等。可使用的其他衬底包括多层式衬底、梯度式(gradient)衬底或混合定向(hybrid orientation)衬底。
所述电子组件包括各种各样的有源装置(例如晶体管)及无源装置(例如电容器、电阻器、电感器)等，其可用于产生半导体管芯201的设计的所需结构性要求及功能性要求。可使用任何适合的方法在管芯201的衬底内或管芯201的衬底上的其他地方形成所述电子组件。
所述金属化层形成在衬底及电子组件之上且被设计成连接各种电子组件以形成功能性电路系统。在一实施例中，所述金属化层由介电材料与导电材料的交替层形成，且可通过任何适合的工艺(例如沉积、镶嵌、双重镶嵌(dual damascene)等)来形成。在一实施例中，可存在四个通过至少一个层间介电层(interlayer dielectric layer，ILD)与衬底分隔开的金属化层，但金属化层的确切数目取决于半导体管芯201的设计。
所述钝化层可形成在金属化层之上，以为底层结构提供一定程度的保护。所述钝化层可由一种或多种适合的介电材料(例如氧化硅、氮化硅、低介电常数(low-k)电介质(例如掺碳氧化物)、极低介电常数电介质(例如多孔掺碳二氧化硅)、这些的组合等)制成。可通过例如化学气相沉积(chemical vapor deposition，CVD)等工艺来形成所述钝化层，但可利用任何适合的工艺。
所述导电接垫可形成在所述金属化层上且电接触所述金属化层。所述导电接垫可包含铝，但作为另一选择，可使用其他材料，例如铜。可通过使用例如溅镀或镀覆等沉积工艺形成一层材料(图中未示出)来形成导电接垫，且接着可通过适合的工艺(例如光刻掩蔽及蚀刻)来移除所述层材料的某些部分以形成导电接垫。然而，可利用任何其他适合的工艺来形成导电接垫。
管芯连接件205可形成在导电接垫上，以在管芯201的金属化层与例如中介层211的导电路径215之间提供用于接触的导电区。在一实施例中，管芯连接件205可为例如微凸块等接触凸块，且可包含例如锡或其他适合的材料(例如银或铜)等材料。在其中管芯连接件205是锡焊料凸块的实施例中，可通过首先通过任何适合的方法(例如蒸镀、电镀、印刷、焊料转移、植球)形成一层锡来形成管芯连接件205。一旦已在结构上形成一层锡，便执行回流以将所述材料成形为直径是例如约10μm至100μm的所需凸块形状，但另一选择为，可利用任何适合的大小。
然而，如所属领域中的一般技术人员将认识到，尽管上文已将管芯连接件205阐述为微凸块，但这些微凸块仅旨在说明而非旨在限制各实施例。实际上，作为另一选择，可利用任何适合类型的外部触点，例如受控塌陷芯片连接(controlled collapse chipconnection，C4)凸块、铜柱、铜层、镍层、无铅(lead free，LF)层、无电镀镍钯浸金(electroless nickel electroless palladium immersion gold，ENEPIG)层、Cu/无铅层、Sn/Ag层、Sn/Pb、这些的组合等。可针对管芯连接件205利用任何适合的外部连接件及任何适合的用于形成外部连接件的工艺，且所有此类外部连接件完全旨在被包含在各实施例的范围内。
参看中介层211，其包括衬底213及导电路径215(例如衬底穿孔(throughsubstrate vias，TSVs))。衬底213可例如为经掺杂或未经掺杂的硅衬底，或者可为绝缘层上硅(SOI)衬底的有源层。然而，作为另一选择，衬底213可为玻璃衬底、陶瓷衬底、聚合物衬底或者可提供适合保护及/或内连功能的任何其他衬底。作为另一选择，可针对衬底213使用这些及任何其他适合的材料。
在一些实施例中，衬底213可包括电子组件，例如电阻器、电容器、信号分配电路系统、这些的组合等。这些电子组件可为有源组件、无源组件或其组合。在其他实施例中，衬底213中不含有源电子组件及无源电子组件。所有此类组合完全旨在被包含在各实施例的范围内。
另外，在一些实施例中，衬底213是半导体芯片。因此，当将一个或多个半导体管芯(例如管芯201)结合到衬底213时，组合结构可形成芯片上芯片(CoW)配置。
导电路径215可为衬底穿孔(TSVs)或任何其他适合的导电路径。在其中导电路径215是衬底穿孔的实施例中，可通过以下操作来形成所述衬底穿孔：首先形成局部穿过衬底213的导电路径，接着将衬底213薄化以暴露出所述导电路径。在其他实施例中，首先导电路径215在被形成时，即延伸穿过衬底213，且不需要将衬底213薄化。可通过以下操作来形成导电路径215：在衬底213上形成适合的光刻胶(photoresist)或硬掩模(hard mask)，将所述光刻胶或所述硬掩模图案化，并接着蚀刻衬底213以产生开口(例如衬底穿孔开口)。
一旦已形成导电路径215的开口，便可以例如衬里(liner)(图2中未单独地说明)、障壁层(图2中也未单独地说明)及导电材料来填充所述开口。在一实施例中，所述衬里可为通过例如化学气相沉积、氧化、物理气相沉积、原子层沉积等工艺形成的介电材料，例如氮化硅、氧化硅、介电聚合物、这些的组合等。
所述障壁层可包含例如氮化钛等导电材料，但另一选择为，可利用其他材料，例如氮化钽、钛、另一种电介质等。可使用化学气相沉积工艺(例如离子增强化学气相沉积(plasma-enhanced CVD，PECVD))来形成所述障壁层。然而，另一选择为，可使用其他替代工艺，例如溅镀或金属有机化学气相沉积(metal organic chemical vapor deposition，MOCVD)、原子层沉积(atomic layer deposition，ALD)。所述障壁层可被形成为覆形(contour)于导电路径215的开口的基础形状(underlying shape)。
所述导电材料可包括铜，但作为另一选择，可利用其他适合的材料，例如铝、钨、合金、经掺杂多晶硅、其组合等。可通过沉积晶种层并接着向所述晶种层上电镀铜、填充及过填充(overfilling)导电路径215的开口来形成所述导电材料。一旦已填充导电路径215的开口，便可通过例如化学机械抛光(chemical mechanical polishing，CMP)等研磨工艺来移除位于开口以外的过量障壁层及过量导电材料，但可使用任何适合的移除工艺。
虽然图2中未示出，但可在衬底213的与管芯201面对的上侧上形成重布线结构，以在导电路径215、管芯连接件205及半导体管芯201之间提供电内连。所述重布线结构包括设置在所述重布线结构的一个或多个介电层中的重布线层(redistribution layer，RDL)(例如导电线及/或通孔)。可使用用于在集成电路中形成内连结构的常见方法来形成重布线结构，此处不再对细节予以赘述。
一旦已形成重布线结构，便可在衬底213的上侧上所述重布线层之上且与所述重布线层电连接地形成导电接垫(图中未说明)。所述导电接垫可包含铝，但作为另一选择，可使用其他材料，例如铜。可通过使用沉积工艺(例如溅镀)形成一层材料(图中未示出)来形成导电接垫，且接着可通过适合的工艺(例如光刻掩蔽及蚀刻)来移除所述层材料的某些部分以形成导电接垫。然而，可利用任何其他适合的工艺来形成导电接垫。
接下来，可在衬底213的下侧上形成外部连接件217，且外部连接件217可经由例如导电路径215电耦合到重布线层。在后续处理(参见图3A及图3B)中例如通过回流工艺将外部连接件217实体地(physically)及电性地耦合到衬底105，以形成衬底芯片上芯片(CoWoS)结构。外部连接件217可为铜柱、受控塌陷芯片连接(C4)凸块、微凸块、铜层、镍层、无铅(LF)层、无电镀镍钯浸金(ENEPIG)层、Cu/无铅层、Sn/Ag层、Sn/Pb、这些的组合等。可针对外部连接件217利用任何适合的外部连接件及任何适合的用于形成外部连接件的工艺，且所有此类外部连接件完全旨在被包含在各实施例的范围内。
一旦准备好，便可使用例如结合工艺将半导体管芯201结合到中介层211。举例来说，可执行回流工艺，以将管芯连接件205与衬底213的上侧上的各个接触接垫(图中未示出)结合。
一旦结合，便可在中介层211与半导体管芯201之间的空间中注入或以其他方式形成底部填充材料(图中未示出)。所述底部填充材料可例如包括在半导体管芯201与衬底213之间施配且接着进行固化以硬化的液体环氧树脂(liquid epoxy)。在其他实施例中，不使用底部填料(underfill)。而是，通过下文中所述的模制材料203来填充管芯201与衬底213之间的间隙。
接下来，在衬底213的上侧上形成模制材料203。在一些实施例中，模制材料203环绕半导体管芯201。作为实例，模制材料203可包括环氧树脂、有机聚合物、添加有或未添加有二氧化硅系(silica-based)填料或玻璃填料的聚合物或其他材料。在一些实施例中，模制材料203包括在被施加时是凝胶型液体的液体模制化合物(liquid molding compound，LMC)。在被施加时，模制材料203也可包括液体或固体。作为另一选择，模制材料203可包括其他绝缘及/或密封材料。在一些实施例中，使用芯片级模制工艺来施加模制材料203。可使用例如压缩模制、转移模制、模制底部填充(molded underfill，MUF)或其他方法来模制出模制材料203。
接下来，在一些实施例中，使用固化工艺将模制材料203固化。所述固化工艺可包括使用退火工艺(anneal process)或其他加热工艺将模制材料203加热至预定温度达预定时间段。所述固化工艺还可包括紫外(UV)光曝光工艺、红外(infrared，IR)能量曝光工艺、其组合或其与加热工艺的组合。作为另一选择，可使用其他方法来将模制材料203固化。在一些实施例中，并不包括固化工艺。接下来，可执行平坦化工艺(planarization process)(例如化学机械抛光工艺)，以将已固化模制材料203的上表面平坦化。因此，形成半导体封装250。
接下来，如图3A中所说明，通过结合工艺(例如回流工艺)将半导体封装250实体地及电性地耦合到衬底105。在结合工艺中，使半导体封装250的外部连接件217对准衬底105的各个导电接垫107。在一些实施例中，使用例如焊料喷射印刷处理在导电接垫107上施配焊料膏。接下来，使半导体封装250的外部连接件217接触衬底105的各个导电接垫107。接着，可执行回流工艺，以将半导体封装250的外部连接件217与衬底105的各个导电接垫107结合。可在约220℃或更高的温度下执行所述回流工艺。
在回流工艺之后，可在导电接垫107与导电路径215之间形成焊料区(图中未个别地说明)。在其中外部连接件217包括铜柱的实施例中，可在所述铜柱与导电接垫107之间形成焊料区。在其中外部连接件217是焊料凸块(例如受控塌陷芯片连接凸块)的实施例中，外部连接件217的焊料在回流工艺期间熔化且在导电接垫107与导电路径215之间形成焊料区的至少某些部分。
现在参照图3B，其显示图3A中的区域280的放大视图。如图3B中所说明及下文所论述，衬底105及半导体封装250可在回流温度下翘曲。图3B中出于说明目的扩大了翘曲的程度。因半导体封装250的不同材料的热膨胀系数失配，半导体封装250可在回流温度(例如220℃或更高)下发生翘曲。举例来说，模制材料203可具有比衬底213的热膨胀系数更高的热膨胀系数。因此，半导体封装250的下表面213L发生翘曲(例如弯曲)而非为平整的。具体来说，衬底213的下表面213L的中心高于下表面213L的两个端部部分(例如远离载体101延伸得更远)。图3B中衬底213的弯曲下表面213L也被阐述为向上拱曲(bow)。图3B所示实施例仅为实例。在其他实施例中，半导体封装250的各材料之间的热膨胀系数失配可使得衬底213的下表面213L向下拱曲，例如衬底213的下表面213L的中心低于下表面213L的端部部分(例如延伸得更靠近载体101)。
类似地，衬底105的热膨胀系数与载体101的热膨胀系数之间的失配可使得衬底105在回流工艺期间发生翘曲。因此，衬底105的上表面105U可向上拱曲或向下拱曲，此视衬底105的热膨胀系数及载体101的热膨胀系数而定。由于外部连接件217贴合到衬底213的下表面213L，因而衬底213的拱曲使外部连接件217的底表面(例如图3B中外部连接件217的最下部分)位于弯曲平面上。如果衬底105的上面形成有导电接垫107的上表面105U是平整的或具有与外部连接件217的弯曲平面不同的形状及/或不同的曲率，则仅由于在回流工艺期间某些外部连接件217将不接触各个导电接垫107就会非常难以将所有外部连接件217结合到各个导电接垫107。此可在外部连接件217与导电接垫107之间产生冷焊。冷焊导致半导体装置的缺陷且降低半导体制造的良率。
如图3B中所说明，在一些实施例中，本发明的实施例通过以下方式来减少或防止冷焊的出现：在回流工艺期间对衬底105引发预定程度的翘曲，以使衬底105的上表面105U的形状(例如向上拱曲或向下拱曲)及/或曲率(例如拱曲程度)实质上匹配半导体封装250的下表面213L的形状及/或曲率。由于钝化层109具有实质上均匀的厚度，因而钝化层109的上表面109U可具有与衬底105的上表面105U相同的形状及/或相同的曲率。类似地，各导电接垫107的上表面处于弯曲平面中，所述弯曲平面也可具有与上表面105U相同的形状及/或相同的曲率。
仍参照图3B，通过使衬底105的翘曲匹配半导体封装250的翘曲，在回流工艺期间(例如当半导体封装250及衬底105两者均翘曲时)，半导体封装250的所有外部连接件217均接触各个导电接垫107，因此在半导体封装250与衬底105之间形成可靠的结合(例如电连接)。
在一些实施例中，对衬底105引发预定程度的翘曲包括分析半导体封装250在回流温度下的翘曲、确定半导体封装250的翘曲下表面213L在回流温度下的第一形状、以及将载体101的热膨胀系数调整成使载体101的热膨胀系数与衬底105的热膨胀系数之间的失配会使得衬底105在回流工艺期间发生翘曲，其中在回流工艺期间，衬底105的翘曲上表面105U的第二形状实质上匹配半导体封装250的翘曲下表面213L的第一形状。
在一些实施例中，分析半导体封装250的翘曲包括通过计算机模拟来估计半导体封装250的翘曲。举例来说，可输入半导体封装250的尺寸、结构、材料、以及回流温度作为计算机模拟程序的输入参数，且接着通过所述计算机程序来产生关于半导体封装250翘曲的细节(例如形状、曲率)。
在一些实施例中，通过使用缺陷检验器(defect inspector)测量并分析莫列波纹(moirépatterns)来获得半导体封装250的翘曲。可使用此项技术中已知的方法来产生莫列波纹。举例来说，可将在低膨胀石英玻璃上蚀刻的参考图案投影到半导体封装250的翘曲表面上。当从石英玻璃上方观察时，在参考图案与半导体封装250的翘曲表面上的所投影的图案之间进行几何推理(geometric inference)便会产生莫列波纹。可使用缺陷检验器(例如来自科天公司(KLA-Tencor Corporation)的ICOS光学缺陷检验器)来测量翘曲的程度。
作为对半导体封装250的翘曲进行分析的结果，获得例如半导体封装250的下表面213L的形状及/或曲率等细节。如下文所论述，可使用这些细节作为对衬底105引发的翘曲的目标。
在一些实施例中，对衬底105引发预定程度的翘曲包括将载体101的热膨胀系数相对于衬底105的热膨胀系数微调成使得在回流温度下，衬底105与载体101之间的热膨胀系数失配会得到与半导体封装250的弯曲下表面213L实质上匹配的弯曲上表面105U。作为实例，考虑其中如图3B中所说明下表面213L(例如因模制材料203的热膨胀系数大于衬底213的热膨胀系数)向上拱曲的情况，载体101的热膨胀系数被微调成小于衬底105的热膨胀系数，使得衬底105与载体101之间的热膨胀系数失配会使衬底105的上表面105U向上拱曲，因此匹配于弯曲下表面213L。作为另一实例，考虑其中下表面213L向下拱曲的情况。在此种情况中，载体101的热膨胀系数被微调成大于衬底105的热膨胀系数，使得衬底105与载体101之间的热膨胀系数失配会使衬底105的上表面105U也向下拱曲，因此匹配于弯曲下表面213L。
所属领域中的技术人员将了解，“实质上匹配”在本文是指在误差容限(errormargin)之内的匹配。举例来说，弯曲下表面213L与弯曲上表面105U之间的距离可具有相对于预期值(例如与外部连接件217的高度与钝化层109的厚度之和相等的值)的偏差(例如大于或小于预期值)小于约20％的值。举例来说，钝化层109的厚度可为20μm，外部连接件217的高度可为80μm，且弯曲下表面213L与弯曲上表面105U之间的距离可具有相对于预期值100μm的偏差为例如约10％至约20％的值。作为在回流工艺期间使弯曲上表面105U与弯曲下表面213L匹配的结果，半导体封装250的所有外部连接件217均接触衬底105的各个导电接垫107，且因此实体地及电性地耦合各个导电接垫107。
应注意，在其中在回流工艺期间半导体封装250具有平整下表面213L的情况中，载体101的热膨胀系数及结构被设计成使得衬底105具有平整上表面105U以匹配平整下表面213L，在此种情况中，载体101用于确保使衬底105发生很少或不发生翘曲或者至少使衬底105的上表面105U发生很少或不发生翘曲。因此，在本文的论述中，对衬底105引发预定程度的翘曲以使衬底105的翘曲实质上匹配衬底213的翘曲包括在衬底105与衬底213均平整(例如翘曲为零)时出现的特殊情况，在此情况中，载体101的热膨胀系数被微调成(例如等于衬底105的热膨胀系数)为衬底105维持平整表面105U以匹配平整下表面213L。另外，由于载体101及衬底105可各自包含多于一种材料(例如多于一种热膨胀系数)，因而载体101的热膨胀系数及衬底105的热膨胀系数可分别是指载体101的整体(例如平均)热膨胀系数及衬底105的整体热膨胀系数。
在一些实施例中，对载体101的热膨胀系数进行微调包括将载体101的热膨胀系数改变成使得在回流工艺期间，衬底105的上表面105U实质上匹配半导体封装250的下表面213L。可使用例如载体101的尺寸、衬底105的尺寸、衬底105的热膨胀系数及结构等因数来确定载体101的热膨胀系数。可使用计算机建模及模拟来针对载体101的给定热膨胀系数估计关于衬底105翘曲的细节。另外，可通过针对载体101使用不同材料(及不同热膨胀系数)来进行实验，且可通过缺陷检验器来测量及分析莫列波纹。在一些实施例中，使用计算机建模及模拟来确定载体101的潜在的热膨胀系数值或载体101的热膨胀系数值范围。接着，使用有不同的热膨胀系数值的不同材料来进行实验，且执行莫列波纹测量及分析以对载体101的热膨胀系数值进行确认及/或细调(fine tune)，直至使衬底105的翘曲实现目标细节为止。
图3A及图3B示出载体101具有单层式结构。载体101可具有多段式结构及/或多层式结构，如图18至图21中所说明。与由单一块状材料制成的载体相比，多段式结构及多层式结构(参见图18至图21)使得能够在选择用于构成载体101的结构及材料时提高灵活性。由于在载体101的设计中可对更多参数进行微调，实现了设计灵活性的提高，此使得能够在对载体101进行设计时具有更多自由度以满足在回流温度下对衬底105所引发的翘曲的目标细节。举例来说，可通过使用多段式及/或多层式结构来实现以复杂形状(例如非对称的弯曲上表面105U)对衬底105所引发的翘曲，而所述复杂形状在先前可能无法实现。
参照图18，其说明载体101的剖视图。载体101具有多段式结构，其包括第一段101A、第二段101B及第三段101C。第一段101A具有第一宽度W1及第一热膨胀系数值，第二段101B具有第二宽度W2及第二热膨胀系数值，且第三段101C具有第三宽度W3及第三热膨胀系数值。在所说明实施例中，第一段101A、第二段101B及第三段101C具有相同高度H。
可将载体101的不同段(例如101A、101B及101C)的宽度(例如W1、W2及W3)及热膨胀系数值(例如第一热膨胀系数值、第二热膨胀系数值及第三热膨胀系数值)彼此独立地进行选择，因此使得能够在对载体101进行设计时具有大的灵活性。在一些实施例中，宽度W1、W2及W3具有不同值。在一些实施例中，第一热膨胀系数值、第二热膨胀系数值及第三热膨胀系数值具有不同值。在另一实施例中，第一段101A与第三段101C具有相同宽度及相同热膨胀系数值，且第二段101B具有与第一段101A(及第三段101C)不同的宽度及不同的热膨胀系数值。
图19说明在一些实施例中载体101的剖视图。载体101具有多层式结构，其包括第一层101A、第二层101B及第三层101C。第一层101A具有第一高度H1及第一热膨胀系数值，第二层101B具有第二高度H2及第二热膨胀系数值，且第三层101C具有第三高度H3及第三热膨胀系数值。在所说明的实施例中，第一层101A、第二层101B及第三层101C具有相同宽度W。
仍参照图19，可将载体101的不同层(例如101A、101B及101C)的高度(例如H1、H2及H3)以及热膨胀系数值(例如第一热膨胀系数值、第二热膨胀系数值及第三热膨胀系数值)彼此独立地进行选择，因此使得能够在对载体101进行设计时具有大的灵活性。在一些实施例中，高度H1、H2及H3具有不同值。在一些实施例中，第一热膨胀系数值、第二热膨胀系数值及第三热膨胀系数值具有不同值。在另一实施例中，第一层101A的第一热膨胀系数值大于第二层101B的第二热膨胀系数值，且第二层101B的第二热膨胀系数值大于第三层101C的第三热膨胀系数值。
可将图18中的多段式结构与图19中的多层式结构组合来构成载体101，如图20及图21中所说明。参照图20，载体101类似于图18中的载体101，只不过中间段101B具有与图19所说明多层式结构类似的多层式结构。在图20所说明的实例中，层101B1、101B2及101B3分别具有高度H1、H2及H3且具有共同宽度W2。在一些实施例中，高度H1、H2及H3之和等于其他段101A及101C的高度H。可将载体101的不同段/层的尺寸(例如高度、宽度)及热膨胀系数值彼此独立地进行调整，以实现衬底105在回流温度下的翘曲的目标细节。
图21说明载体101的又一实施例。图21中的载体101类似于图20中的载体101，但其中多层式段(由101C表示)的位置是在载体101的右侧处。其他细节可类似于图20所示细节，因此不再予以赘述。
图18至图21仅为非限制性实例。可作出其他修改及变化，且其完全旨在被包含在本发明的实施例的范围内。举例来说，多段式结构中，段的数目可为多于或少于三个。类似地，多层式结构中，层的数目可为多于或少于三个。另外，在其中将多段式结构与多层式结构组合的实施例中，载体101的多于一个段可具有多层式结构，且具有多层式结构的段的位置可为载体101的任何适合的段。
本发明的实施例的优点包括装置故障率(failure)得以降低及制造良率得以提高。通过在回流温度下使衬底105的上表面105U的翘曲匹配半导体封装250的下表面213L的翘曲，半导体封装250的外部连接件217均接触衬底105的上表面105U上的各个导电接垫107，因此防止或减少冷焊的出现。在其中在回流工艺期间使用夹具来夹持半导体封装250的左侧及右侧以减少半导体封装250的翘曲的先前方法中，半导体封装250的被夹持部分经受高应力且可能在回流工艺期间破裂，并且半导体封装250的未被夹持的中间部分仍可能出现翘曲且具有冷焊问题。相比之下，本发明的实施例并不夹持半导体封装250，因此避免了与夹持相关联的问题。此外，载体101完全支撑衬底105的下表面，因此能够使衬底105的应力跨越大的区域(例如衬底105的下表面)分布且防止或减少对衬底105的损坏。载体101的多层式结构及多段式结构使得能够在为载体101选择结构及材料时具有大的灵活性。可实现使衬底105的翘曲具有复杂形状，而这是使用现有载体设计不可能实现的。
现在参照图4，在结合工艺之后，例如在半导体装置100冷却至室温之后，移除载体101。可通过例如穿过载体101向粘合层103(参见图3A)施加紫外(UV)光或激光来移除载体101，载体101对于紫外光或激光可为透明的。在一些实施例中，通过向粘合层103施加水来移除所述粘合层。还可使用其他适合的方法，例如机械剥除、蚀刻、研磨等。在载体101被移除之后，可通过额外清洁工艺来移除粘合层103的残留物(如果有)。因此，在一些实施例中，图4所示半导体装置100形成衬底芯片上芯片上封装。
图5至图8说明在另一实施例中半导体装置100在各种制作阶段的剖视图。图5至图8中的类似编号表示与图1至图4中类似的组件。图5至图8所示实施例类似于图1至图4中所说明的实施例，只不过衬底105不使用粘合层103贴合到载体101。在示例性的实施例中，图5至图8中的载体101是静电吸盘(electro-static chuck)。通过对静电吸盘供应电压，衬底105通过相反电荷的吸引力而贴合到所述静电吸盘。通过使电场停止(例如通过停止对静电吸盘供应电压)，可轻易地从载体101移除衬底105。由于不存在要移除的粘合层，因而工艺步骤的数目及处理时间得以减少。
在图5中，通过对载体101(静电吸盘)供应电压将衬底105贴合到载体101。在图6中，在衬底105之上设置半导体封装250，其中外部连接件217对准衬底105的上表面上的各个导电接垫107。可在导电接垫107之上形成焊料膏(图中未示出)。在图7中，在结合工艺(例如回流工艺)中，将半导体封装250的外部连接件217实体地及电性地结合到各个导电接垫107。在一些实施例中，载体101被设计成在回流温度下对衬底105引发预定程度的翘曲，使得在回流工艺期间外部连接件217接触各个导电接垫107，因此避免或减少冷焊的出现。载体101的细节可类似于上文参照图1至图4及图18至图21所述的细节，因此不再予以赘述。在图8中，在结合工艺之后，通过停止对载体101供应电压而从衬底105移除载体101。
图9至图13说明在另一实施例中半导体装置100在各种制作阶段的剖视图。图9至图13所示实施例类似于图1至图4所示实施例，只不过并非芯片上芯片(CoW)封装250，而是将集成扇出型(InFO)封装350贴合到衬底105的导电接垫107。图9至图13中的类似编号表示与图1至图4中类似的组件。
在图9中，将衬底105贴合到载体101。衬底105及载体101的细节类似于上文参照图1所述的细节，因此不再予以赘述。
图10说明集成扇出型封装350的剖视图。如图10中所说明，在载体301之上形成背侧介电层305。背侧介电层305可为背侧钝化层，且可包含通过物理气相沉积、化学气相沉积或其他适合的沉积方法而形成的聚合物、聚酰亚胺(polyimide)、氧化硅、氮化硅或其他适合的材料。载体301可含有基底材料，例如硅、聚合物、聚合物复合物、金属箔(metal foil)、陶瓷、玻璃、玻璃环氧树脂、氧化铍(beryllium oxide)、胶带或其他适于作为结构性支撑的材料。可在背侧介电层305与载体301之间形成粘合层，例如光热转换(LTHC)膜。
经由例如管芯贴合膜307将管芯309贴合到背侧介电层305。参看管芯309，在管芯309的上表面之上形成接触接垫311，且在接触接垫311之上形成钝化层315。通孔316延伸穿过钝化层315且电连接到接触接垫311。导电接垫318形成在钝化层315之上且电连接到通孔316。关于管芯309的形成细节可类似于图2中管芯201的形成细节，因此不再予以赘述。
通孔317形成在背侧介电层305之上且与管芯309横向间隔开。通孔317可包含导电材料(例如铜、钨)，且可通过以下操作来形成：在背侧介电层305之上形成晶种层、在晶种层之上形成经图案化光刻胶(photoresist)、进行镀覆以填充经图案化光刻胶层的开口、以及移除所述光刻胶并移除晶种层的位于通孔317的边界以外的部分。通孔317可在管芯309被贴合到介电层305之前或之后形成。
接下来，在背侧介电层305之上形成模制材料313。模制材料313环绕管芯309及通孔317。模制材料313可为模制化合物、环氧树脂等，且可通过压缩模制、转移模制等来施加。在固化之后，模制材料313可经历研磨工艺(例如化学机械平坦化(chemical mechanicalplanarization，CMP)工艺)，以暴露出管芯309的通孔317的上表面及导电接垫318的上表面。
接下来，在模制材料313及管芯309之上形成重布线结构320。重布线结构320可包括在一个或多个介电层325中形成的一个或多个重布线层(例如导电线321、通孔323)。穿孔317电耦合到重布线结构320的重布线层。重布线结构320的重布线层也电耦合到管芯309。重布线结构320的重布线层可由金属(例如铝、铜、钨、钛或其组合)形成，且可通过物理气相沉积(PVD)、化学气相沉积(CVD)、镀覆或其他适合的沉积方法来形成。重布线结构320的一个或多个介电层325可包含氧化硅、氮化硅、低介电常数电介质(例如掺碳氧化物)、极低介电常数电介质(例如多孔掺碳二氧化硅)、这些的组合等，且可通过例如化学气相沉积、物理气相沉积或任何其他适合的沉积方法等工艺来形成。
接下来，如图10中所说明，在重布线结构320的顶表面之上形成凸块下金属(under-bump metallurgy，UBM)结构331。可通过在重布线结构320之上沉积导电材料(例如铜、金或铝)并将所述导电材料图案化来形成凸块下金属结构331。可将电子组件333(例如集成式无源装置(integrated-passive device，IPD))耦合到凸块下金属结构331。可在凸块下金属结构331上形成外部连接件335，例如球栅阵列封装(ball-grid-array，BGA)、导电柱(例如铜柱)或顶部上具有焊料区的导电柱。接下来，图中未示出，将图10中的集成扇出型封装350上下翻转，且将外部连接件335贴合到例如切割胶带(dicing tape)等胶带。接着，通过脱离工艺从集成扇出型封装350移除载体301。在一些实施例中，在载体101被移除之前将多个集成扇出型封装(图中未示出)一起形成在载体101上，因此，可在载体101被移除之后执行切割以产生多个个别的集成扇出型封装350。
在图11中，在衬底105之上设置集成扇出型封装350。使集成扇出型封装350的外部连接件335对准衬底105的各个导电接垫107。可使用例如焊料喷射印刷工艺在衬底105的导电接垫107之上形成焊料膏(图中未示出)。
在图12中，执行结合工艺(例如回流工艺)，以将集成扇出型封装350的外部连接件335实体地及电性地耦合到衬底105的导电接垫107。在一些实施例中，载体101被设计成在回流温度下对衬底105引发预定程度的翘曲，使得在回流工艺期间外部连接件335接触各个导电接垫107，因此避免或减少冷焊。在一些实施例中，载体101的热膨胀系数被微调成使得由载体101与衬底105之间的热膨胀系数失配引起的衬底105的第一翘曲(例如弯曲上表面)实质上匹配集成扇出型封装350的第二翘曲(例如弯曲下表面)。载体101的细节可类似于上文参照图1至图4及图18至图21所述的细节，因此不再予以赘述。
在图13中，使用与上文参照图4所述的处理步骤类似的处理步骤来移除载体101。不再对细节予以赘述。
图14至图17说明在另一实施例中半导体装置100在各种制作阶段的剖视图。图14至图17中的类似编号表示与图9至图13中类似的组件。图14至图17所示实施例类似于图9至图13所示实施例，只不过衬底105不使用粘合层103贴合到载体101。在示例性的实施例中，载体101是静电吸盘。通过对静电吸盘供应电压，衬底105被贴合到所述静电吸盘。通过使电场停止，可轻易地从载体101移除衬底105。由于不存在要移除的粘合层，因而处理步骤的数目及处理时间得以减少。
在图14中，通过对载体101(静电吸盘)供应电压将衬底105贴合到载体101。在图15中，在衬底105之上设置半导体封装350(例如集成扇出型封装)，其中使外部连接件335对准衬底105的上表面上的各个导电接垫107。可在导电接垫107之上形成焊料膏(图中未示出)。在图16中，在结合工艺(例如回流工艺)期间，将半导体封装350的外部连接件335实体地及电性地结合到各个导电接垫107。在一些实施例中，载体101被设计成在回流温度下对衬底105引发预定程度的翘曲，使得在回流工艺期间外部连接件335接触各个导电接垫107，因此避免或减少冷焊。载体101的细节可类似于上文参照图1至图4及图18至图21所述的细节，因此不再予以赘述。在图17中，在回流工艺之后，通过停止对载体101供应电压而从衬底105移除载体101。
本发明的实施例可实现许多优点。举例来说，通过对载体101进行恰当设计，可在回流工艺期间对衬底105引发预定翘曲，以匹配半导体装置(例如图3A中的250及图12中的350)的翘曲。避免冷焊的出现，且提高了生产良率。本发明的实施例不需要使用夹具来夹持半导体装置，因此避免与应力的不均匀分布有关的对半导体封装的损坏。另外，载体101的多层式结构及多段式结构使得能够在对载体101进行设计时具有大的灵活性。可实现使衬底105的翘曲具有复杂形状，而这在先前是不可能实现的。
图22说明根据一些实施例制作半导体结构的方法的流程图。应理解，图22所示实施例方法仅为许多可能实施例方法的实例。所属领域中的一般技术人员将认识到许多变化、替代方案及修改。举例来说，可添加、去除、替换、重新安排及重复图22中所说明的各种步骤。
参照图22，在步骤1010，将衬底贴合到载体。在步骤1020，使第一半导体封装的外部连接件对准所述衬底的背对所述载体的第一表面上的第一导电接垫。在步骤1030，执行回流工艺，其中衬底与载体之间的第一热膨胀系数(CTE)失配使得在回流工艺期间所述衬底发生第一翘曲，其中第一半导体封装的各材料之间的第二热膨胀系数失配使得在回流工艺期间所述第一半导体封装发生第二翘曲，且其中第一翘曲实质上匹配第二翘曲。在步骤1040，在回流工艺之后，从衬底移除载体。
在一实施例中，一种半导体结构的制造方法包括：将衬底贴合到载体；使第一半导体封装的第一表面上的外部连接件对准所述衬底的背对所述载体的第一表面上的第一导电接垫；执行回流工艺，其中所述衬底与所述载体之间的热膨胀系数(CTE)差异使得在所述回流工艺期间所述衬底的所述第一表面为第一形状，其中所述第一半导体封装的各材料的热膨胀系数差异使得在所述回流工艺期间所述第一半导体封装的所述第一表面为第二形状，且其中所述第一形状实质上匹配所述第二形状；以及在所述回流工艺之后，从所述衬底移除所述载体。在一实施例中，将所述衬底贴合到所述载体包括使用粘合层将所述衬底贴合到所述载体。在一实施例中，所述载体是静电吸盘，其中将所述衬底贴合到所述载体包括对所述静电吸盘供应电压。在一实施例中，所述衬底是印刷电路板(PCB)。在一实施例中，所述第一形状及所述第二形状是弯曲形状。在一实施例中，执行所述回流工艺会将所述第一半导体封装实体地及电性地耦合到所述衬底。在一实施例中，所述方法进一步包括：在执行所述回流工艺之前，将第二半导体封装的外部连接件对准所述衬底的所述第一表面上的第二导电接垫，其中所述回流工艺将所述第一半导体封装及所述第二半导体封装实体地及电性地耦合到所述衬底。在一实施例中，所述衬底具有矩形形状、正方形形状、多边形形状或圆形形状。
在一实施例中，一种半导体结构的制造方法包括：对载体的热膨胀系数(CTEs)进行微调；将衬底的第一侧贴合到所述载体，所述衬底在所述衬底的与所述第一侧相对的第二侧上具有导电接垫；将半导体封装放置在所述衬底的所述第二侧上，其中位于所述半导体封装的与所述衬底面对的第一侧上的外部连接件对准所述衬底的各个所述导电接垫；以及加热所述衬底、所述载体及所述半导体封装，其中所述半导体封装的所述第一侧在所述加热期间具有第一弯曲形状，其中所述载体的所述热膨胀系数被相对于所述衬底的热膨胀系数微调成使得所述衬底的所述第二侧在所述加热期间具有第二弯曲形状，且其中所述第一弯曲形状实质上匹配所述第二弯曲形状。在一实施例中，所述方法进一步包括在加热所述衬底、所述载体及所述半导体封装之后从所述衬底移除所述载体。在一实施例中，在所述加热期间，所述半导体封装的所述外部连接件接触所述衬底的各个所述导电接垫。在一实施例中，所述方法进一步包括：分析所述半导体封装在加热温度下的翘曲；以及确定所述半导体封装的所述第一侧在所述加热温度下的所述第一弯曲形状。在一实施例中，所述衬底是印刷电路板。在一实施例中，所述半导体封装包括：半导体管芯；模制材料，位于所述半导体管芯周围；导电特征，电耦合到所述半导体管芯且延伸超过所述半导体管芯的边界；以及所述外部连接件，电耦合到所述导电特征，其中所述导电特征位于所述半导体管芯与所述外部连接件之间。在一实施例中，所述导电特征是位于所述半导体管芯与所述外部连接件之间的重布线结构的重布线层(RDL)。在一实施例中，所述导电特征是位于所述半导体管芯与所述外部连接件之间的中介层的通孔。
在一实施例中，一种半导体结构的制造方法包括：将衬底的第一侧贴合到载体；以及在结合温度下将半导体封装结合到所述衬底的与所述第一侧相对的第二侧，其中所述半导体封装的与所述衬底面对的第一侧在所述结合温度下具有第一弯曲形状，其中所述载体与所述衬底之间的热膨胀系数(CTE)差异使得所述衬底的所述第二侧在所述结合温度下为第二弯曲形状，且其中所述第一弯曲形状匹配所述第二弯曲形状。在一实施例中，结合所述半导体封装包括将所述半导体封装的外部连接件结合到设置在所述衬底的所述第二侧上的导电接垫，其中在所述结合期间所述半导体封装的所述外部连接件接触所述衬底的各个所述导电接垫。在一实施例中，所述方法进一步包括分析所述半导体封装在所述结合温度下的翘曲。在一实施例中，所述分析包括测量及分析所述半导体封装的莫列波纹。
以上内容概述了若干实施例的特征以使所属领域中的技术人员可更好地理解本发明的各方面。所属领域中的技术人员应了解，他们可易于使用本发明作为基础来设计或修改其他工艺及结构以施行本文所介绍实施例的相同目的及/或实现本文所介绍实施例的相同优点。所属领域中的技术人员还应认识到，此种等效构造并不背离本发明的精神及范围，且在不背离本发明的精神及范围的条件下，他们可对本文作出各种改变、替代、及变更。

Claims (10)

1.一种半导体结构的制造方法，其特征在于，包括：
将衬底贴合到载体；
使第一半导体封装的第一表面上的外部连接件对准所述衬底的背对所述载体的第一表面上的第一导电接垫；
执行回流工艺，其中所述衬底与所述载体之间的热膨胀系数差异使得在所述回流工艺期间所述衬底的所述第一表面为第一形状，其中所述第一半导体封装的各材料的热膨胀系数差异使得在所述回流工艺期间所述第一半导体封装的所述第一表面为第二形状，且其中所述第一形状实质上匹配所述第二形状；以及
在所述回流工艺之后，从所述衬底移除所述载体。
2.根据权利要求1所述的方法，其特征在于，将所述衬底贴合到所述载体包括使用粘合层将所述衬底贴合到所述载体，或者对所述载体供应电压，其中所述载体是静电吸盘。
3.根据权利要求1所述的方法，其特征在于，执行所述回流工艺将所述第一半导体封装实体地及电性地耦合到所述衬底。
4.一种半导体结构的制造方法，其特征在于，包括：
对载体的热膨胀系数进行微调；
将衬底的第一侧贴合到所述载体，所述衬底在所述衬底的与所述第一侧相对的第二侧上具有导电接垫；
将半导体封装放置在所述衬底的所述第二侧上，其中位于所述半导体封装的与所述衬底面对的第一侧上的外部连接件对准所述衬底的各个所述导电接垫；以及
加热所述衬底、所述载体及所述半导体封装，其中所述半导体封装的所述第一侧在所述加热期间具有第一弯曲形状，其中所述载体的所述热膨胀系数被相对于所述衬底的热膨胀系数微调成使得所述衬底的所述第二侧在所述加热期间具有第二弯曲形状，且其中所述第一弯曲形状实质上匹配所述第二弯曲形状。
5.根据权利要求4所述的方法，其特征在于，在所述加热期间，所述半导体封装的所述外部连接件接触所述衬底的各个所述导电接垫。
6.根据权利要求4所述的方法，其特征在于，进一步包括：
分析所述半导体封装在加热温度下的翘曲；以及
确定所述半导体封装的所述第一侧在所述加热温度下的所述第一弯曲形状。
7.一种半导体结构的制造方法，其特征在于，包括：
将衬底的第一侧贴合到载体；以及
在结合温度下将半导体封装结合到所述衬底的与所述第一侧相对的第二侧，其中所述半导体封装的与所述衬底面对的第一侧在所述结合温度下具有第一弯曲形状，其中所述载体与所述衬底之间的热膨胀系数差异使得所述衬底的所述第二侧在所述结合温度下为第二弯曲形状，且其中所述第一弯曲形状匹配所述第二弯曲形状。
8.根据权利要求7所述的方法，其特征在于，结合所述半导体封装包括将所述半导体封装的外部连接件结合到设置在所述衬底的所述第二侧上的导电接垫，其中在所述结合期间所述半导体封装的所述外部连接件接触所述衬底的各个所述导电接垫。
9.根据权利要求7所述的方法，其特征在于，进一步包括：分析所述半导体封装在所述结合温度下的翘曲。
10.根据权利要求9所述的方法，其特征在于，所述分析包括测量及分析所述半导体封装的莫列波纹。
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