TWI556400B - 堆疊式扇出半導體晶片 - Google Patents

堆疊式扇出半導體晶片 Download PDF

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Publication number
TWI556400B
TWI556400B TW102119606A TW102119606A TWI556400B TW I556400 B TWI556400 B TW I556400B TW 102119606 A TW102119606 A TW 102119606A TW 102119606 A TW102119606 A TW 102119606A TW I556400 B TWI556400 B TW I556400B
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Taiwan
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semiconductor wafer
layer
semiconductor
wafer
redistribution layer
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TW102119606A
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English (en)
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TW201405765A (zh
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索斯登 梅爾
吉拉德 歐菲若
史文 艾伯斯
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英特爾德國公司
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Publication of TW201405765A publication Critical patent/TW201405765A/zh
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Description

堆疊式扇出半導體晶片
本申請涉及一種堆疊的扇出半導體晶片。
存在幾種用於堆疊半導體晶片的方法。在線結合堆疊中，一個晶片可以被堆疊到另一個晶片上，並且兩個晶片之間的電接觸可以透過線結合產生。這些線結合堆疊可能具有大的尺寸和受限的電性能。在倒裝晶片線結合堆疊中，焊料凸塊可以被放置在晶片的頂側，並且所述晶片可以被倒裝，使得所述頂側(具有所述焊料凸塊)可以接觸置於基板上的電接觸。然後線結合晶片可以被附著到倒裝晶片的底部，形成堆疊。堆疊在所述封裝上的另外的晶片會需要線結合，產生大的封裝尺寸和受限的電性能。在直通矽通孔(TSV)晶片堆疊中，通孔可延伸(從晶片的主動側)穿過所述晶片以提供到所述晶片被動側的電連接。然而，TSV技術是昂貴的並且用於TSV晶片的供應鏈仍在開發。需要的是潛在地較不貴並且產生可相對地小並可具有極好電性能的晶片封裝的晶片堆疊技術。
在一些方面中，由晶片堆疊技術形成的半導體裝置可包括多個層，包括：具有第一半導體晶片的基層，所述第一半導體晶片在所述第一半導體晶片的第一側具有至少一個導電接觸，接觸所述第一半導體晶片的所述至少一個導電接觸的第一再分配層，其中第一再分配層可延伸到所述第一半導體晶片的邊界之外，具有第一側和第二側的第二半導體晶片，所述第二半導體晶片在所述第二半導體晶片的第一側具有至少一個導電接觸，以及放置在所述第一半導體晶片的第一側和所述第二半導體晶片的第二側之間的黏合劑層，其中所述第二半導體晶片可直接被放置在所述黏合劑層上。
所述半導體裝置可進一步包括：至少部分地放置在所述第二半導體晶片的第一側上方的電絕緣層，其中所述電絕緣層可具有暴露所述第一再分配層的至少一個通孔，以及接觸所述第二半導體晶片的所述至少一個導電接觸的第二再分配層，其中所述第二再分配層可透過所述至少一個通孔被電連接到所述第一再分配層。至少一個焊球可接觸所述第二再分配層。
所述半導體裝置可具有多個層。例如，所述半導體裝置可包括：具有第一側和第二側的第三半導體晶片，所述第三半導體晶片具有在所述第三半導體晶片的第一側的至少一個導電接觸，放置在第二半導體晶片的第一側和第三半導體晶片的第二側之間的第二黏合劑層，其中 所述第三半導體晶片可被直接放置在所述第二黏合劑層上，至少部分地放置在第三半導體晶片的第一側上方的第二電絕緣層，其中第二電絕緣層可具有暴露所述第二再分配層的至少一個通孔，以及接觸所述第三半導體晶片的所述至少一個導電接觸的第三再分配層，其中所述第三再分配層可透過所述第二電絕緣層的至少一個通孔被電連接到所述第二再分配層。
在一些方面中，半導體裝置的基層可以是重構晶圓，並且所述第一半導體晶片可被嵌入在所述重構晶圓中。多個半導體晶片也可被嵌入在所述重構晶圓中。所述多個半導體晶片可包括至少一個被動半導體晶片和至少一個主動半導體晶片。
所述半導體裝置的所述第一半導體晶片和第二半導體晶片可形成單個積體電路封裝。在一些方面中，第二半導體晶片可以是在不損壞所述封裝的情況下不可從所述單個積體電路封裝釋放的。
在另一些方面中，半導體裝置的黏合劑層可被至少部分地放置在所述第一再分配層上。所述第一半導體晶片和第二半導體晶片可以是積體電路。
在另外的方面中，所述半導體裝置可包括：將所述第二半導體晶片的所述至少一個導電接觸電連接到所述第一再分配層的至少一個線，和至少部分地放置在所述第二半導體晶片的第一側和所述至少一個線的上方的電絕緣層，其中所述電絕緣層可具有暴露所述第一再分配層 的至少一個通孔。
在此還描述了一種半導體裝置，其具有：具有第一半導體晶片的基層，所述第一半導體晶片在所述第一半導體晶片的第一側具有至少一個導電接觸，接觸所述第一半導體晶片的所述至少一個導電接觸的第一再分配層，其中第一再分配層可延伸到所述第一半導體晶片的邊界之外，具有第一側和第二側的半導體倒裝晶片，所述半導體倒裝晶片在所述半導體倒裝晶片的第一側具有至少一個導電接觸。所述第一半導體晶片的第一側可面向所述半導體倒裝晶片的第一側。所述半導體裝置也可包括：至少部分地放置在所述半導體倒裝晶片的第二側上方的電絕緣層，其中所述電絕緣層可具有暴露所述第一再分配層的至少一個通孔，以及穿過所述至少一個通孔和第一再分配層電連接到所述半導體倒裝晶片的所述至少一個導電接觸的第二再分配層。
用於製作半導體裝置的方法也在此被描述。所述方法可包括：在具有第一半導體晶片的基層的表面上形成第一再分配層，所述第一半導體晶片在所述第一半導體晶片的第一側具有至少一個導電接觸，其中所述第一再分配層可接觸所述第一半導體晶片的所述至少一個導電接觸；至少部分地在所述第一再分配層的表面上施加黏合劑層；在所述黏合劑層上放置第二半導體晶片；在所述第二半導體晶片周圍施加聚合體層；形成穿過所述聚合體層的至少一個通孔，其中所述至少一個通孔可暴露所述第一再 分配層；以及在所述聚合體層的表面上形成第二再分配層。所述第二半導體晶片可以在所述第二半導體晶片的第一側具有至少一個導電接觸，並且其中放置所述第二半導體晶片可包括將所述第二半導體晶片的第二側放置在所述黏合劑層上，所述第二側與所述第一側不同。所述方法可進一步包括：至少部分地在所述第二半導體晶片的第一側上形成電絕緣層；以及形成穿過所述絕緣層的至少一個通孔，其中所述至少一個通孔可暴露所述第一再分配層。
在一些方面中，所述方法可進一步包括在電絕緣層上形成第二再分配層，其中所述第二再分配層可透過所述至少一個通孔將所述第二半導體晶片的所述至少一個導電接觸電連接到所述第一再分配層。所述方法可進一步包括將至少一個焊球放置在所述第二再分配層上。
所述方法可包括至少部分地在所述第二分配層的表面上施加第二黏合劑層；在所述第二黏合劑層上放置第三半導體晶片；至少部分地在所述第三半導體晶片上形成第二電絕緣層；形成穿過所述第二絕緣層的至少一個通孔，其中所述第二絕緣層的至少一個通孔可暴露所述第二再分配層；以及在所述第二電絕緣層上形成第三再分配層，其中所述第三再分配層可透過所述第二絕緣層的所述至少一個通孔將所述第三半導體晶片的至少一個導電接觸電連接到所述第二再分配層。
所述方法可包括研磨所述基層以去除多餘材料。在一些方面中，所述基層可以是重構晶圓，並且所述 第一半導體晶片可以被嵌入在所述重構晶圓中。所述方法可以進一步包括在施加所述聚合體層之前，使用線將所述第二半導體晶片的至少一個導電接觸電連接到所述第一再分配層。
在考慮下面的詳細描述時，本公開的這些以及其它方面將是顯而易見的。
101‧‧‧基層(重構晶圓)
103‧‧‧絕緣層(模塑)
105‧‧‧晶片
105-1‧‧‧晶片
105-2‧‧‧晶片
106‧‧‧接觸
107‧‧‧第一側
108‧‧‧第二相對側
109‧‧‧電絕緣層(電介質)
110‧‧‧金屬化延伸
111‧‧‧第一再分配層
112‧‧‧占位空間
113‧‧‧黏合劑層
114‧‧‧第二半導體晶片
114-1‧‧‧晶片
114-2‧‧‧晶片
115‧‧‧第一側
116‧‧‧第二側
117‧‧‧金屬化延伸(導電延伸)
119‧‧‧電絕緣層(模塑層)
121‧‧‧位置
123‧‧‧通孔
125‧‧‧導電材料
127‧‧‧第二再分配層
129‧‧‧第二電絕緣層
131‧‧‧位置
133‧‧‧焊球
135‧‧‧位置
137‧‧‧封裝
137-1‧‧‧半導體裝置封裝
137-2‧‧‧半導體裝置封裝
200‧‧‧半導體裝置(半導體封裝)
201‧‧‧晶片
203‧‧‧晶片
205‧‧‧晶片
207‧‧‧晶片
300‧‧‧半導體裝置(半導體封裝)
303‧‧‧黏合劑
305‧‧‧半導體晶片
305-1‧‧‧晶片
305-2‧‧‧晶片
307‧‧‧電絕緣層(電介質)
309‧‧‧通孔
311‧‧‧第三再分配層
313‧‧‧電絕緣層
315‧‧‧焊球
409‧‧‧倒裝晶片封裝
409-1‧‧‧倒裝晶片封裝
409-2‧‧‧倒裝晶片封裝
411‧‧‧第一側
413‧‧‧第二側
415‧‧‧焊料凸塊
417‧‧‧電絕緣層
419‧‧‧位置
421‧‧‧通孔
423‧‧‧導電材料
425‧‧‧第二再分配層
427‧‧‧半導體封裝
429‧‧‧電絕緣層
431‧‧‧焊球
500‧‧‧半導體封裝
501‧‧‧導電線
503‧‧‧電絕緣層
505‧‧‧電絕緣層(通孔)
509‧‧‧第二再分配層
511‧‧‧電絕緣層
513‧‧‧焊球
600‧‧‧半導體封裝
601‧‧‧基層(重構晶圓)
603‧‧‧被動晶片
605‧‧‧主動晶片
607‧‧‧電絕緣層
609‧‧‧第一再分配層
611‧‧‧被動晶片
613‧‧‧黏合劑
615‧‧‧主動晶片
617‧‧‧電絕緣層
619‧‧‧導電填充物
621‧‧‧第二再分配層
623‧‧‧電絕緣層
625‧‧‧被動晶片
627‧‧‧焊球
700‧‧‧半導體裝置
701‧‧‧基層
703‧‧‧倒裝晶片封裝
705‧‧‧填充材料
707‧‧‧被動晶片
A‧‧‧焊球高度
B‧‧‧電介質和第二半導體高度
C‧‧‧第二半導體晶片和第二金屬化延伸高度
D‧‧‧第一介電層、第一再分配層、以及黏合劑高度
E‧‧‧模塑的重構晶圓高度
F‧‧‧總體高度
透過參考下面考慮到附圖的描述，可以對本公開以及在此描述的各方面的潛在優點得到更完全的理解，在附圖中相似的參考數字表示相似的特徵，並且其中：圖1A-1K示出半導體裝置(或者其各部分)和/或根據此處描述的一個或多個方面製作半導體裝置的實例方法的側面剖視圖的實例。
圖2示出根據此處描述的一個或多個方面，半導體裝置(或者其部分)的側面剖視圖的另一實例。
圖3示出根據此處描述的一個或多個方面，半導體裝置(或者其部分)的側面剖視圖的又一實例。
圖4A-4E示出根據此處描述的一個或多個方面，具有倒裝晶片封裝的半導體裝置(或者其各部分)和/或製作具有倒裝晶片封裝的半導體裝置的實例方法的側面剖視圖的實例。
圖5A-5D示出根據此處描述的一個或多個方 面，具有線的半導體裝置(或者其各部分)和/或製作具有線的半導體裝置的實例方法的側面剖視圖的實例。
圖6A-6C示出根據此處描述的一個或多個方面，具有主動和/或被動部件的半導體裝置(或者其各部分)和/或製作具有主動和/或被動部件的半導體裝置的實例方法的側面剖視圖的實例。
圖7示出根據此處描述的一個或多個方面，具有主動和/或被動部件的半導體裝置(或者其部分)的側面剖視圖的另一實例。
應該注意到所述附圖中的一個或多個可不必要按比例繪製。
圖1A-1K示出半導體裝置(或者其各部分)和/或根據此處描述的一個或多個方面製作半導體裝置的實例方法的側面剖視圖的實例。在圖1A中，可提供基層(基板層)101。所述基層101可以是重構晶圓，例如具有各扇出部分的重構晶圓(諸如，晶圓級球(WLB)或者嵌入晶圓級球(eWLB)晶圓)。所述重構晶圓可以透過選擇多個半導體晶片105(其可以是晶粒)形成，作為實例，所述多個半導體晶片105被示為晶片105-1和105-2，其可以已知和/或測試為良好的(例如，起作用的)。所述半導體晶片105可取自由其來形成晶片105的晶圓(例如，透過切割矽晶圓)並且使用黏合箔被放置到載體 上。所述晶片105可以被面朝上地(例如，具有導電(例如，金屬)接觸106的晶片105的主動側面朝上)放置在載體上或者面朝下地(例如，具有導電接觸106的晶片的主動側面朝下)放置在載體上以形成第一半導體晶片105層。如果在初始矽晶圓中所述晶片105的密度大於所述重構晶圓101的所需密度(即，如果在初始矽晶圓中晶片105之間的距離小於在基層101中晶片105之間的距離)，與所述晶片105在初始矽晶圓上相比，從初始矽晶圓去除的所述晶片105可以以彼此間更大的距離被放置在載體上。如將在下面的實例中以更多細節被描述的，透過展開所述晶片105，可以形成扇出區域。
可以在所述晶片105的周圍形成例如模塑(molding)的電絕緣層103以生成基層101。例如，可以透過壓縮模塑生成基層101以生成圓形晶圓、矩形晶圓，或任何其它形狀的晶圓。因此，所述半導體晶片105可透過模塑程序被至少部分地嵌入在所述基層101中。可使用本領域普通技術人員可用的任何方法暴露所述導電接觸106。例如，可透過所述絕緣層103的研磨、雷射去除、和/或研磨和雷射去除的結合將所述接觸106暴露。所述基層101可被用作用於堆疊另外的層和/或晶片的起始基礎。因此，可以不需要另外的半導體晶片承載系統。
嵌入在所述重構晶圓中的半導體晶片105可以包括具有多個導電接觸106的第一側107(在此被稱作“頂”側，不管相對於重力或者相對於所述裝置的剩餘部 分的實際取向)。所述接觸106可透過將例如多晶矽和/或金屬(諸如，鋁)的任何導電材料沉積到半導體晶片105上形成。所述接觸106也可被例如銅柱、柱子，或者其它結構的金屬結構覆蓋(全部地或者部分地)。示例性的金屬結構可以是例如7到20μm厚。所述金屬結構可以在將層和/或材料從所述半導體晶片去除期間(例如在雷射鑽孔期間)保護所述接觸106。一些層和/或材料去除程序(例如光微影)可不需要保護所述接觸106的金屬結構。因此，如將在下面的實例中以更多細節被描述的，如果電絕緣層109透過光微影被構造，金屬結構可能不需要覆蓋所述接觸106。下面描述的所述晶片接觸的任何一個可類似地包括覆蓋所述接觸的金屬結構，以在所述層和/或材料去除期間保護它們。所述接觸可以形成為用來形成所述初始矽晶圓的程序的一部分。在一些方面中，因為再分配層、被動層、焊料停止(solder stop)、和/或焊球未被形成在所述重構晶圓101上，所以所述裸露的接觸106不可能是可焊接的。半導體晶片105也可具有可以具有或者可以不具有任何導電接觸的第二相對側108(例如，“底”側)。
在圖1B中，電絕緣層109(例如，電介質)可被形成在所述重構晶圓101上。接觸106可例如透過使用光微影和/或雷射技術被暴露。可以在被暴露的接觸106上形成金屬化延伸110(其可由銅或者其它導電材料製成)。第一再分配層111可以被形成在所述電介質109的 上方。所述第一再分配層111可包括多個再分配線，所述再分配線的至少一些可以延伸到所述一個或多個半導體晶片105的邊界之外，在所述晶片105之間的區域中形成扇出區域。透過將所述接觸106扇出到每個晶片105的占位空間112的外面，所述接觸106可更容易接入(例如，到另外的半導體晶片和/或其它類型的部件，接觸，等)。再分配層可以使用各種薄膜和/或印刷電路板(PCB)沉積技術被施加，包括濺射和電鍍、無電極種子層施加、電解電鍍、印刷、和/或其它沉積程序。
在圖1C中，黏合劑層113可被形成在所述第一半導體晶片105層的上方(諸如，透過印刷、層壓、點膠(dispensing)等)，例如在所述電介質109上和/或所述第一再分配層111上。所述第一再分配層111的各部分可保持暴露以便於晶片堆疊。例如，如在下面的實例中將以更多細節被描述的，黏合劑可被施加到半導體晶片的第二層的拾取和放置位置。黏合劑可以包括例如環氧樹脂、聚醯亞胺、矽樹脂、其它材料、以及其結合。此外，所述黏合劑可被填充有例如矽和碳的填充物以及其它類型的填充物，或者未被填充。雖然所述黏合劑層113被示作圖案化層，所述黏合劑層113可以是所述晶片105之間的連續層。而且，所述黏合劑層113的邊界可在每個所述晶片105的占位空間處或在每個所述晶片105的占位空間內部，或者所述黏合劑層113可以延伸到每個所述晶片105的占位空間之外。
在圖1D中，半導體晶片114的第二層(作為實例被示為晶片114-1和114-2)可被直接地放置在所述黏合劑113上。可以使用拾取和放置機。第二半導體晶片114可以均包括具有多個導電接觸的第一側115(例如，頂側)。可以以與用於半導體晶片105的第一層相同或者相似的方式在所述第二半導體晶片114的接觸上形成金屬化延伸117(例如，由銅或者其它導電材料製成)。在一些方面中，所述金屬化延伸117可以例如以銅凸點下金屬化(UBM)的形式被預施加到所述晶片114的接觸。所述第二晶片114也可以均具有第二側116(例如，底側)，所述第二側可以具有或者可以不具有任何導電接觸。所述第二側116可以被直接放置在所述黏合劑113上。
在圖1E中，電絕緣層119(例如模塑層或者層壓層)可被形成在所述第二半導體晶片114的周圍，使得所述第二晶片114至少部分地嵌入在所述絕緣層119中。所述絕緣層119可以使用例如層壓、壓縮模塑、印刷等的任何半導體製作程序步驟被施加。在圖1F中，所述絕緣層119可例如透過所述絕緣層的研磨和/或雷射鑽孔在尺寸上被減小(例如，變薄)。研磨所述絕緣層119(例如，到位置121)可以暴露所述第二半導體晶片114的導電延伸117。
在圖1G中，可例如透過鑽孔(例如，雷射鑽孔)和或光微影程序在所述電絕緣層119中形成一個或多個通孔123(例如，互連路徑)。所述通孔123可以暴露 所述第二半導體晶片114的導電延伸117和/或所述第一再分配層111。例如，在所述第一再分配層111和/或一個或多個導電延伸117處，所述鑽孔可被致使停止。
在圖1H中，所述通孔123可被填充有一個或多個導電材料125，例如銅，以允許電接入到所述第一再分配層111和/或所述第二半導體晶片114的導電延伸117。在所述模塑層119的上方也可形成(例如，透過濺射和電鍍、無電極種子層電鍍、或者電解電鍍)第二再分配層127。在一些方面中，可以與所述再分配層127的形成一起來填充所述通孔123。替代地，可以與所述再分配層127的形成分開地填充所述通孔123。例如，所述通孔123可以首先被填充(例如，透過印刷、電解電鍍等)。然後，可形成再分配層127。所述通孔123可以完全地或者部分地填充有導電材料。部分地填充的通孔可以是塞緊的通孔，其中再分配類型層透過所述通孔被向下傳遞，並且如將在下面實例中以更多細節描述的，所述通孔的其餘部分被單獨填充或者由例如第二電絕緣層129的電絕緣材料填充。所述第二再分配層127可以生成所述第一和第二半導體晶片的導電接觸的第二扇出互連。例如，所述接觸可以被扇出到每個所述第一半導體晶片105的占位空間的外部，每個所述第二半導體晶片114的占位空間的外部，和/或所述第一和第二半導體晶片105，114兩者的占位空間的外部。所述第二再分配層127可以透過將所述導電材料125填充所述至少一個通孔123來被電連接到所述第一 再分配層111。所述第二再分配層127可類似地被電連接到所述第二半導體晶片114的一個或多個導電接觸。在一些方面中，在所述第二再分配層127和所述第一再分配層111和/或導電延伸117之間的電連接可以不需要任何焊料，潛在地簡化了用來生成所述半導體裝置的製造程序和/或潛在地提高了所述半導體裝置的穩固性(例如，抵抗高溫的能力)。
在圖1I中，可在所述第二再分配層127上形成第二電絕緣層129(例如，電介質)。所述第二再分配層127可以被暴露在一個或多個位置131(例如，透過雷射鑽孔、光微影等)。在圖1J中，可施加焊料停止層，和/或焊球133(例如，球或者半球)。在圖1K中，背向在其上施加(或者將施加)焊球133的側面的所述基層101的底部(例如，模塑103)可以被研磨以減小所述結構的高度，例如減小到位置135。然後可以在每個堆疊的晶片組和/或每個其它部件之間，例如在圖1K中透過虛線示出的位置處，分開(例如，切割)所述結構，產生了多個分開的半導體裝置封裝。例如，在圖1K的實例中示出兩個半導體裝置封裝137-1和137-2，每個所述封裝可以具有多個半導體晶片(例如，第一半導體晶片105和第二半導體晶片114)。替代地，參考數字137-1和137-2可以形成單個半導體封裝。所述第一半導體晶片105和第二半導體晶片114可能是不可從相應封裝137釋放的。
圖2根據此處描述的一個或多個方面示出半 導體裝置200(或者其部分)的側面剖視圖的另一實例。可以在所述重構晶圓或者任何其它層中嵌入多個半導體晶片(例如，晶片201，203，205和207)和/或其它主動或者被動部件(如將在下面的實例中以更多細節被描述的)。所述實例半導體封裝200可以具有非常低的封裝高度。例如，所述焊球高度A可以是在200μm到300μm的範圍中，例如大約250μm(在焊球之間具有大約0.50mm的間距)。所述焊球高度A可以是在150μm到250μm的範圍中，例如大約200μm(具有大約0.40mm的間距)。所述電介質和第二半導體高度B可以是在5μm到40μm的範圍中，例如大約30μm。所述第二半導體晶片和第二金屬化延伸高度C可以是在20μm到250μm的範圍中，例如大約120μm。所述第二金屬化高度針對雷射鑽孔連接可以在10μm到30μm範圍中，以及針對其它連接類型可以在5μm到15μm範圍中。例如，所述第二半導體晶片可以具有大約100μm的高度，並且所述金屬化延伸可以具有大約20μm的高度。在一些方面中，所述第二晶片可以具有甚至更低的高度，例如大約50μm。所述第一介電層、第一再分配層、以及黏合劑高度D可以是大約40μm。所述模塑的(和研磨的)重構晶圓高度E可以是大約100μm。因此，具有兩個半導體晶片層的三維半導體封裝200可以具有大約490μm的總體高度F(或者大約440μm，如果所述第二半導體晶片在高度上大約是50μm)。相似地，具有三個半導體晶片層的封裝可以具 有大約600μm的總體高度。此處描述的所述實例尺寸也可以應用到其它實施例中，例如圖1K，3，4E，5D，6C，和7的實例實施例。所述堆疊的晶片組和/或其它部件可以再一次被分開(例如，切割)以形成單獨的封裝。
除了由在本公開中包括的實例所體現的潛在尺寸優勢，相比於製作起來可能是相當昂貴的利用直通矽通通孔(TSV)的封裝，所述半導體裝置200製作起來可以是較不昂貴的。如果需要，可以例如透過扇出所述半導體晶片的導電焊盤並且使用一個或多個再分配層來避免TSV。此外，所述堆疊的電性能可以從使用再分配材料層和所述再分配層之間的短路連接中獲益。晶片和/或封裝的另外堆疊是可能的。例如，封裝可以包括多於三個的層。封裝也可以被堆疊到其它封裝上。
圖3示出根據此處描述的一個或者多個方面，半導體裝置300(或者其部分)的側面剖視圖的另一實例。所述半導體裝置300可以具有三個(或者更多)半導體晶片層。製作具有三個(或者更多)層的裝置的方法可以從在圖1H中示出的中間半導體裝置繼續。可以在多個半導體晶片305(在圖3中作為實例被示為晶片305-1和305-2)的第三層的拾取和放置位置處形成(例如，透過印刷、層壓、點膠等)第二黏合劑層303。所述第三半導體晶片305可以被直接放置在所述黏合劑303上。所述第三半導體晶片305可以具有第一側(例如，頂側)，所述第一側具有多個導電接觸和/或導電延伸。第三半導體 晶片305也可以具有被放置在所述黏合劑303上的第二側(例如，底側)。可以在所述第三半導體晶片305的周圍形成第三電絕緣層307，並且可以形成(例如，透過鑽孔)多個通孔309以暴露所述第三半導體晶片305的所述第二再分配層和/或所述導電延伸。可以在所述電介質307的上方形成第三再分配層311。如先前描述的，所述第三再分配層311可以將半導體晶片105的第一層的導電接觸、半導體晶片114的第二層、和/或半導體晶片305的第三層扇出。可以在所述第三再分配層311的上方和/或周圍形成電絕緣層313，並且鑽孔和/或其它光微影技術可以暴露所述第三再分配層311。這些步驟可以被重複任何次數以形成半導體晶片的任何數目的疊層。在最後的層中，可以施加焊料停止和/或焊球315以形成半導體封裝300。與其它實施例相似，所述堆疊的晶片組和/或其它部件可被分開(例如，切割)以形成單個封裝。
圖4A-4E示出根據此處描述的一個或多個方面的具有一個或多個倒裝晶片封裝的半導體裝置(或者其各部分)和/或製作具有一個或多個倒裝晶片封裝的半導體裝置的實例方法的側面剖示圖的實例。製作具有一個或多個倒裝晶片封裝的半導體裝置的方法可以從在圖1B中示出的中間半導體裝置繼續。如在圖1C中示出的，取代施加黏合劑層，可以使用倒裝晶片封裝，例如倒裝晶片封裝409-1和409-2。在圖4A中，倒裝晶片封裝409可以具有第一側411(例如，主動側)，所述第一側具有多個導 電接觸。倒裝晶片封裝409也可以具有可能不具有任何導電接觸的第二側413。倒裝晶片封裝409可以具有電連接到所述倒裝晶片封裝409的導電接觸的多個焊料凸塊415(例如，倒裝晶片μ凸塊)。所述焊料凸塊415可透過例如銅UBM的金屬化元件被附著到所述導電接觸。以焊料凸塊415面朝“上”，倒裝晶片封裝409可以被倒裝並且被直接放置在所述第一再分配層111上。當被倒裝時，所述倒裝晶片封裝409的主動側411可以面對所述嵌入半導體晶片105的主動側。可以透過將所述焊料凸塊415焊接到所述第一再分配層111上，和/或透過使用熱壓縮結合，和/或透過使用其它半導體裝置製作技術來保持電氣和/或物理連接。
在圖4B中，所述倒裝晶片封裝409可以使用電絕緣材料被底部填充、過模塑，和/或過模塑/欠模塑(例如，模塑底部填充(MUF))，形成電絕緣層417(例如，模塑層)。例如，可將能夠在由所述焊料凸塊415形成的間隙之間流動的材料用於底部填充。在圖4C中，電絕緣層417可被研磨以減小封裝高度(例如，到位置419)。可以形成(例如，透過雷射鑽孔、光微影等)多個通孔421(例如，互連路徑)以暴露所述第一再分配層。在圖4D中，所述通孔421可以被填充有導電材料423，並且可以形成第二再分配層425以扇出嵌入在所述重構晶圓中和/或倒裝晶片封裝409中的第一半導體晶片的電接觸。在圖4A-4D中示出的步驟可以被重複以形成 具有任何數目的半導體晶片層的半導體封裝。
圖4E示出根據此處描述的一個或多個方面，具有兩個半導體晶片層(包括倒裝晶片層)的半導體封裝427的側面剖視圖的實例。所述半導體封裝427可以具有另一個電絕緣層429，焊料停止，和/或焊球431。與其它實施例相似，所述堆疊的晶片組和/或其它部件可以被分開(例如，切割)以形成更小的單獨封裝。
圖5A-5D示出根據此處描述的一個或多個方面，具有線的半導體裝置(或者其各部分)和/或製作具有線的半導體裝置的實例方法的側面剖視圖的實例。製作具有線的半導體裝置的所述方法可以從在圖1D中示出的中間半導體裝置繼續。因為線可以被直接連接到裸露晶片(例如，第二晶片114)，所以可以不需要導電延伸117。在圖5A中，導電線501可以將所述第一再分配層111電連接到所述第二半導體晶片114的導電接觸。在圖5B中，可以在所述第二半導體晶片114和/或所述線501周圍形成電絕緣層503(例如，模塑)。在圖5C中，可在電絕緣層505中形成多個通孔505(例如，互連路徑)以暴露所述第一再分配層111。
圖5D示出具有至少兩個堆疊半導體晶片層並且使用線結合堆疊用於半導體晶片的第二層的半導體封裝500的實例。由在圖5C中示出的方法，所述通孔505可被填充有導電材料，可形成第二再分配層509，可形成電絕緣層511(例如電介質)，和/或可形成焊球513(以及 焊料停止)。與其它實施例相似，所述堆疊的晶片組和/或其它部件可被分開(例如，切割)以形成更小的單獨封裝。
圖6A-6C示出根據此處描述的一個或多個方面，具有主動和/或被動部件的半導體裝置(或者其各部分)和/或製作具有主動和/或被動部件的半導體裝置的實例方法的側面剖視圖的實例。此處描述的半導體裝置可以包括任何數目的主動和被動半導體晶片。主動半導體晶片可以包括，但不限於，積體電路，例如記憶體、基帶晶片、處理器等。被動半導體晶片可以包括，但不限於，表面安裝裝置(SMD)、積體被動裝置(IPD)、電阻器、電容器、二極體、電感器等等。
在圖6A中，可以提供基層601(例如，重構晶圓)。所述基層101可以具有多個嵌入主動晶片605和/或多個嵌入被動晶片603。在圖6B中，可在所述重構晶圓601上形成電絕緣層607(例如，電介質)。使用暴露的所述晶片603和/或605的接觸，可以在所述半導體裝置上形成第一再分配層609。可以放置與所述第一再分配層609電連接的另外的主動晶片615和/或被動晶片611。例如，主動晶片615可以透過黏合劑613在結構上被連接到絕緣層607。如先前描述的，在圖1(例如，RDL連接)和圖5(例如，線結合連接)中示出的實例中，主動晶片615的主動側可以是面朝上。如先前描述的，晶片615的接觸可被覆蓋有金屬結構(例如，銅柱)。替代 地，在圖4中示出的實例中(例如，倒裝晶片連接)，晶片615的主動側可以是面朝下。
在圖6C中，可在主動晶片615和/或被動晶片611的第二層的周圍形成電絕緣層617(例如，可光學構造的電絕緣層)。可暴露(例如，透過雷射鑽孔、光微影等)所述第一再分配層609和/或其它導電接觸(例如，在主動晶片和/或被動晶片上的接觸)，並且可以使用導電填充物619來將所述第一再分配層電連接到上層。可以在所述半導體裝置上形成第二再分配層621和電絕緣層623(例如，電介質)。可以將另外的主動晶片和/或被動晶片625與所述第二再分配層621電連接放置。可以將焊球627與所述第二再分配層621電連接放置以形成具有多個被動和/或主動部件的半導體封裝600。與其它實施例相似，所述堆疊的晶片組和/或其它部件可被分開(例如，切割)以形成更小的單獨封裝。
圖7示出根據此處描述的一個或多個方面，具有主動和/或被動部件的半導體裝置700(或者其部分)的側面剖視圖的另一實例。半導體裝置700可以具有基層701(例如，重構晶圓)，所述基層具有嵌入的被動和/或主動晶片。所述半導體裝置700可以具有主動和/或被動的晶片和/或封裝的一個或者多個另外的層，所述主動和/或被動的晶片和/或封裝例如是主動倒裝晶片封裝703和多個被動晶片707。所述倒裝晶片封裝703可以在所述倒裝晶片封裝已經被放置成與再分配層電連接(例如，透過 焊接、熱壓縮結合等)之後，使用填充材料705被底部填充。與其它實施例相似，所述堆疊的晶片組和/或其它部件可被分開(例如，切割)以形成更小的單獨封裝。
雖然已經示出和描述各種實施例，但只是實例。在本說明書中使用的詞是描述的詞而不是限制的詞，並且應該理解在不偏離本公開的精神和範圍的情況下可作出各種改變。
135‧‧‧位置
137-2‧‧‧半導體裝置封裝

Claims (22)

  1. 一種半導體裝置，包括：具有第一半導體晶片的基層，該第一半導體晶片在該第一半導體晶片的第一側具有至少一個導電接觸，其中該第一半導體晶片係與該基層直接附接；與該第一半導體晶片的該至少一個導電接觸接觸的第一再分配層，其中該第一再分配層延伸到該第一半導體晶片的邊界之外；具有第一側和第二側的第二半導體晶片，該第二半導體晶片在該第二半導體晶片的第一側具有至少一個導電接觸；至少部分包封該第二半導體晶片的電絕緣層，其中該電絕緣層具有暴露該第一再分配層的至少一個通孔；和放置在該第一半導體晶片的第一側和該第二半導體晶片的第二側之間的黏合劑層，其中該第二半導體晶片被直接放置在該黏合劑層上。
  2. 如申請專利範圍第1項的半導體裝置，進一步包括：與該第二半導體晶片的該至少一個導電接觸接觸的第二再分配層，其中該第二再分配層透過該至少一個通孔被電連接到該第一再分配層。
  3. 如申請專利範圍第2項的半導體裝置，進一步包括：與該第二再分配層接觸的至少一個焊球。
  4. 如申請專利範圍第2項的半導體裝置，進一步包括：具有第一側和第二側的第三半導體晶片，該第三半導體晶片在該第三半導體晶片的第一側具有至少一個導電接觸；放置在該第二半導體晶片的第一側和該第三半導體晶片的第二側之間的第二黏合劑層，其中該第三半導體晶片被直接放置在該第二黏合劑層上；至少部分地包封該第三半導體晶片的第二電絕緣層，其中該第二電絕緣層具有暴露該第二再分配層的至少一個通孔；以及與該第三半導體晶片的該至少一個導電接觸接觸的第三再分配層，其中該第三再分配層透過該第二電絕緣層的該至少一個通孔被電連接到該第二再分配層。
  5. 如申請專利範圍第1項的半導體裝置，其中該基層是重構晶圓並且其中該第一半導體晶片被嵌入在該重構晶圓中。
  6. 如申請專利範圍第5項的半導體裝置，其中多個半導體晶片被嵌入在該重構晶圓中。
  7. 如申請專利範圍第6項的半導體裝置，其中該等多個半導體晶片包括至少一個被動半導體晶片和至少一個主動半導體晶片。
  8. 如申請專利範圍第1項的半導體裝置，其中該第一半導體晶片和該第二半導體晶片形成單個積體電路封裝。
  9. 如申請專利範圍第8項的半導體裝置，其中該第二半導體晶片是在不損壞該封裝的情況下不可從該單個積體電路封裝釋放的。
  10. 如申請專利範圍第1項的半導體裝置，其中該黏合劑層被至少部分地放置在該第一再分配層上。
  11. 如申請專利範圍第1項的半導體裝置，其中該第一半導體晶片和該第二半導體晶片是積體電路。
  12. 如申請專利範圍第1項的半導體裝置，進一步包括：至少一個線，其將該第二半導體晶片的該至少一個導電接觸電連接到該第一再分配層，其中該電絕緣層被至少部分地放置在該第二半導體晶片的第一側和該至少一個線上方。
  13. 一種半導體裝置，包括：具有第一半導體晶片的基層，該第一半導體晶片在該第一半導體晶片的第一側具有至少一個導電接觸，其中該第一半導體晶片係與該基層直接附接；與該第一半導體晶片的該至少一個導電接觸接觸的第一再分配層，其中該第一再分配層延伸到該第一半導體晶片的邊界之外；和具有第一側和第二側的半導體倒裝晶片，該半導體倒裝晶片在該半導體倒裝晶片的第一側具有至少一個導電接觸，至少部分包封該半導體倒裝晶片的電絕緣層，其中該 電絕緣層具有暴露該第一再分配層的至少一個通孔；和其中該第一半導體晶片的第一側面向該半導體倒裝晶片的第一側。
  14. 如申請專利範圍第13項的半導體裝置，進一步包括：第二再分配層，其穿過該至少一個通孔和該第一再分配層被電連接到該半導體倒裝晶片的該至少一個導電接觸。
  15. 一種用於製作半導體裝置的方法，所述方法包括：在具有第一半導體晶片的基層的表面上形成第一再分配層，該第一半導體晶片在該第一半導體晶片的第一側具有至少一個導電接觸，其中該第一再分配層與該第一半導體晶片的該至少一個導電接觸接觸，其中該第一半導體晶片係與該基層直接附接；至少部分地在該第一再分配層的表面上施加黏合劑層；在該黏合劑層上放置第二半導體晶片；在該第二半導體晶片的周圍施加聚合體層；形成穿過該聚合體層的至少一個通孔，其中該至少一個通孔暴露該第一再分配層；在該聚合體層的表面上形成第二再分配層；形成至少部分包封該第二半導體晶片的電絕緣層；以及 形成穿過該絕緣層的至少一個通孔，其中該至少一個通孔暴露該第一再分配層。
  16. 如申請專利範圍第15項的方法，其中該第二半導體晶片在該第二半導體晶片的第一側具有至少一個導電接觸，並且其中放置該第二半導體晶片包括：在該黏合劑層上放置該第二半導體晶片的第二側，該第二側與該第一側不同。
  17. 如申請專利範圍第16項的方法，進一步包括：在該電絕緣層上形成第二分配層，其中該第二再分配層透過該至少一個通孔將該第二半導體晶片的該至少一個導電接觸電連接到該第一再分配層。
  18. 如申請專利範圍第17項的方法，進一步包括：將至少一個焊球放置在該第二再分配層上。
  19. 如申請專利範圍第17項的方法，進一步包括：至少部分地在該第二再分配層的表面上施加第二黏合劑層；將第三半導體晶片放置在該第二黏合劑層上；形成至少部分包封該第三半導體晶片的第二電絕緣層；形成穿過該第二絕緣層的至少一個通孔，其中該第二絕緣層的該至少一個通孔暴露該第二再分配層；以及在該第二電絕緣層上形成第三再分配層，其中該第三再分配層透過該第二絕緣層的該至少一個通孔將該第三半導體晶片的至少一個導電接觸電連接到該第二再分配層。
  20. 如申請專利範圍第15項的方法，進一步包括：研磨該基層以去除多餘材料。
  21. 如申請專利範圍第15項的方法，其中該基層是重構晶圓並且其中該第一半導體晶片被嵌入在該重構晶圓中。
  22. 如申請專利範圍第15項的方法，進一步包括：在施加該聚合體層之前，使用線將該第二半導體晶片的至少一個導電接觸電連接到該第一再分配層。
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