TWI582916B - 多晶片封裝結構、晶圓級晶片封裝結構及其製程 - Google Patents

多晶片封裝結構、晶圓級晶片封裝結構及其製程 Download PDF

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TWI582916B
TWI582916B TW104113401A TW104113401A TWI582916B TW I582916 B TWI582916 B TW I582916B TW 104113401 A TW104113401 A TW 104113401A TW 104113401 A TW104113401 A TW 104113401A TW I582916 B TWI582916 B TW I582916B
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Taiwan
Prior art keywords
wafer
contacts
conductive bumps
wafers
insulating layer
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TW104113401A
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English (en)
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TW201639092A (zh
Inventor
周世文
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南茂科技股份有限公司
百慕達南茂科技股份有限公司
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Priority to TW104113401A priority Critical patent/TWI582916B/zh
Priority to CN201510392347.XA priority patent/CN106098675B/zh
Priority to US14/855,397 priority patent/US9653429B2/en
Publication of TW201639092A publication Critical patent/TW201639092A/zh
Priority to US15/484,056 priority patent/US9953960B2/en
Application granted granted Critical
Publication of TWI582916B publication Critical patent/TWI582916B/zh

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Description

多晶片封裝結構、晶圓級晶片封裝結構及其製程
本發明是有關於一種封裝結構及製程，且特別是有關於一種多晶片封裝結構、晶圓級晶片封裝結構及其製程。
隨著電子產品的需求朝向高功能化、訊號傳輸高速化及電路元件高密度化，積體電路晶片所呈現的功能也越強大，而針對消費性電子產品，搭配的被動元件數量亦隨之劇增。再者，在電子產品強調輕薄短小之際，如何在有限的構裝空間中容納數目龐大的電子元件，已成為電子構裝業者急待解決與克服的技術瓶頸。為了解決此一問題，構裝技術逐漸走向單構裝系統(System in Package,SIP)的系統整合階段，特別是多晶片模組(Multi-Chip Module,MCM)的構裝。
以多晶片封裝結構為例，主要是將第一晶片以面對面(face-to-face)的方式配置於一第二晶片上，並藉由導電凸塊作為晶 片之間電性連接的媒介，且上述第二晶片則會藉由凸塊或打線(wire bonding)的方式與線路板電性連接。
在此類封裝結構中，由於晶片上的空間日益狹窄，當第一晶片與第二晶片的尺寸接近時，第一晶片邊緣會相當靠近第二晶片上用以連接至線路板的導電凸塊。因此，當在填充第一晶片與第二晶片之間填入底填膠時，底填膠容易溢流至第二晶片上用以連接至線路板的導電凸塊之銲墊上，進而影響了第二晶片與線路板之間電性連接的可靠度。
本發明提供一種多晶片封裝結構，其具有可阻擋底填膠溢流的阻擋結構。
本發明提供一種晶圓級晶片封裝結構，其可切割出多個上述的多晶片封裝結構。
本發明提供一種晶圓級晶片封裝結構製程，其可製作出上述的晶圓級晶片封裝結構。
本發明的一種多晶片封裝結構，包括一第一晶片、至少一阻擋結構、多個第一導電凸塊、一第二晶片、多個第二導電凸塊及一底填膠。第一晶片具有一晶片接合區、多個位於晶片接合區內的第一內接點以及多個位於晶片接合區外之第一外接點。阻擋結構配置於第一晶片的晶片結合區以外的區域上，位於這些第一內接點與這些第一外接點之間，且環繞這些第一內接點。這些 第一導電凸塊配置於這些第一外接點上。第二晶片覆置於(flip on)晶片接合區上，且第二晶片具有多個第二接點。這些第二導電凸塊位於這些第一內接點與該些第二接點之間，各第一內接點分別透過對應的第二導電凸塊與對應的第二接點電性連接。底填膠位於第一晶片與第二晶片之間以包覆這些第二導電凸塊。
本發明的一種晶圓級晶片封裝製程，包括下列步驟：提供一晶圓，晶圓包括多個陣列排列的第一晶片以及對應於這些第一晶片的多個阻擋結構，其中各第一晶片分別具有一晶片接合區、多個位於晶片接合區內的第一內接點以及多個位於晶片接合區外之第一外接點，其中各阻擋結構配置於對應的第一晶片的晶片結合區以外的區域上，位於這些第一內接點與這些第一外接點之間，且環繞這些第一內接點。於這些第一外接點上形成多個第一導電凸塊。提供多個第二晶片，各第二晶片分別具有多個第二接點，且這些第二接點上形成有多個第二導電凸塊。將這些第二晶片覆設於這些晶片接合區上，以使這些第二導電凸塊位於這些第一內接點與這些第二接點之間，且各第一內接點分別透過對應的第二導電凸塊而與對應的第二接點電性連接。於第一晶片與第二晶片之間形成一底填膠，以包覆這些第二導電凸塊。
本發明的一種晶圓級晶片封裝結構，包括一晶圓、多個第一導電凸塊、多個第二晶片、多個第二導電凸塊及一底填膠。晶圓包括多個陣列排列的一第一晶片以及對應於這些第一晶片的多個阻擋結構，各第一晶片具有一晶片接合區、多個位於晶片接 合區內的第一內接點及多個位於晶片接合區外之第一外接點，其中各阻擋結構配置於對應的第一晶片的晶片結合區以外的區域上，位於這些第一內接點與這些第一外接點之間，且環繞這些第一內接點。這些第一導電凸塊配置於這些第一外接點上。這些第二晶片覆置於這些晶片接合區上，且各第二晶片具有多個第二接點。這些第二導電凸塊位於這些第一內接點與這些第二接點之間，各第一內接點分別透過對應的第二導電凸塊與對應的第二接點電性連接。底填膠位於這些第一晶片與這些第二晶片之間以包覆這些第二導電凸塊。
基於上述，本發明的多晶片封裝結構藉由將阻擋結構配置於第一晶片的晶片結合區以外的區域，且於第一內接點與第一外接點之間，並環繞第一內接點，來阻隔第一晶片與第二晶片之間的底填膠向外流至第一導電凸塊，以避免影響到第一導電凸塊與線路板之間的電性連接品質。本發明更提供能切割出多個上述的多晶片封裝結構的晶圓級晶片封裝結構以及其製程。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
12‧‧‧介質金屬層
14‧‧‧光阻層
100‧‧‧多晶片封裝結構
110‧‧‧第一晶片
112‧‧‧晶片接合區
114‧‧‧第一內接點
116‧‧‧第一外接點
120‧‧‧阻擋結構
122‧‧‧金屬層
130‧‧‧第一導電凸塊
135‧‧‧第二導電凸塊
140‧‧‧第二晶片
142‧‧‧第二接點
150‧‧‧底填膠
160‧‧‧第一絕緣層
170‧‧‧重佈線路層
180‧‧‧第二絕緣層
182‧‧‧第一部分
184‧‧‧第二部分
186a、186b‧‧‧間隙
190‧‧‧線路板
200‧‧‧晶圓級晶片封裝結構
202‧‧‧晶圓
300‧‧‧晶圓級晶片封裝製程
310-370‧‧‧步驟
圖1是依照本發明的一實施例的一種多晶片封裝結構的示意圖。
圖2是隱藏圖1的多晶片封裝結構的線路板的上視示意圖。
圖3是依照本發明的一實施例的一種晶圓級晶片封裝結構的示意圖。
圖4至圖12是製造本發明的一實施例的一種晶圓級晶片封裝結構的局部剖面示意圖。
圖13是依照本發明的一實施例的一種晶圓級晶片封裝製程的流程圖。
圖1是依照本發明的一實施例的一種多晶片封裝結構的示意圖。請參閱圖1，本實施例的多晶片封裝結構100包括一第一晶片110、至少一阻擋結構120、多個第一導電凸塊130、多個第二導電凸塊135、一第二晶片140、一底填膠150、一第一絕緣層160、一重佈線路層170、一第二絕緣層180及一線路板190。
第一晶片110具有一晶片接合區112、多個位於晶片接合區112內的第一內接點114以及多個位於晶片接合區112外之第一外接點116。第一絕緣層160配置於第一晶片110上並且暴露出這些第一內接點114以及這些第一外接點116。重佈線路層170配置於第一絕緣層160上並與這些第一內接點114電性連接。第二絕緣層180覆蓋於第一絕緣層160以及重佈線路層170上以暴露出部分的重佈線路層170以及這些第一外接點116。
在本實施例中，第一晶片110的尺寸大於第二晶片140 的尺寸，尺寸較小的第二晶片140倒置覆設於尺寸較大的第一晶片110的晶片接合區112上。第二晶片140具有多個第二接點142。第二導電凸塊135位於第一晶片110的第一內接點114與第二晶片140的第二接點142之間。第一晶片110的第一內接點114透過重佈線路層170、對應的第二導電凸塊135與第二晶片140的上對應的第二接點142電性連接，以使第一晶片110與第二晶片140電性連接。
底填膠(underfill)150位於第一晶片110與第二晶片140之間以包覆這些第二導電凸塊135。底填膠150之材質例如為環氧樹脂(Epoxy)等材料底填膠150可用來提供第一晶片110與第二晶片140之間的固定及密封效果，並能夠提供緩衝及防潮防塵等效果來提昇多晶片封裝結構100的可靠度。
第一導電凸塊130配置於第一晶片110的第一外接點116上，第一晶片110能夠藉由第一導電凸塊130而與線路板190電性連接。在本實施例中，由於第二晶片140與第二導電凸塊135位於線路板190與第一晶片110之間，第一導電凸塊130的高度會大於第二導電凸塊135的高度。更進一步地說，第一導電凸塊130的高度會大於第二導電凸塊135與第二晶片140的總高度。
本實施例的多晶片封裝結構100在製作時會先將第二晶片140倒置覆設並電性連接於第一晶片110，在第一晶片110與第二晶片140之間填入底填膠150，再將第一晶片110透過第一導電凸塊130連接至線路板190，以使第一晶片110、第二晶片140與 線路板190三者之間電性連接。如圖1所示，由於第一晶片110與第二晶片140的尺寸接近，當底填膠150被填入第一晶片110與第二晶片140之間的部位時，底填膠150可能會往外流動而接觸到第一導電凸塊130。
為了避免第一導電凸塊130被底填膠150沾附而影響到之後連接至與線路板190之間的連接能力，在本實施例中，將阻擋結構120配置於第一晶片110的晶片結合區112以外的區域上，且阻擋結構120的所在位置對應於第一內接點114與第一外接點116之間的位置。更詳細地說，阻擋結構120配置在第一絕緣層160上，且在第一導電凸塊130與第二導電凸塊135之間的位置。
在本實施例中，第二絕緣層180包括位於中央的一第一部分182以及環繞第一部分182的一第二部分184，第二絕緣層180的第一部分182覆蓋重佈線路層170上並且暴露出部分的重佈線路層170。第一部分182與第二部分184之間維持一間隙186a，並且，於該第一導電凸塊130與阻擋結構120之間存在第二道間隙186b，阻擋結構120位於兩道間隙186a、186b之間，以形成一獨立凸出之結構。
阻擋結構120包括一金屬層122，第二絕緣層180的第二部分184覆蓋金屬層122。也就是說，在本實施例中，金屬層122與第二絕緣層180的第二部分184共同形成阻擋結構120，由於該第二絕緣層180之第二部份184包覆了一層金屬層122，因此可做為阻擋結構120之補強結構。當然，在其他實施例中，也可以僅 由第二絕緣層180的第二部分184作為阻擋結構120而無需再多一層金屬層122亦可達到相同之阻隔效果，阻擋結構120的材質、形狀與樣式並不以上述為限制。
圖2是隱藏圖1的多晶片封裝結構的線路板的上視示意圖。如圖1與圖2所示，阻擋結構120位於第一導電凸塊130與第二導電凸塊135之間，當底填膠150填充至第一晶片110與第二晶片140之間以包覆第二導電凸塊135時，底填膠150會填充於間隙186a，阻擋結構120凸起於第一絕緣層160上，而形成了立體障礙，換句話說，底填膠150會被阻擋結構120圍繞，有效地阻擋底填膠150向外溢流至第一導電凸塊130的機率。因此，第一導電凸塊130便不會被底填膠150污染，而影響了與線路板190連接的品質。在本實施例中，第一導電凸塊130與阻擋結構120之間還存在第二道間隙186b，當作第二道防護，即便底填膠150過多而使部分的底填膠150未被阻擋結構120阻擋，位在外側的第二道間隙186b可供此部分的底填膠150填入，而避免汙染第一導電凸塊130。
需說明的是，在本實施例中，阻擋結構120為一連續的環形凸起結構，但在其他實施例中，阻擋結構120也可以是配置在第一導電凸塊130與第二導電凸塊135之間的多條不連續的凸起結構。其凸起之高度於本圖式係繪製與第一部分182高度等高，於實施上，其凸起高度亦可略高於第一部分182之高度，阻擋結構120的實際形狀及高度並不以上述為限制，只要能夠降低底填 膠150向外溢流至第一導電凸塊130的機率即可。
在上面的實施例中，阻擋結構120是實施在晶片堆疊在晶片(Chip on Chip,COC)的封裝階段中，但在其他實施例中，阻擋結構120也可以製作在晶片堆疊在晶圓(Chip on Wafer,COW)的封裝階段。圖3是依照本發明的一實施例的一種晶圓級晶片封裝結構的示意圖。請參閱圖3，在晶圓202被切割之前，將上述的阻擋結構120、第一導電凸塊130、第二導電凸塊135、第二晶片140、線路板160等元件配置在晶圓202上，而形成晶圓級晶片封裝結構200。此晶圓級晶片封裝結構200可切割成多個上述的多晶片封裝堆疊結構100。
下面將以圖3的晶圓級晶片封裝結構200為例，詳細地介紹晶圓級晶片封裝結構200的其中一種晶圓級晶片封裝製程。圖4至圖12是製造本發明的一實施例的一種晶圓級晶片封裝結構的局部剖面示意圖。圖13是依照本發明的一實施例的一種晶圓級晶片封裝製程的流程圖。需說明的是，為了清楚顯示各元件的細節，圖4至圖12僅繪示出晶圓級晶片封裝結構200在製作過程之中的局部區域。更精確地說，圖4至圖12僅繪示出晶圓級晶片封裝結構200的其中一個多晶片封裝結構100的製作過程。並且，為了方便了解，圖4至圖12中所呈現的視角是以圖3的A-A線段的剖面來繪示。此外，在本實施例中，相似或相同的元件以與前一實施例相同的元件編號來表示。
本實施例的晶圓級晶片封裝製程300包括下列步驟：首 先，如圖13的步驟310所述以及配合圖4至圖12所示，提供一晶圓202，晶圓202包括多個陣列排列的第一晶片110以及對應於這些第一晶片110的多個阻擋結構120，其中各第一晶片110分別具有一晶片接合區112、多個位於晶片接合區112內的第一內接點114以及多個位於晶片接合區112外之第一外接點116，其中各阻擋結構120配置於對應的第一晶片110的晶片結合區112以外的區域上，位於這些第一內接點114與這些第一外接點116之間，且環繞這些第一內接點114。
詳細地說，請先參考圖4，晶圓202包括多個第一晶片110，第一晶片110具有一晶片接合區112、多個位於晶片接合區112內的第一內接點114以及多個位於晶片接合區112外之第一外接點116。一開始可選擇性地對晶圓202進行清洗(Incoming Clean)的步驟，透過例如是高壓水柱清洗的方式來移除第一晶片110表面的髒污。當然，在其他實施例中，也可以選擇不對晶圓202進行清洗。
接著，如圖5所示，在第一晶片110上形成圖案化的一第一絕緣層160。詳細地說，可先在第一晶片110上塗佈一絕緣層，該絕緣層之材料可為一般之感光性光阻材料、聚醯亞胺(PI)層或是氮化矽(silicon nitride,Si3N4)，再罩設一光罩(未繪示)在絕緣層上，並且進行曝光(Exposure)的程序，其中光罩的圖案對應於所欲露出的第一晶片的圖案。之後進行顯影(Develop)的程序，以顯影液將未曝光的絕緣層溶解並移除。接著，透過加熱的方式固化 (Curing)未被移除的絕緣層，再透過例如是氧氣電漿的方式對固化的絕緣層進行表面處理，即可完成第一絕緣層160。如圖5所示，第一絕緣層160配置於這些第一晶片110上並且暴露出這些第一內接點114以及這些第一外接點116。
再來，如圖6所示，沉積一介質金屬層(UBM Deposition)12。在本實施例中，先透過氬氣去移除第一絕緣層160、第一內接點114與第一外接點116上的氧化物。接著，在第一絕緣層160、第一內接點114與第一外接點116上依序濺鍍鈦鎢層、金層與鈦層，以形成介質金屬層12。
接著，如圖7及圖8所示，形成圖案化的一光阻層14、一重佈線路層170與一金屬層122。詳細地說，在本實施例中，先在圖6的介質金屬層12上塗佈光阻材料，再進行曝光的程序。使光阻層14上對應於第一內接點114與第一外接點116之區域形成開孔後再進行一道電鍍製程，而於該曝露的開孔中形成重佈線路層170與金屬層122。接著，移除光阻層14及未被重佈線路層170與金屬層122覆蓋之介質金屬層12，而留下了重佈線路層170與金屬層122。如圖8所示，重佈線路層170配置於第一絕緣層160上並與這些第一內接點114電性連接。
其後，如圖9所示，形成圖案化的一第二絕緣層180。在本實施例中，第二絕緣層180的材質例如為聚醯亞胺，如同第一絕緣層160的形成方式，透過曝光顯影等步驟形成第二絕緣層180，且第二絕緣層180覆蓋於第一絕緣層160以及重佈線路層170 上，並暴露出部分的重佈線路層170以及這些第一外接點116。在本實施例中，第二絕緣層180包括一第一部分182以及一第二部分184，且第一部分182與第二部分184之間維持一間隙186a，於另一實施例中，亦可於該第一導電凸塊130與阻擋結構120之間，進一步形成第二道間隙186b，使該阻擋結構120位於兩道間隙186a、186b之間，以形成一獨立凸出之結構。形成間隙186a,186b的方法包括黃光製程、雷射加工或反應離子蝕刻(RIE)。第一部分182覆蓋重佈線路層170上並且暴露出部分的重佈線路層170，而第二部分184覆蓋一單獨之金屬層122，而與金屬層122共同形成阻擋結構120。值得一提的是，該阻擋結構120之高度如需再進一步增加時，可於該第二部分182上進一步塗覆一層與第二絕緣層180材質相同之材料，即可增加該阻擋結構120之高度。在本實施例中，透過圖4至圖9的程序完成了步驟310。
再來，如圖10所示，於這些第一外接點116上形成多個第一導電凸塊130(步驟320)，形成的方式可包括植球、電鍍、印刷等方式後再加熱迴焊。
接著，如圖11所示，提供第二晶片140，第二晶片140具有多個第二接點142，且這些第二接點142上形成有多個第二導電凸塊135(步驟330)。第一導電凸塊130與第二導電凸塊135的材質包括單一金屬元素或合金，其材質可為含鉛材料(例如鉛或錫鉛合金)或無鉛材料，其包括金、銀、銅、錫、鎳或其合金，於本發明圖式中，係列舉為球狀為例，然而，其外觀形狀不僅可 成型為球狀、圓柱狀或圓頂柱狀，其所選用之材料亦可採用單一種金屬材料或採用兩種或兩種以上之金屬材料電鍍成型，例如，銅柱(Copper Pillar)上形成一層錫(Solder Cap)，或銅凸塊外壁覆蓋一層金..等等，均為本發明可行之導電凸塊。
再者，將第二晶片140覆設於晶片接合區112上，以使這些第二導電凸塊135位於這些第一內接點114與這些第二接點142之間，且各第一內接點114分別透過對應的第二導電凸塊135而與對應的第二接點142電性連接(步驟340)，其中這些第二導電凸塊135透過重佈線路層170與這些第一內接點114電性連接。接著，於第一晶片110與第二晶片140之間形成一底填膠150，以包覆這些第二導電凸塊135(步驟350)。如圖11所示，在本實施例中，底填膠150會向外流而填充於間隙186a，且被阻擋結構120阻擋。因此，第一導電凸塊130便不會被底填膠150污染，而影響了與線路板190連接的品質。在本實施例中，第一導電凸塊130與阻擋結構120之間還存在第二道間隙186b，當作第二道防護，即便底填膠150過多而使部分的底填膠150未被阻擋結構120阻擋，此部分的底填膠150仍可流入位在外側的第二道間隙186b內，而避免汙染第一導電凸塊130。
最後，如圖12所示，進行一晶圓切割步驟，以使這些第一晶片110彼此分離而形成多個多晶片封裝結構100(步驟360)，接下來，再使這些單離化之多晶片封裝結構以第一導電凸塊130電性連接至一線路板190，其中第二晶片140、這些第一導電凸塊 130以及這些第二導電凸塊135位於線路板190與第一晶片110之間(步驟370)。在本實施例的步驟340與步驟370中，可透過一加熱升溫程序，例如是迴焊作業來使第二導電凸塊135連接至重佈線路層170以及第一導電凸塊130連接至線路板190。值得一提的是，該迴焊作業可針對該第一導電凸塊130與第二導電凸塊135同時加熱迴焊，亦可先就第二導電凸塊135迴焊連接於第一晶片110上，再進行第二次迴焊作業，使第一導電凸塊130連接於線路板160上，於實施作業上該迴焊作業可隨製程不同而作調整。
再次說明的是，圖4至圖12僅繪示出晶圓級晶片封裝結構200的其中一部分，因此，在圖12中顯示出一個多晶片封裝結構100，實際上，若以圖3的角度觀之，則可切割出多個如圖12所示的多晶片封裝結構100。
此外，雖然在本實施例中是先在這些第一外接點116上形成多個第一導電凸塊130(步驟320)之後，再將第二晶片140覆設於晶片接合區112上(步驟330、340)。但在其他實施例中，也可以是先將第二晶片140覆設於晶片接合區112上，以使第二導電凸塊135連接至第一內接點114(步驟330、340)，之後，在這些第一外接點116上形成多個第一導電凸塊130(步驟320)，製程順序上可視需求而調整。
綜上所述，本發明的多晶片封裝結構與晶圓級晶片封裝結構藉由將阻擋結構配置於第一晶片上，且阻擋結構的位置對應於第一內接點與第一外接點之間並環繞第一內接點的位置，來阻 隔第一晶片與第二晶片之間的底填膠向外流至第一導電凸塊，以避免影響到第一導電凸塊與線路板之間的電性連接品質。本發明更提供上述晶圓級晶片封裝結構的製程，而能夠製作出底填膠不會流至第一導電凸塊的晶圓級晶片封裝結構。並且，此晶圓級晶片封裝結構透過晶圓切割程序，便可形成多個上述的多晶片封裝結構。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧多晶片封裝結構
110‧‧‧第一晶片
112‧‧‧晶片接合區
114‧‧‧第一內接點
116‧‧‧第一外接點
120‧‧‧阻擋結構
122‧‧‧金屬層
130‧‧‧第一導電凸塊
135‧‧‧第二導電凸塊
140‧‧‧第二晶片
142‧‧‧第二接點
150‧‧‧底填膠
160‧‧‧第一絕緣層
170‧‧‧重佈線路層
180‧‧‧第二絕緣層
182‧‧‧第一部分
184‧‧‧第二部分
186a、186b‧‧‧間隙
190‧‧‧線路板

Claims (19)

  1. 一種多晶片封裝結構，包括：一第一晶片，具有一晶片接合區、多個位於該晶片接合區內的第一內接點以及多個位於該晶片接合區外之第一外接點；至少一阻擋結構，配置於該第一晶片的該晶片結合區以外的區域上，且於該些第一內接點與該些第一外接點之間，並環繞該些第一內接點；多個第一導電凸塊，配置於該些第一外接點上；一第二晶片，覆置於(flip on)該晶片接合區上，且該第二晶片具有多個第二接點；多個第二導電凸塊，位於該些第一內接點與該些第二接點之間，各該第一內接點分別透過對應的該第二導電凸塊與對應的該第二接點電性連接；一底填膠，位於該第一晶片與該第二晶片之間以包覆該些第二導電凸塊；一第一絕緣層，配置於該第一晶片上並且暴露出該些第一內接點以及該些第一外接點；一重佈線路層，配置於該第一絕緣層上並與該些第一內接點電性連接；以及一第二絕緣層，覆蓋於該第一絕緣層以及該重佈線路層上以暴露出部分的該重佈線路層以及該些第一外接點，其中該些第二導電凸塊透過該重佈線路層與該些第一內接點電性連接，其中該 第二絕緣層包括一第一部分以及一第二部分，該第一部分覆蓋該重佈線路層上並且暴露出部分的該重佈線路層，而該第二部分為該阻擋結構的至少其中一部分，且該第一部分與該第二部分之間維持一間隙。
  2. 如申請專利範圍第1項所述的多晶片封裝結構，其中該第一晶片的尺寸大於該第二晶片的尺寸。
  3. 如申請專利範圍第1項所述的多晶片封裝結構，其中該第二部分與該第一導電凸塊之間還具有一道間隙。
  4. 如申請專利範圍第1項所述的多晶片封裝結構，更包括一線路板，其中該線路板與該些第一導電凸塊電性連接，且該第二晶片、該些第一導電凸塊以及該些第二導電凸塊位於該線路板與該第一晶片之間。
  5. 如申請專利範圍第1項所述的多晶片封裝結構，其中各該第一導電凸塊的高度大於各該第二導電凸塊的高度。
  6. 如申請專利範圍第1項所述的多晶片封裝結構，其中該阻擋結構包括一金屬層。
  7. 一種晶圓級晶片封裝製程，包括：提供一晶圓，該晶圓包括多個陣列排列的第一晶片、對應於該些第一晶片的多個阻擋結構、一第一絕緣層、一重佈線路層以及一第二絕緣層，其中各該第一晶片分別具有一晶片接合區、多個位於該晶片接合區內的第一內接點以及多個位於該晶片接合區外之第一外接點，其中各該阻擋結構配置於對應的該第一晶片的 該晶片結合區以外的區域上，且於該些第一內接點與該些第一外接點之間，並環繞該些第一內接點，其中該第一絕緣層配置於該些第一晶片上並且暴露出該些第一內接點以及該些第一外接點，其中該重佈線路層配置於該第一絕緣層上並與該些第一內接點電性連接，其中該第二絕緣層覆蓋於該第一絕緣層以及該重佈線路層上以暴露出部分的該重佈線路層以及該些第一外接點，其中該第二絕緣層包括一第一部分以及一第二部分，該第一部分覆蓋該重佈線路層上並且暴露出部分的該重佈線路層，而該第二部分為該阻擋結構的至少其中一部分，且該第一部分與該第二部分之間維持一間隙；於該些第一外接點上形成多個第一導電凸塊；提供多個第二晶片，各該第二晶片分別具有多個第二接點，且該些第二接點上形成有多個第二導電凸塊，其中該些第二導電凸塊透過該重佈線路層與該些第一內接點電性連接；將該些第二晶片覆設於該些晶片接合區上，以使該些第二導電凸塊位於該些第一內接點與該些第二接點之間，且各該第一內接點分別透過對應的該第二導電凸塊而與對應的該第二接點電性連接；以及於該第一晶片與該第二晶片之間形成一底填膠，以包覆該些第二導電凸塊。
  8. 如申請專利範圍第7項所述的晶圓級晶片封裝製程，其中各該第一晶片的尺寸大於各該第二晶片的尺寸。
  9. 如申請專利範圍第7項所述的晶圓級晶片封裝製程，其中將該些第二晶片覆設於該些晶片接合區之前，於該些第一外接點上形成該些第一導電凸塊。
  10. 如申請專利範圍第7項所述的晶圓級晶片封裝製程，其中在該些第一外接點上形成該些第一導電凸塊之後，將該些第二晶片覆設於該些晶片接合區上。
  11. 如申請專利範圍第7項所述的晶圓級晶片封裝製程，更包括：使該些第一導電凸塊電性連接至一線路板，其中該第二晶片、該些第一導電凸塊以及該些第二導電凸塊位於該線路板與該第一晶片之間。
  12. 如申請專利範圍第7項所述的晶圓級晶片封裝製程，其中各該第一導電凸塊的高度大於各該第二導電凸塊的高度。
  13. 如申請專利範圍第7項所述的晶圓級晶片封裝製程，更包括進行一迴焊作業，以使該些第二晶片透過該些第二導電凸塊以與該些第一內接點電性連接。
  14. 如申請專利範圍第7項所述的晶圓級晶片封裝製程，更包括進行一晶圓切割步驟，以使該些第一晶片彼此分離而形成多個多晶片封裝結構。
  15. 一種晶圓級晶片封裝結構，包括：一晶圓，包括多個陣列排列的一第一晶片以及對應於該些第一晶片的多個阻擋結構，各該第一晶片具有一晶片接合區、多個 位於該晶片接合區內的第一內接點及多個位於該晶片接合區外之第一外接點，其中各該阻擋結構配置於對應的該第一晶片的該晶片結合區以外的區域上，且於該些第一內接點與該些第一外接點之間，並環繞該些第一內接點；多個第一導電凸塊，配置於該些第一外接點上；多個第二晶片，覆置於該些晶片接合區上，且各該第二晶片具有多個第二接點；多個第二導電凸塊，位於該些第一內接點與該些第二接點之間，各該第一內接點分別透過對應的該第二導電凸塊與對應的該第二接點電性連接；一底填膠，位於該些第一晶片與該些第二晶片之間以包覆該些第二導電凸塊；一第一絕緣層，配置於該第一晶片上並且暴露出該些第一內接點以及該些第一外接點；一重佈線路層，配置於該些第一絕緣層上並與該些第一內接點電性連接；以及一第二絕緣層，覆蓋於該第一絕緣層以及該重佈線路層上以暴露出部分的該重佈線路層以及該些第一外接點，其中該些第二導電凸塊透過該重佈線路層與該些第一內接點電性連接，其中該第二絕緣層包括一第一部分以及一第二部分，該第一部分覆蓋該重佈線路層上並且暴露出部分的該重佈線路層，而該第二部分為該阻擋結構的至少其中一部分，且該第一部分與該第二部分之間 維持一間隙。
  16. 如申請專利範圍第15項所述的晶圓級晶片封裝結構，其中該第一晶片的尺寸大於該第二晶片的尺寸。
  17. 如申請專利範圍第15項所述的晶圓級晶片封裝結構，其中該第二部分與該第一導電凸塊之間還具有一道間隙。
  18. 如申請專利範圍第15項所述的晶圓級晶片封裝結構，其中各該第一導電凸塊的高度大於各該第二導電凸塊的高度。
  19. 如申請專利範圍第15項所述的晶圓級晶片封裝結構，其中該些阻擋結構包括金屬層。
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