CN103545288A - 堆叠的扇出半导体芯片 - Google Patents

堆叠的扇出半导体芯片 Download PDF

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Publication number
CN103545288A
CN103545288A CN201310293408.8A CN201310293408A CN103545288A CN 103545288 A CN103545288 A CN 103545288A CN 201310293408 A CN201310293408 A CN 201310293408A CN 103545288 A CN103545288 A CN 103545288A
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China
Prior art keywords
semiconductor chip
redistribution layer
semiconductor
chip
layer
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CN201310293408.8A
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English (en)
Inventor
T.迈耶
G.奥夫纳
S.阿尔贝尔斯
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Infineon Technologies AG
Intel Deutschland GmbH
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Infineon Technologies AG
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Publication of CN103545288A publication Critical patent/CN103545288A/zh
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Abstract

本发明涉及堆叠的扇出半导体芯片。描述了堆叠的半导体器件以及制作堆叠的半导体器件的方法。所述半导体器件可包括具有多个嵌入的半导体芯片的重构基层。第一再分配层可以接触所述嵌入芯片的导电接触并且延伸到所述嵌入芯片的一个或多个的边界之外，形成扇出区域。另一个芯片可以被堆叠在嵌入在所述基层中的芯片的上面并且通过第二再分配层被电连接到所述嵌入芯片。在所述半导体器件中可包括芯片的另外的层。

Description

堆叠的扇出半导体芯片
技术领域
本申请涉及一种堆叠的扇出半导体芯片。
背景技术
存在几种用于堆叠半导体芯片的方法。在线结合堆叠中，一个芯片可以被堆叠到另一个芯片上，并且两个芯片之间的电接触可以通过线结合产生。这些线结合堆叠可能具有大的维度和受限的电性能。在倒装芯片线结合堆叠中，焊料凸块可以被放置在芯片的顶侧，并且所述芯片可以被倒装，使得所述顶侧（具有所述焊料凸块）可以接触置于衬底上的电接触。然后线结合芯片可以被附着到倒装芯片的底部，形成堆叠。堆叠在所述封装上的另外的芯片会需要线结合，产生大的封装尺寸和受限的电性能。在直通硅通孔（TSV）芯片堆叠中，通孔可延伸（从芯片的有源侧）穿过所述芯片以提供到所述芯片无源侧的电连接。然而，TSV技术是昂贵的并且用于TSV芯片的供应链仍在开发。需要的是潜在地较不贵并且产生可相对地小并可具有极好电性能的芯片封装的芯片堆叠技术。
发明内容
在一些方面中，由芯片堆叠技术形成的半导体器件可包括多个层，包括：具有第一半导体芯片的基层，所述第一半导体芯片在所述第一半导体芯片的第一侧具有至少一个导电接触，接触所述第一半导体芯片的所述至少一个导电接触的第一再分配层，其中第一再分配层可延伸到所述第一半导体芯片的边界之外，具有第一侧和第二侧的第二半导体芯片，所述第二半导体芯片在所述第二半导体芯片的第一侧具有至少一个导电接触，以及放置在所述第一半导体芯片的第一侧和所述第二半导体芯片的第二侧之间的粘合剂层，其中所述第二半导体芯片可直接被放置在所述粘合剂层上。
所述半导体器件可进一步包括：至少部分地放置在所述第二半导体芯片的第一侧上方的电绝缘层，其中所述电绝缘层可具有暴露所述第一再分配层的至少一个通孔，以及接触所述第二半导体芯片的所述至少一个导电接触的第二再分配层，其中所述第二再分配层可通过所述至少一个通孔被电连接到所述第一再分配层。至少一个焊球可接触所述第二再分配层。
所述半导体器件可具有多个层。例如，所述半导体器件可包括：具有第一侧和第二侧的第三半导体芯片，所述第三半导体芯片具有在所述第三半导体芯片的第一侧的至少一个导电接触，放置在第二半导体芯片的第一侧和第三半导体芯片的第二侧之间的第二粘合剂层，其中所述第三半导体芯片可被直接放置在所述第二粘合剂层上，至少部分地放置在第三半导体芯片的第一侧上方的第二电绝缘层，其中第二电绝缘层可具有暴露所述第二再分配层的至少一个通孔，以及接触所述第三半导体芯片的所述至少一个导电接触的第三再分配层，其中所述第三再分配层可通过所述第二电绝缘层的至少一个通孔被电连接到所述第二再分配层。
在一些方面中，半导体器件的基层可以是重构晶片，并且所述第一半导体芯片可被嵌入在所述重构晶片中。多个半导体芯片也可被嵌入在所述重构晶片中。所述多个半导体芯片可包括至少一个无源半导体芯片和至少一个有源半导体芯片。
所述半导体器件的所述第一半导体芯片和第二半导体芯片可形成单个集成电路封装。在一些方面中，第二半导体芯片可以是在不损坏所述封装的情况下不可从所述单个集成电路封装释放的。
在另一些方面中，半导体器件的粘合剂层可被至少部分地放置在所述第一再分配层上。所述第一半导体芯片和第二半导体芯片可以是集成电路。
在另外的方面中，所述半导体器件可包括：将所述第二半导体芯片的所述至少一个导电接触电连接到所述第一再分配层的至少一个线，和至少部分地放置在所述第二半导体芯片的第一侧和所述至少一个线的上方的电绝缘层，其中所述电绝缘层可具有暴露所述第一再分配层的至少一个通孔。
在此还描述了一种半导体器件，其具有：具有第一半导体芯片的基层，所述第一半导体芯片在所述第一半导体芯片的第一侧具有至少一个导电接触，接触所述第一半导体芯片的所述至少一个导电接触的第一再分配层，其中第一再分配层可延伸到所述第一半导体芯片的边界之外，具有第一侧和第二侧的半导体倒装芯片，所述半导体倒装芯片在所述半导体倒装芯片的第一侧具有至少一个导电接触。所述第一半导体芯片的第一侧可面向所述半导体倒装芯片的第一侧。所述半导体器件也可包括：至少部分地放置在所述半导体倒装芯片的第二侧上方的电绝缘层，其中所述电绝缘层可具有暴露所述第一再分配层的至少一个通孔，以及穿过所述至少一个通孔和第一再分配层电连接到所述半导体倒装芯片的所述至少一个导电接触的第二再分配层。
用于制作半导体器件的方法也在此被描述。所述方法可包括：在具有第一半导体芯片的基层的表面上形成第一再分配层，所述第一半导体芯片在所述第一半导体芯片的第一侧具有至少一个导电接触，其中所述第一再分配层可接触所述第一半导体芯片的所述至少一个导电接触；至少部分地在所述第一再分配层的表面上施加粘合剂层；在所述粘合剂层上放置第二半导体芯片；在所述第二半导体芯片周围施加聚合体层；形成穿过所述聚合体层的至少一个通孔，其中所述至少一个通孔可暴露所述第一再分配层；以及在所述聚合体层的表面上形成第二再分配层。所述第二半导体芯片可以在所述第二半导体芯片的第一侧具有至少一个导电接触，并且其中放置所述第二半导体芯片可包括将所述第二半导体芯片的第二侧放置在所述粘合剂层上，所述第二侧与所述第一侧不同。所述方法可进一步包括：至少部分地在所述第二半导体芯片的第一侧上形成电绝缘层；以及形成穿过所述绝缘层的至少一个通孔，其中所述至少一个通孔可暴露所述第一再分配层。
在一些方面中，所述方法可进一步包括在电绝缘层上形成第二再分配层，其中所述第二再分配层可通过所述至少一个通孔将所述第二半导体芯片的所述至少一个导电接触电连接到所述第一再分配层。所述方法可进一步包括将至少一个焊球放置在所述第二再分配层上。
所述方法可包括至少部分地在所述第二分配层的表面上施加第二粘合剂层；在所述第二粘合剂层上放置第三半导体芯片；至少部分地在所述第三半导体芯片上形成第二电绝缘层；形成穿过所述第二绝缘层的至少一个通孔，其中所述第二绝缘层的至少一个通孔可暴露所述第二再分配层；以及在所述第二电绝缘层上形成第三再分配层，其中所述第三再分配层可通过所述第二绝缘层的所述至少一个通孔将所述第三半导体芯片的至少一个导电接触电连接到所述第二再分配层。
所述方法可包括研磨所述基层以去除多余材料。在一些方面中，所述基层可以是重构晶片，并且所述第一半导体芯片可以被嵌入在所述重构晶片中。所述方法可以进一步包括在施加所述聚合体层之前，使用线将所述第二半导体芯片的至少一个导电接触电连接到所述第一再分配层。
在考虑下面的详细描述时，本公开的这些以及其它方面将是显而易见的。
附图说明
通过参考下面考虑到附图的描述，可以对本公开以及在此描述的各方面的潜在优点得到更完全的理解，在附图中相似的参考数字表示相似的特征，并且其中：
图1A-1K示出半导体器件（或者其各部分）和/或根据此处描述的一个或多个方面制作半导体器件的实例方法的侧面剖视图的实例。
图2示出根据此处描述的一个或多个方面，半导体器件（或者其部分）的侧面剖视图的另一实例。
图3示出根据此处描述的一个或多个方面，半导体器件（或者其部分）的侧面剖视图的又一实例。
图4A-4E示出根据此处描述的一个或多个方面，具有倒装芯片封装的半导体器件（或者其各部分）和/或制作具有倒装芯片封装的半导体器件的实例方法的侧面剖视图的实例。
图5A-5D示出根据此处描述的一个或多个方面，具有线的半导体器件（或者其各部分）和/或制作具有线的半导体器件的实例方法的侧面剖视图的实例。
图6A-6C示出根据此处描述的一个或多个方面，具有有源和/或无源部件的半导体器件（或者其各部分）和/或制作具有有源和/或无源部件的半导体器件的实例方法的侧面剖视图的实例。
图7示出根据此处描述的一个或多个方面，具有有源和/或无源部件的半导体器件（或者其部分）的侧面剖视图的另一实例。
应该注意到所述附图中的一个或多个可不必要按比例绘制。
具体实施方式
图1A-1K示出半导体器件（或者其各部分）和/或根据此处描述的一个或多个方面制作半导体器件的实例方法的侧面剖视图的实例。在图1A中，可提供基层（衬底层）101。所述基层101可以是重构晶片，例如具有各扇出部分的重构晶片（诸如，晶片级球（WLB）或者嵌入晶片级球（eWLB）晶片）。所述重构晶片可以通过选择多个半导体芯片105（其可以是管芯）形成，作为实例，所述多个半导体芯片105被示为芯片105-1和105-2，其可以已知和/或测试为良好的（例如，起作用的）。所述半导体芯片105可取自由其来形成芯片105的晶片（例如，通过切割硅晶片）并且使用粘合箔被放置到载体上。所述芯片105可以被面朝上地（例如，具有导电（例如，金属）接触106的芯片105的有源侧面朝上）放置在载体上或者面朝下地（例如，具有导电接触106的芯片的有源侧面朝下）放置在载体上以形成第一半导体芯片105层。如果在初始硅晶片中所述芯片105的密度大于所述重构晶片101的所需密度（即，如果在初始硅晶片中芯片105之间的距离小于在基层101中芯片105之间的距离），与所述芯片105在初始硅晶片上相比，从初始硅晶片去除的所述芯片105可以以彼此间更大的距离被放置在载体上。如将在下面的实例中以更多细节被描述的，通过展开所述芯片105，可以形成扇出区域。
可以在所述芯片105的周围形成例如模塑（molding）的电绝缘层103以生成基层101。例如，可以通过压缩模塑生成基层101以生成圆形晶片、矩形晶片，或任何其它形状的晶片。因此，所述半导体芯片105可通过模塑工艺被至少部分地嵌入在所述基层101中。可使用本领域普通技术人员可用的任何方法暴露所述导电接触106。例如，可通过所述绝缘层103的研磨、激光去除、和/或研磨和激光去除的结合将所述接触106暴露。所述基层101可被用作用于堆叠另外的层和/或芯片的起始基础。因此，可以不需要另外的半导体芯片承载系统。
嵌入在所述重构晶片中的半导体芯片105可以包括具有多个导电接触106的第一侧107（在此被称作“顶”侧，不管相对于重力或者相对于所述器件的剩余部分的实际取向）。所述接触106可通过将例如多晶硅和/或金属（诸如，铝）的任何导电材料沉积到半导体芯片105上形成。所述接触106也可被例如铜柱、柱子，或者其它结构的金属结构覆盖（全部地或者部分地）。示例性的金属结构可以是例如7到20μm厚。所述金属结构可以在将层和/或材料从所述半导体芯片去除期间（例如在激光钻孔期间）保护所述接触106。一些层和/或材料去除工艺（例如光刻）可不需要保护所述接触106的金属结构。因此，如将在下面的实例中以更多细节被描述的，如果电绝缘层109通过光刻被构造，金属结构可能不需要覆盖所述接触106。下面描述的所述芯片接触的任何一个可类似地包括覆盖所述接触的金属结构，以在所述层和/或材料去除期间保护它们。所述接触可以已经被形成为用以形成所述初始硅晶片的工艺的一部分。在一些方面中，因为再分配层、无源层、焊料停止（solder stop）、和/或焊球未被形成在所述重构晶片101上，所以所述裸露的接触106不可能是可焊接的。半导体芯片105也可具有可以具有或者可以不具有任何导电接触的第二相对侧108（例如，“底”侧）。
在图1B中，电绝缘层109（例如，电介质）可被形成在所述重构晶片101上。接触106可例如通过使用光刻和/或激光技术被暴露。可以在被暴露的接触106上形成金属化延伸110（其可由铜或者其它导电材料制成）。第一再分配层111可以被形成在所述电介质109的上方。所述第一再分配层111可包括多个再分配线，所述再分配线的至少一些可以延伸到所述一个或多个半导体芯片105的边界之外，在所述芯片105之间的区域中形成扇出区域。通过将所述接触106扇出到每个芯片105的占位空间112的外面，所述接触106可更容易接入（例如，到另外的半导体芯片和/或其它类型的部件，接触，等）。再分配层可以使用各种薄膜和/或印刷电路板（PCB）沉积技术被施加，包括溅射和电镀、无电极种子层施加、电解电镀、印刷、和/或其它沉积工艺。
在图1C中，粘合剂层113可被形成在所述第一半导体芯片105层的上方（诸如，通过印刷、层压、点胶（dispensing）等），例如在所述电介质109上和/或所述第一再分配层111上。所述第一再分配层111的各部分可保持暴露以便于芯片堆叠。例如，如在下面的实例中将以更多细节被描述的，粘合剂可被施加到半导体芯片的第二层的拾取和放置位置。粘合剂可以包括例如环氧树脂、聚酰亚胺、硅树脂、其它材料、以及其结合。此外，所述粘合剂可被填充有例如硅和碳的填充物以及其它类型的填充物，或者未被填充。虽然所述粘合剂层113被示作图案化层，所述粘合剂层113可以是所述芯片105之间的连续层。而且，所述粘合剂层113的边界可在每个所述芯片105的占位空间处或在每个所述芯片105的占位空间内部，或者所述粘合剂层113可以延伸到每个所述芯片105的占位空间之外。
在图1D中，半导体芯片114的第二层（作为实例被示为芯片114-1和114-2）可被直接地放置在所述粘合剂113上。可以使用拾取和放置机。第二半导体芯片114可以均包括具有多个导电接触的第一侧115（例如，顶侧）。可以以与用于半导体芯片105的第一层相同或者相似的方式在所述第二半导体芯片114的接触上形成金属化延伸117（例如，由铜或者其它导电材料制成）。在一些方面中，所述金属化延伸117可以例如以铜凸点下金属化（UBM）的形式被预施加到所述芯片114的接触。所述第二芯片114也可以均具有第二侧116（例如，底侧），所述第二侧可以具有或者可以不具有任何导电接触。所述第二侧116可以被直接放置在所述粘合剂113上。
在图1E中，电绝缘层119（例如模塑层或者层压层）可被形成在所述第二半导体芯片114的周围，使得所述第二芯片114至少部分地嵌入在所述绝缘层119中。所述绝缘层119可以使用例如层压、压缩模塑、印刷等的任何半导体制作工艺步骤被施加。在图1F中，所述绝缘层119可例如通过所述绝缘层的研磨和/或激光钻孔在尺寸上被减小（例如，变薄）。研磨所述绝缘层119（例如，到位置121）可以暴露所述第二半导体芯片114的导电延伸117。
在图1G中，可例如通过钻孔（例如，激光钻孔）和或光刻工艺在所述电绝缘层119中形成一个或多个通孔123（例如，互连路径）。所述通孔123可以暴露所述第二半导体芯片114的导电延伸117和/或所述第一再分配层111。例如，在所述第一再分配层111和/或一个或多个导电延伸117处，所述钻孔可被致使停止。
在图1H中，所述通孔123可被填充有一个或多个导电材料125，例如铜，以允许电接入到所述第一再分配层111和/或所述第二半导体芯片114的导电延伸117。在所述模塑层119的上方也可形成（例如，通过溅射和电镀、无电极种子层电镀、或者电解电镀）第二再分配层127。在一些方面中，可以与所述再分配层127的形成一起来填充所述通孔123。替代地，可以与所述再分配层127的形成分开地填充所述通孔123。例如，所述通孔123可以首先被填充（例如，通过印刷、电解电镀等）。然后，可形成再分配层127。所述通孔123可以完全地或者部分地填充有导电材料。部分地填充的通孔可以是塞紧的通孔，其中再分配类型层通过所述通孔被向下传递，并且如将在下面实例中以更多细节描述的，所述通孔的其余部分被单独填充或者由例如第二电绝缘层129的电绝缘材料填充。所述第二再分配层127可以生成所述第一和第二半导体芯片的导电接触的第二扇出互连。例如，所述接触可以被扇出到每个所述第一半导体芯片105的占位空间的外部，每个所述第二半导体芯片114的占位空间的外部，和/或所述第一和第二半导体芯片105，114两者的占位空间的外部。所述第二再分配层127可以通过将所述导电材料125填充所述至少一个通孔123来被电连接到所述第一再分配层111。所述第二再分配层127可类似地被电连接到所述第二半导体芯片114的一个或多个导电接触。在一些方面中，在所述第二再分配层127和所述第一再分配层111和/或导电延伸117之间的电连接可以不需要任何焊料，潜在地简化了用来生成所述半导体器件的制造工艺和/或潜在地提高了所述半导体器件的鲁棒性（例如，抵抗高温的能力）。
在图1I中，可在所述第二再分配层127上形成第二电绝缘层129（例如，电介质）。所述第二再分配层127可以被暴露在一个或多个位置131（例如，通过激光钻孔、光刻等）。在图1J中，可施加焊料停止层，和/或焊球133（例如，球或者半球）。在图1K中，背向在其上施加（或者将施加）焊球133的侧面的所述基层101的底部（例如，模塑103）可以被研磨以减小所述结构的高度，例如减小到位置135。然后可以在每个堆叠的芯片组和/或每个其它部件之间，例如在图1K中通过虚线示出的位置处，分开（例如，切割）所述结构，产生了多个分开的半导体器件封装。例如，在图1K的实例中示出两个半导体器件封装137-1和137-2，每个所述封装可以具有多个半导体芯片（例如，第一半导体芯片105和第二半导体芯片114）。替代地，参考数字137-1和137-2可以形成单个半导体封装。所述第一半导体芯片105和第二半导体芯片114可能是不可从相应封装137释放的。
图2根据此处描述的一个或多个方面示出半导体器件200（或者其部分）的侧面剖视图的另一实例。可以在所述重构晶片或者任何其它层中嵌入多个半导体芯片（例如，芯片201，203，205和207）和/或其它有源或者无源部件（如将在下面的实例中以更多细节被描述的）。所述实例半导体封装200可以具有非常低的封装高度。例如，所述焊球高度A可以是在200μm到300μm的范围中，例如大约250μm（在焊球之间具有大约0.50mm的间距）。所述焊球高度A可以是在150μm到250μm的范围中，例如大约200μm（具有大约0.40mm的间距）。所述电介质和第二半导体高度B可以是在5μm到40μm的范围中，例如大约30μm。所述第二半导体芯片和第二金属化延伸高度C可以是在20μm到250μm的范围中，例如大约120μm。所述第二金属化高度针对激光钻孔连接可以在10μm到30μm范围中，以及针对其它连接类型可以在5μm到15μm范围中。例如，所述第二半导体芯片可以具有大约100μm的高度，并且所述金属化延伸可以具有大约20μm的高度。在一些方面中，所述第二芯片可以具有甚至更低的高度，例如大约50μm。所述第一介电层、第一再分配层、以及粘合剂高度D可以是大约40μm。所述模塑的（和研磨的）重构晶片高度E可以是大约100μm。因此，具有两个半导体芯片层的三维半导体封装200可以具有大约490μm的总体高度F（或者大约440μm，如果所述第二半导体芯片在高度上大约是50μm）。相似地，具有三个半导体芯片层的封装可以具有大约600μm的总体高度。此处描述的所述实例维度也可以应用到其它实施例中，例如图1K，3，4E，5D，6C，和7的实例实施例。所述堆叠的芯片组和/或其它部件可以再一次被分开（例如，切割）以形成单独的封装。
除了由在本公开中包括的实例所体现的潜在尺寸优势，相比于制作起来可能是相当昂贵的利用直通硅通通孔（TSV）的封装，所述半导体器件200制作起来可以是较不昂贵的。如果需要，可以例如通过扇出所述半导体芯片的导电焊盘并且使用一个或多个再分配层来避免TSV。此外，所述堆叠的电性能可以从使用再分配材料层和所述再分配层之间的短路连接中获益。芯片和/或封装的另外堆叠是可能的。例如，封装可以包括多于三个的层。封装也可以被堆叠到其它封装上。
图3示出根据此处描述的一个或者多个方面，半导体器件300（或者其部分）的侧面剖视图的另一实例。所述半导体器件300可以具有三个（或者更多）半导体芯片层。制作具有三个（或者更多）层的器件的方法可以从在图1H中示出的中间半导体器件继续。可以在多个半导体芯片305（在图3中作为实例被示为芯片305-1和305-2）的第三层的拾取和放置位置处形成（例如，通过印刷、层压、点胶等）第二粘合剂层303。所述第三半导体芯片305可以被直接放置在所述粘合剂303上。所述第三半导体芯片305可以具有第一侧（例如，顶侧），所述第一侧具有多个导电接触和/或导电延伸。第三半导体芯片305也可以具有被放置在所述粘合剂303上的第二侧（例如，底侧）。可以在所述第三半导体芯片305的周围形成第三电绝缘层307，并且可以形成（例如，通过钻孔）多个通孔309以暴露所述第三半导体芯片305的所述第二再分配层和/或所述导电延伸。可以在所述电介质307的上方形成第三再分配层311。如先前描述的，所述第三再分配层311可以将半导体芯片105的第一层的导电接触、半导体芯片114的第二层、和/或半导体芯片305的第三层扇出。可以在所述第三再分配层311的上方和/或周围形成电绝缘层313，并且钻孔和/或其它光刻技术可以暴露所述第三再分配层311。这些步骤可以被重复任何次数以形成半导体芯片的任何数目的叠层。在最后的层中，可以施加焊料停止和/或焊球315以形成半导体封装300。与其它实施例相似，所述堆叠的芯片组和/或其它部件可被分开（例如，切割）以形成单个封装。
图4A-4E示出根据此处描述的一个或多个方面的具有一个或多个倒装芯片封装的半导体器件（或者其各部分）和/或制作具有一个或多个倒装芯片封装的半导体器件的实例方法的侧面剖示图的实例。制作具有一个或多个倒装芯片封装的半导体器件的方法可以从在图1B中示出的中间半导体器件继续。如在图1C中示出的，取代施加粘合剂层，可以使用倒装芯片封装，例如倒装芯片封装409-1和409-2。在图4A中，倒装芯片封装409可以具有第一侧411（例如，有源侧），所述第一侧具有多个导电接触。倒装芯片封装409也可以具有可能不具有任何导电接触的第二侧413。倒装芯片封装409可以具有电连接到所述倒装芯片封装409的导电接触的多个焊料凸块415（例如，倒装芯片μ凸块）。所述焊料凸块415可通过例如铜UBM的金属化元件被附着到所述导电接触。以焊料凸块415面朝“上”，倒装芯片封装409可以被倒装并且被直接放置在所述第一再分配层111上。当被倒装时，所述倒装芯片封装409的有源侧411可以面对所述嵌入半导体芯片105的有源侧。可以通过将所述焊料凸块415焊接到所述第一再分配层111上，和/或通过使用热压缩结合，和/或通过使用其它半导体器件制作技术来保持电气和/或物理连接。
在图4B中，所述倒装芯片封装409可以使用电绝缘材料被底部填充、过模塑，和/或过模塑/欠模塑（例如，模塑底部填充（MUF）），形成电绝缘层417（例如，模塑层）。例如，可将能够在由所述焊料凸块415形成的间隙之间流动的材料用于底部填充。在图4C中，电绝缘层417可被研磨以减小封装高度（例如，到位置419）。可以形成（例如，通过激光钻孔、光刻等）多个通孔421（例如，互连路径）以暴露所述第一再分配层。在图4D中，所述通孔421可以被填充有导电材料423，并且可以形成第二再分配层425以扇出嵌入在所述重构晶片中和/或倒装芯片封装409中的第一半导体芯片的电接触。在图4A-4D中示出的步骤可以被重复以形成具有任何数目的半导体芯片层的半导体封装。
图4E示出根据此处描述的一个或多个方面，具有两个半导体芯片层（包括倒装芯片层）的半导体封装427的侧面剖视图的实例。所述半导体封装427可以具有另一个电绝缘层429，焊料停止，和/或焊球431。与其它实施例相似，所述堆叠的芯片组和/或其它部件可以被分开（例如，切割）以形成更小的单独封装。
图5A-5D示出根据此处描述的一个或多个方面，具有线的半导体器件（或者其各部分）和/或制作具有线的半导体器件的实例方法的侧面剖视图的实例。制作具有线的半导体器件的所述方法可以从在图1D中示出的中间半导体器件继续。因为线可以被直接连接到裸露芯片（例如，第二芯片114），所以可以不需要导电延伸117。在图5A中，导电线501可以将所述第一再分配层111电连接到所述第二半导体芯片114的导电接触。在图5B中，可以在所述第二半导体芯片114和/或所述线501周围形成电绝缘层503（例如，模塑）。在图5C中，可在电绝缘层505中形成多个通孔505（例如，互连路径）以暴露所述第一再分配层111。
图5D示出具有至少两个堆叠半导体芯片层并且使用线结合堆叠用于半导体芯片的第二层的半导体封装500的实例。由在图5C中示出的方法，所述通孔505可被填充有导电材料，可形成第二再分配层509，可形成电绝缘层511（例如电介质），和/或可形成焊球513（以及焊料停止）。与其它实施例相似，所述堆叠的芯片组和/或其它部件可被分开（例如，切割）以形成更小的单独封装。
图6A-6C示出根据此处描述的一个或多个方面，具有有源和/或无源部件的半导体器件（或者其各部分）和/或制作具有有源和/或无源部件的半导体器件的实例方法的侧面剖视图的实例。此处描述的半导体器件可以包括任何数目的有源和无源半导体芯片。有源半导体芯片可以包括，但不限于，集成电路，例如存储器、基带芯片、处理器等。无源半导体芯片可以包括，但不限于，表面安装器件（SMD）、集成无源器件（IPD）、电阻器、电容器、二极管、电感器等等。
在图6A中，可以提供基层601（例如，重构晶片）。所述基层101可以具有多个嵌入有源芯片605和/或多个嵌入无源芯片603。在图6B中，可在所述重构晶片601上形成电绝缘层607（例如，电介质）。使用暴露的所述芯片603和/或605的接触，可以在所述半导体器件上形成第一再分配层609。可以放置与所述第一再分配层609电连接的另外的有源芯片615和/或无源芯片611。例如，有源芯片615可以通过粘合剂613在结构上被连接到绝缘层607。如先前描述的，在图1（例如，RDL连接）和图5（例如，线结合连接）中示出的实例中，有源芯片615的有源侧可以是面朝上。如先前描述的，芯片615的接触可被覆盖有金属结构（例如，铜柱）。替代地，在图4中示出的实例中（例如，倒装芯片连接），芯片615的有源侧可以是面朝下。
在图6C中，可在有源芯片615和/或无源芯片611的第二层的周围形成电绝缘层617（例如，可光学构造的电绝缘层）。可暴露（例如，通过激光钻孔、光刻等）所述第一再分配层609和/或其它导电接触（例如，在有源芯片和/或无源芯片上的接触），并且可以使用导电填充物619来将所述第一再分配层电连接到上层。可以在所述半导体器件上形成第二再分配层621和电绝缘层623（例如，电介质）。可以将另外的有源芯片和/或无源芯片625与所述第二再分配层621电连接放置。可以将焊球627与所述第二再分配层621电连接放置以形成具有多个无源和/或有源部件的半导体封装600。与其它实施例相似，所述堆叠的芯片组和/或其它部件可被分开（例如，切割）以形成更小的单独封装。
图7示出根据此处描述的一个或多个方面，具有有源和/或无源部件的半导体器件700（或者其部分）的侧面剖视图的另一实例。半导体器件700可以具有基层701（例如，重构晶片），所述基层具有嵌入的无源和/或有源芯片。所述半导体器件700可以具有有源和/或无源的芯片和/或封装的一个或者多个另外的层，所述有源和/或无源的芯片和/或封装例如是有源倒装芯片封装703和多个无源芯片707。所述倒装芯片封装703可以在所述倒装芯片封装已经被放置成与再分配层电连接（例如，通过焊接、热压缩结合等）之后，使用填充材料705被底部填充。与其它实施例相似，所述堆叠的芯片组和/或其它部件可被分开（例如，切割）以形成更小的单独封装。
虽然已经示出和描述各种实施例，但只是实例。在本说明书中使用的词是描述的词而不是限制的词，并且应该理解在不偏离本公开的精神和范围的情况下可作出各种改变。

Claims (23)

1.一种半导体器件，包括：
具有第一半导体芯片的基层，所述第一半导体芯片在所述第一半导体芯片的第一侧具有至少一个导电接触；
与所述第一半导体芯片的所述至少一个导电接触接触的第一再分配层，其中所述第一再分配层延伸到所述第一半导体芯片的边界之外；
具有第一侧和第二侧的第二半导体芯片，所述第二半导体芯片在所述第二半导体芯片的第一侧具有至少一个导电接触；和
放置在所述第一半导体芯片的第一侧和所述第二半导体芯片的第二侧之间的粘合剂层，其中所述第二半导体芯片被直接放置在所述粘合剂层上。
2.权利要求1的半导体器件，进一步包括：
至少部分地放置在所述第二半导体芯片的第一侧上方的电绝缘层，其中所述电绝缘层具有暴露所述第一再分配层的至少一个通孔；和
与所述第二半导体芯片的所述至少一个导电接触接触的第二再分配层，其中所述第二再分配层通过所述至少一个通孔被电连接到所述第一再分配层。
3.权利要求2的半导体器件，进一步包括：
与所述第二再分配层接触的至少一个焊球。
4.权利要求2的半导体器件，进一步包括：
具有第一侧和第二侧的第三半导体芯片，所述第三半导体芯片在所述第三半导体芯片的第一侧具有至少一个导电接触；
放置在所述第二半导体芯片的第一侧和所述第三半导体芯片的第二侧之间的第二粘合剂层，其中所述第三半导体芯片被直接放置在所述第二粘合剂层上；
至少部分地放置在所述第三半导体芯片的第一侧上方的第二电绝缘层，其中所述第二电绝缘层具有暴露所述第二再分配层的至少一个通孔；以及
与所述第三半导体芯片的所述至少一个导电接触接触的第三再分配层，其中所述第三再分配层通过所述第二电绝缘层的所述至少一个通孔被电连接到所述第二再分配层。
5.权利要求1的半导体器件，其中所述基层是重构晶片并且其中所述第一半导体芯片被嵌入在所述重构晶片中。
6.权利要求5的半导体器件，其中多个半导体芯片被嵌入在所述重构晶片中。
7.权利要求6的半导体器件，其中所述多个半导体芯片包括至少一个无源半导体芯片和至少一个有源半导体芯片。
8.权利要求1的半导体器件，其中所述第一半导体芯片和所述第二半导体芯片形成单个集成电路封装。
9.权利要求8的半导体器件，其中所述第二半导体芯片是在不损坏所述封装的情况下不可从所述单个集成电路封装释放的。
10.权利要求1的半导体器件，其中所述粘合剂层被至少部分地放置在所述第一再分配层上。
11.权利要求1的半导体器件，其中所述第一半导体芯片和所述第二半导体芯片是集成电路。
12.权利要求1的半导体器件，进一步包括：
至少一个线，其将所述第二半导体芯片的所述至少一个导电接触电连接到所述第一再分配层；和
电绝缘层，其被至少部分地放置在所述第二半导体芯片的第一侧和所述至少一个线上方，其中所述电绝缘层具有暴露所述第一再分配层的至少一个通孔。
13.一种半导体器件，包括：
具有第一半导体芯片的基层，所述第一半导体芯片在所述第一半导体芯片的第一侧具有至少一个导电接触；
与所述第一半导体芯片的所述至少一个导电接触接触的第一再分配层，其中所述第一再分配层延伸到所述第一半导体芯片的边界之外；和
具有第一侧和第二侧的半导体倒装芯片，所述半导体倒装芯片在所述半导体倒装芯片的第一侧具有至少一个导电接触，
其中所述第一半导体芯片的第一侧面向所述半导体倒装芯片的第一侧。
14.权利要求13的半导体器件，进一步包括：
电绝缘层，其至少部分地被放置在所述半导体倒装芯片的第二侧的上方，其中所述电绝缘层具有暴露所述第一再分配层的至少一个通孔；和
第二再分配层，其穿过所述至少一个通孔和所述第一再分配层被电连接到所述半导体倒装芯片的所述至少一个导电接触。
15.一种用于制作半导体器件的方法，所述方法包括：
在具有第一半导体芯片的基层的表面上形成第一再分配层，所述第一半导体芯片在所述第一半导体芯片的第一侧具有至少一个导电接触，其中所述第一再分配层与所述第一半导体芯片的所述至少一个导电接触接触；
至少部分地在所述第一再分配层的表面上施加粘合剂层；
在所述粘合剂层上放置第二半导体芯片；
在所述第二半导体芯片的周围施加聚合体层；
形成穿过所述聚合体层的至少一个通孔，其中所述至少一个通孔暴露所述第一再分配层；以及
在所述聚合体层的表面上形成第二再分配层。
16.权利要求15的方法，其中所述第二半导体芯片在所述第二半导体芯片的第一侧具有至少一个导电接触，并且其中放置所述第二半导体芯片包括：
在所述粘合剂层上放置所述第二半导体芯片的第二侧，所述第二侧与所述第一侧不同。
17.权利要求16的方法，进一步包括：
至少部分地在所述第二半导体芯片的第一侧上形成电绝缘层；以及
形成穿过所述绝缘层的至少一个通孔，其中所述至少一个通孔暴露所述第一再分配层。
18.权利要求17的方法，进一步包括：
在电绝缘层上形成第二分配层，其中所述第二再分配层通过所述至少一个通孔将所述第二半导体芯片的所述至少一个导电接触电连接到所述第一再分配层。
19.权利要求18的方法，进一步包括：
将至少一个焊球放置在所述第二再分配层上。
20.权利要求18的方法，进一步包括：
至少部分地在所述第二再分配层的表面上施加第二粘合剂层；
将第三半导体芯片放置在所述第二粘合剂层上；
至少部分地在所述第三半导体芯片上形成第二电绝缘层；
形成穿过所述第二绝缘层的至少一个通孔，其中所述第二绝缘层的所述至少一个通孔暴露所述第二再分配层；以及
在所述第二电绝缘层上形成第三再分配层，其中所述第三再分配层通过所述第二绝缘层的所述至少一个通孔将所述第三半导体芯片的至少一个导电接触电连接到所述第二再分配层。
21.权利要求15的方法，进一步包括：
研磨所述基层以去除多余材料。
22.权利要求15的方法，其中所述基层是重构晶片并且其中所述第一半导体芯片被嵌入在所述重构晶片中。
23.权利要求15的方法，进一步包括：
在施加所述聚合体层之前，使用线将所述第二半导体芯片的至少一个导电接触电连接到所述第一再分配层。
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