CN111081650A - 扇出型半导体封装件 - Google Patents
扇出型半导体封装件 Download PDFInfo
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- CN111081650A CN111081650A CN201910977376.0A CN201910977376A CN111081650A CN 111081650 A CN111081650 A CN 111081650A CN 201910977376 A CN201910977376 A CN 201910977376A CN 111081650 A CN111081650 A CN 111081650A
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- fan
- semiconductor chip
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- insulating layer
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Abstract
本公开提供一种扇出型半导体封装件,所述扇出型半导体封装件包括:连接结构,包括一个或更多个重新分布层;第一半导体芯片,设置在所述连接结构的第一表面上并具有第一连接焊盘;第一包封剂,设置在所述连接结构的所述第一表面上,并覆盖所述第一半导体芯片的至少一部分;以及第二半导体芯片,设置在所述连接结构的第二表面上并具有第二连接焊盘,其中,所述第一连接焊盘通过所述连接结构的连接过孔电连接到所述一个或更多个重新分布层,所述第二连接焊盘通过线电连接到所述一个或更多个重新分布层,并且所述第一连接焊盘和所述第二连接焊盘通过所述一个或更多个重新分布层彼此电连接。
Description
本申请要求于2018年10月19日在韩国知识产权局提交的第10-2018-0125334号韩国专利申请的优先权的权益,所述韩国专利申请的公开内容通过引用被包含于此。
技术领域
本公开涉及一种半导体封装件,例如,电连接金属可延伸到除了设置半导体芯片的区域以外的区域的扇出型半导体封装件。
背景技术
在半导体市场中,持续需求的趋势是半导体的轻量化、纤薄化、缩短化和小型化。由于消费者想要以低成本提供的具有低电池耗电量的较小尺寸的产品,因此半导体制造商正在尝试减小芯片尺寸和封装件尺寸。
随着对这种小尺寸的产品的应用的需求,半导体芯片的尺寸已不断减小。在制造半导体封装件时为了电信号的连接而提出的半导体封装件技术是扇出型封装件。在应用有这种扇出型封装件的传统的层叠封装(PoP)型封装结构的情况下,单独制造下封装件和上封装件以构成完整的封装件。在这种情况下,产品会具有相当大的厚度并且会出现信号损耗。
发明内容
根据本公开的方面,即使扇出型半导体封装件包括多个半导体芯片,扇出型半导体封装件也可变薄,并且可具有较少的信号损耗。
根据本公开的方面,第一半导体芯片可以以面朝上的取向嵌在面板级封装件(PLP)中,并且第二半导体芯片可设置在PLP的重新分布层(RDL)上并通过线电连接到RDL。结果,第一半导体芯片和第二半导体芯片可通过RDL彼此电连接。
根据本公开的一方面,一种扇出型半导体封装件包括:连接结构,包括一个或更多个重新分布层;第一半导体芯片,设置在所述连接结构的第一表面上,并具有第一有效表面和与所述第一有效表面相对的第一无效表面,其中,在所述第一有效表面上设置有第一连接焊盘,并且所述第一有效表面面对所述连接结构的所述第一表面;第一包封剂,设置在所述连接结构的所述第一表面上,覆盖所述第一半导体芯片的至少一部分;以及第二半导体芯片,设置在所述连接结构的与所述第一表面相对的第二表面上,具有第二有效表面和与所述第二有效表面相对的第二无效表面,其中,在所述第二有效表面上设置有第二连接焊盘,并且所述第二无效表面面对所述连接结构的所述第二表面。所述第一连接焊盘通过所述连接结构的连接过孔电连接到所述一个或更多个重新分布层,所述第二连接焊盘通过线电连接到所述一个或更多个重新分布层,并且所述第一连接焊盘和所述第二连接焊盘通过所述一个或更多个重新分布层彼此电连接。
根据本公开的另一方面,一种扇出型半导体封装件包括:框架,具有通孔并包括一个或更多个布线层;第一半导体芯片,设置在所述框架的所述通孔中,具有第一有效表面和与所述第一有效表面相对的第一无效表面,其中,在所述第一有效表面上设置有第一连接焊盘;第一包封剂,覆盖所述第一半导体芯片的至少一部分;以及第二半导体芯片,设置在所述第一半导体芯片的一个表面上,具有第二有效表面和与所述第二有效表面相对的第二无效表面,其中,在所述第二有效表面上设置有第二连接焊盘,所述第二无效表面面对所述第一半导体芯片的所述第一有效表面。所述第一半导体芯片和所述第二半导体芯片被布置为相对于垂直于堆叠方向的方向错位,使得所述第一连接焊盘被暴露,所述第一连接焊盘通过第一线电连接到所述一个或更多个布线层,所述第二连接焊盘通过第二线电连接到所述一个或更多个布线层,并且所述第一连接焊盘和所述第二连接焊盘通过所述一个或更多个布线层彼此电连接。
附图说明
通过下面结合附图进行的详细描述,本公开的以上和其他方面、特征和优点将被更清楚地理解,在附图中:
图1是示意性地示出电子装置系统的示例的框图;
图2是示出电子装置的示例的示意性透视图;
图3A和图3B是示出扇入型半导体封装件在被封装之前和被封装之后的状态的示意性截面图;
图4是示出扇入型半导体封装件的封装工艺的示意性截面图;
图5是示出扇入型半导体封装件安装在球栅阵列(BGA)基板上并且最终安装在电子装置的主板上的情况的示意性截面图;
图6是示出扇入型半导体封装件嵌在BGA基板中并且最终安装在电子装置的主板上的情况的示意性截面图;
图7是示出扇出型半导体封装件的示意性截面图;
图8是示出扇出型半导体封装件安装在电子装置的主板上的情况的示意性截面图;
图9是示出扇出型半导体封装件的示例的示意性截面图;
图10是沿着图9中的扇出型半导体封装件的线I-I'截取的剖切平面图;
图11是示出扇出型半导体封装件的另一示例的示意性截面图;
图12是示出扇出型半导体封装件的另一示例的示意性截面图;
图13是示出扇出型半导体封装件的另一示例的示意性截面图;以及
图14是示出扇出型半导体封装件的另一示例的示意性截面图。
具体实施方式
在下文中,将参照附图如下描述本公开的实施例。
电子装置
图1是示出电子装置系统的示例的示意性框图。
参照图1,电子装置1000可将主板1010容纳在其中。主板1010可包括物理连接或者电连接到其的芯片相关组件1020、网络相关组件1030、其他组件1040等。这些组件可通过各种信号线1090连接到以下将描述的其他组件。
芯片相关组件1020可包括:存储器芯片,诸如易失性存储器(例如,动态随机存取存储器(DRAM))、非易失性存储器(例如,只读存储器(ROM))、闪存等;应用处理器芯片,诸如中央处理器(例如,中央处理单元(CPU))、图形处理器(例如,图形处理单元(GPU))、数字信号处理器、密码处理器、微处理器、微控制器等;以及逻辑芯片,诸如模拟数字转换器(ADC)、专用集成电路(ASIC)等。然而,芯片相关组件1020不限于此,而是还可包括其他类型的芯片相关组件。此外,芯片相关组件1020可彼此组合。
网络相关组件1030可包括根据诸如以下的协议操作的组件:无线保真(Wi-Fi)(电工电子工程师协会(IEEE)802.11族等)、全球微波接入互操作性(WiMAX)(IEEE 802.16族等)、IEEE 802.20、长期演进(LTE)、演进数据最优化(Ev-DO)、高速分组接入+(HSPA+)、高速下行链路分组接入+(HSDPA+)、高速上行链路分组接入+(HSUPA+)、增强型数据GSM环境(EDGE)、全球移动通信系统(GSM)、全球定位系统(GPS)、通用分组无线业务(GPRS)、码分多址(CDMA)、时分多址(TDMA)、数字增强型无绳电信(DECT)、蓝牙、3G协议、4G协议和5G协议以及在上述协议之后指定的任意其他无线协议和有线协议。然而,网络相关组件1030不限于此,而是还可包括根据各种其他无线标准或协议或者有线标准或协议操作的组件。此外,网络相关组件1030可与上述芯片相关组件1020一起彼此组合。
其他组件1040可包括高频电感器、铁氧体电感器、功率电感器、铁氧体磁珠、低温共烧陶瓷(LTCC)、电磁干扰(EMI)滤波器、多层陶瓷电容器(MLCC)等。然而,其他组件1040不限于此,而是还可包括用于各种其他目的的无源组件等。此外,其他组件1040可与上述芯片相关组件1020或网络相关组件1030一起彼此组合。
根据电子装置1000的类型,电子装置1000可包括可物理连接或电连接到主板1010或者可不物理连接或电连接到主板1010的其他组件。这些其他组件可包括例如相机1050、天线1060、显示器1070、电池1080、音频编解码器(未示出)、视频编解码器(未示出)、功率放大器(未示出)、指南针(未示出)、加速计(未示出)、陀螺仪(未示出)、扬声器(未示出)、大容量存储单元(例如,硬盘驱动器)(未示出)、光盘(CD)驱动器(未示出)、数字通用光盘(DVD)驱动器(未示出)等。然而,这些其他组件不限于此,而是还可根据电子装置1000的类型等而包括用于各种目的的其他组件。
电子装置1000可以是智能电话、个人数字助理(PDA)、数字摄像机、数码相机、网络系统、计算机、监视器、平板PC、膝上型PC、上网本PC、电视机、视频游戏机、智能手表、汽车组件等。然而,电子装置1000不限于此,而是可以是处理数据的任意其他电子装置。
图2是示出电子装置的示例的示意性透视图。
参照图2,半导体封装件可在如上所述的各种电子装置1000中用于各种目的。例如,母板1110可被容纳在智能电话1100的主体1101中,并且各种电子组件1120可物理连接或者电连接到母板1110。另外,可物理连接或电连接到母板1110或者可不物理连接或电连接到母板1110的其他组件(诸如,相机模块1130)可被容纳在主体1101中。电子组件1120中的一些可以是芯片相关组件,例如,半导体封装件1121,但不限于此。电子装置不必局限于智能电话1100,而是可以是如上所述的其他电子装置。
半导体封装件
通常,在半导体芯片中集成了大量的微电子电路。然而,半导体芯片本身可能无法用作成品的半导体产品,并且可能会由于外部的物理冲击或者化学冲击而损坏。因此,半导体芯片本身可能无法被使用,而是可被封装并且在封装的状态下在电子装置等中使用。
这里,就电连接而言,由于半导体芯片和电子装置的主板之间的电路宽度存在差异,因此需要半导体封装。详细地,半导体芯片的连接焊盘的尺寸和半导体芯片的连接焊盘之间的间距非常细小,而在电子装置中使用的主板的组件安装焊盘的尺寸和主板的组件安装焊盘之间的间距显著大于半导体芯片的连接焊盘的尺寸和半导体芯片的连接焊盘之间的间距。因此,可能难以将半导体芯片直接安装在主板上,并且需要用于缓解半导体芯片和主板之间的电路宽度的差异的封装技术。
通过封装技术制造的半导体封装件可根据其结构和目的而分为扇入型半导体封装件和扇出型半导体封装件。
在下文中,将参照附图更详细地描述扇入型半导体封装件和扇出型半导体封装件。
扇入型半导体封装件
图3A和图3B是示出扇入型半导体封装件在被封装之前和被封装之后的状态的示意性截面图。
图4是示出扇入型半导体封装件的封装工艺的示意性截面图。
参照图3A至图4,半导体芯片2220可以是例如处于裸态的集成电路(IC),并且包括:主体2221,包括硅(Si)、锗(Ge)、砷化镓(GaAs)等;连接焊盘2222,形成在主体2221的一个表面上,并且包括诸如铝(Al)等的导电材料;以及诸如氧化物层、氮化物层等的钝化层2223,形成在主体2221的一个表面上并且覆盖连接焊盘2222的至少部分。在这种情况下,由于连接焊盘2222可能非常小,因此可能难以将集成电路(IC)安装在中等尺寸等级的印刷电路板(PCB)以及电子装置的主板等上。
因此,根据半导体芯片2220的尺寸,可在半导体芯片2220上形成连接构件2240,以使连接焊盘2222重新分布。连接构件2240可通过如下步骤形成:使用诸如感光介电(PID)树脂的绝缘材料在半导体芯片2220上形成绝缘层2241,形成使连接焊盘2222敞开的通路孔2243h,然后形成布线图案2242和过孔2243。然后,可形成保护连接构件2240的钝化层2250,可形成开口2251,并且可形成凸块下金属层2260等。也就是说,可通过一系列工艺制造包括例如半导体芯片2220、连接构件2240、钝化层2250和凸块下金属层2260的扇入型半导体封装件2200。
如上所述,扇入型半导体封装件可具有半导体芯片的所有的连接焊盘(例如,输入/输出(I/O)端子)设置在半导体芯片的内部的封装件形式,可具有优异的电特性,并且可按照低成本生产。因此,安装在智能电话中的许多元件已经按照扇入型半导体封装件形式来制造。详细地,安装在智能电话中的许多元件已经被开发为在具有紧凑的尺寸的同时实现快速的信号传输。
然而,在扇入型半导体封装件中,由于所有的I/O端子需要设置在半导体芯片的内部,因此扇入型半导体封装件具有很大的空间局限性。因此,难以将此结构应用于具有大量的I/O端子的半导体芯片或者具有紧凑尺寸的半导体芯片。另外,由于上述缺点,可能无法在电子装置的主板上直接安装和使用扇入型半导体封装件。原因在于:即使半导体芯片的I/O端子的尺寸和半导体芯片的I/O端子之间的间距通过重新分布工艺被增大,半导体芯片的I/O端子的尺寸和半导体芯片的I/O端子之间的间距仍不足以将扇入型半导体封装件直接安装在电子装置的主板上。
图5是示出扇入型半导体封装件安装在球栅阵列(BGA)基板上并且最终安装在电子装置的主板上的情况的示意性截面图。
图6是示出扇入型半导体封装件嵌在BGA基板中并且最终安装在电子装置的主板上的情况的示意性截面图。
参照图5,在扇入型半导体封装件2200中,半导体芯片2220的连接焊盘2222(即,I/O端子)可通过BGA基板2301重新分布,并且扇入型半导体封装件2200可在其安装在BGA基板2301上的状态下最终安装在电子装置的主板2500上。在这种情况下,焊球2270等可通过底部填充树脂2280等固定,并且半导体芯片2220的外侧可利用模制材料2290等覆盖。可选地,参照图6,扇入型半导体封装件2200可嵌在单独的BGA基板2302中,在扇入型半导体封装件2200嵌在BGA基板2302中的状态下,半导体芯片2220的连接焊盘2222(即,I/O端子)可通过BGA基板2302重新分布,并且扇入型半导体封装件2200可最终安装在电子装置的主板2500上。
如上所述,可能会难以在电子装置的主板上直接安装和使用扇入型半导体封装件。因此,扇入型半导体封装件可安装在单独的BGA基板上然后通过封装工艺安装在电子装置的主板上,或者可在扇入型半导体封装件嵌在BGA基板中的状态下在电子装置的主板上安装和使用扇入型半导体封装件。
扇出型半导体封装件
图7是示出扇出型半导体封装件的示意性截面图。
参照图7,在扇出型半导体封装件2100中,例如,半导体芯片2120的外侧可通过包封剂2130保护,并且半导体芯片2120的连接焊盘2122可通过连接构件2140重新分布到半导体芯片2120的外部。在这种情况下,可在连接构件2140上进一步形成钝化层2150,并且可在钝化层2150的开口中进一步形成凸块下金属层2160。焊球2170可进一步形成在凸块下金属层2160上。半导体芯片2120可以是包括主体2121、连接焊盘2122、钝化层(未示出)等的集成电路(IC)。连接构件2140可包括:绝缘层2141;重新分布层2142,形成在绝缘层2141上;以及过孔2143,使连接焊盘2122和重新分布层2142彼此电连接。
如上所述,扇出型半导体封装件可具有半导体芯片的I/O端子通过形成在半导体芯片上的连接构件重新分布并且设置在半导体芯片的外部的形式。如上所述,在扇入型半导体封装件中,半导体芯片的所有的I/O端子需要设置在半导体芯片的内部。因此,当半导体芯片的尺寸减小时,球的尺寸和节距需要减小,使得在扇入型半导体封装件中可能无法使用标准化的球布局。另一方面,如上所述,扇出型半导体封装件具有半导体芯片的I/O端子通过形成在半导体芯片上的连接构件重新分布并且设置在半导体芯片的外部的形式。因此,即使在半导体芯片的尺寸减小的情况下,在扇出型半导体封装件中仍可按照原样使用标准化的球布局,使得扇出型半导体封装件可在不使用单独的BGA基板的情况下安装在电子装置的主板上,如下所述。
图8是示出扇出型半导体封装件安装在电子装置的主板上的情况的示意性截面图。
参照图8,扇出型半导体封装件2100可通过焊球2170等安装在电子装置的主板2500上。也就是说,如上所述,扇出型半导体封装件2100包括连接构件2140,连接构件2140形成在半导体芯片2120上并且能够使连接焊盘2122重新分布到半导体芯片2120的尺寸的外部的扇出区域,使得可在扇出型半导体封装件2100中按照原样使用标准化的球布局。结果,扇出型半导体封装件2100可在不使用单独的BGA基板等的情况下安装在电子装置的主板2500上。
如上所述,由于扇出型半导体封装件可在不使用单独的BGA基板的情况下安装在电子装置的主板上,因此扇出型半导体封装件可按照比使用BGA基板的扇入型半导体封装件的厚度小的厚度实现。因此,扇出型半导体封装件可被小型化和纤薄化。另外,扇出型半导体封装件具有优异的热特性和电特性,使得其特别适合于移动产品。因此,扇出型半导体封装件可按照比使用印刷电路板(PCB)的普通的层叠封装(POP)类型的形式更紧凑的形式实现,并且可解决由于翘曲现象的发生而引起的问题。
另外,扇出型半导体封装件指的是如上所述的用于将半导体芯片安装在电子装置的主板等上并且保护半导体芯片免受外部冲击的影响的封装件技术,并且是与诸如BGA基板等的印刷电路板(PCB)(具有与扇出型半导体封装件的规格、用途等不同的规格、用途等,并且具有嵌在其中的扇入型半导体封装件)的概念不同的概念。
在下文中,将参照附图描述即使扇出型半导体封装件包括多个半导体芯片也可变薄并且具有较少的信号损耗的扇出型半导体封装件。
图9是示出扇出型半导体封装件的示例的示意性截面图,并且图10是沿着图9中的扇出型半导体封装件的线I-I'截取的剖切平面图。
参照图9和图10,根据示例实施例的半导体封装件100A包括:框架110,具有通孔110H并且包括一个或更多个布线层112a和112b;第一半导体芯片121,设置在框架110的通孔110H中,具有第一有效表面和与第一有效表面相对的第一无效表面,在第一有效表面上设置有第一连接焊盘121P;第一包封剂130,覆盖框架110和第一半导体芯片121的第一无效表面并填充通孔110H的至少一部分;连接结构140,设置在框架110和第一半导体芯片121的第一有效表面上,包括一个或更多个重新分布层142;第二半导体芯片122,设置在连接结构140上,具有第二有效表面和与第二有效表面相对的第二无效表面,在第二有效表面上设置有第二连接焊盘122P;第二包封剂150,设置在连接结构140上并覆盖第二半导体芯片122的至少一部分;多个开口130h,在与设置有连接结构140的一侧相对的一侧上形成在第一包封剂130的覆盖框架110的区域中,每个开口130h使设置在框架110的与设置有第一连接结构140的一侧相对的一侧上的布线层112b的至少一部分暴露;以及多个电连接金属160,分别设置在多个开口130h中,每个电连接金属160电连接到暴露的布线层112b。
第一半导体芯片121以第一有效表面面对连接结构140的底表面(基于附图)这样的方式设置,第二半导体芯片122以第二无效表面面对连接结构的顶表面(基于附图)这样的方式设置,第一连接焊盘121P通过连接结构140的连接过孔143电连接到重新分布层142,并且第二连接焊盘122P通过线125电连接到重新分布层142。结果,第一连接焊盘121P和第二连接焊盘122P通过重新分布层142彼此电连接。第二半导体芯片122可以以第二无效表面通过粘合剂128附着到连接结构140的顶表面这样的方式设置。粘合剂128可以是已知的芯片附着膜(DAF)。
例如,扇出型半导体封装件100A包括设置在第一半导体芯片121和第二半导体芯片122之间并且包括重新分布层142的连接结构140。在这种情况下,第一半导体芯片121以面朝上的取向设置以通过连接过孔143电连接到重新分布层142,并且第二半导体芯片122通过线电连接到重新分布层142。因此,可显著减小第一半导体芯片121和第二半导体芯片122之间的信号传输路径。结果,可显著降低信号特性的损耗。由于这种结构是设置有第一半导体芯片121和第二半导体芯片122而没有附加的插入件的结构,因此可显著减小封装件100A的总厚度。例如,可提供即使扇出型半导体封装件100A包括多个半导体芯片也可变薄并且具有较少的信号损耗的扇出型半导体封装件100A。扇出型半导体封装件100A可有效地应用于存储器封装件等。
在下文中,将详细描述包括在根据示例实施例的扇出型半导体封装件100A中的每个组件。
框架110包括使第一半导体芯片121的第一连接焊盘121P和第二半导体芯片122的第二连接焊盘122P重新分布的一个或更多个布线层112a和112b,并且可减少连接结构140的层数。另外,可根据框架110的绝缘层111的具体材料来保持封装件100A的刚性,并且框架110可用于确保第一包封剂130的厚度均匀性等。扇出型半导体封装件100A的上部和下部可通过框架110电连接。框架110可具有通孔110H,并且第一半导体芯片121可设置在通孔110H中。通孔110H可形成为包围第一半导体芯片121的侧表面的外周。作为框架110的替代,可设置能够将扇出型半导体封装件100A的上部和下部电连接的另一电连接结构(诸如金属柱)。
作为示例,框架110可包括:绝缘层111,设置为与连接结构140接触;第一布线层112a,嵌在绝缘层111中并与连接结构140接触;第二布线层112b,设置在绝缘层111的与设置有第一布线层112a的一侧相对的一侧上;以及连接过孔层113,贯穿绝缘层111并且将第一布线层112a和第二布线层112b电连接。当第一布线层112a嵌在绝缘层111中时,由于第一布线层112a的厚度相对于绝缘层111形成的台阶显著减小。相应地,由于连接结构140的绝缘距离具有恒定值,因此可容易地执行连接结构140的高密度布线设计。第一布线层112a的设置为与连接结构140接触的表面相对于绝缘层111的设置为与连接结构140接触的表面可具有预定的台阶。利用这样的预定的台阶的结构,绝缘层111可防止第一包封剂130渗到第一布线层112a以解决渗漏问题。
绝缘层111的材料不受限制。例如,绝缘材料可用作绝缘层111的材料。在这种情况下,绝缘材料可以是热固性树脂(诸如环氧树脂)、热塑性树脂(诸如聚酰亚胺树脂)、热固性树脂或热塑性树脂与无机填料混合或者与无机填料一起浸在诸如玻璃纤维(或玻璃布或玻璃织物)的芯材料中的树脂(例如,半固化片、ABF(Ajinomoto Build up Film)、FR-4、双马来酰亚胺三嗪(BT)等)。详细地,半固化片或ABF可用作绝缘材料。
第一布线层112a和第二布线层112b可用于使第一半导体芯片121的第一连接焊盘121P和第二半导体芯片122的第二连接焊盘122P重新分布,并且可用于提供用于连接过孔层113的焊盘图案以连接封装件100A的上部和下部。第一布线层112a和第二布线层112b中的每个的材料可以是诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金的金属材料。第一布线层112a和第二布线层112b可根据相应层的设计而执行各种功能。例如,第一布线层112a和第二布线层112b可包括接地(GND)图案、电力(PWR)图案、信号(S)图案等。信号(S)图案可包括除了接地(GND)图案、电力(PWR)图案等之外的各种信号图案(诸如数据信号图案等)。另外,第一布线层112a和第二布线层112b可包括过孔焊盘、电连接金属焊盘等。电连接金属焊盘的至少一部分可通过形成在第一包封剂130中的开口130h暴露。根据需要,表面处理层(未示出)可形成在电连接金属焊盘上。表面处理层(未示出)可以不受限制,只要是本领域已知的即可,并且表面处理层(未示出)可通过例如电镀金、浸镀金(immersion gold plating)、有机可焊性保护(OSP)或浸镀锡(immersion tinplating)、浸镀银(immersion silver plating)、化镍浸金(ENIG)、直接浸金(DIG)镀、热空气焊料均涂(HASL)等形成。
连接过孔层113可将设置在不同层上的第一布线层112a和第二布线层112b彼此电连接,以在框架110中形成电路径。连接过孔层113的材料可以是金属材料。连接过孔层113可以是利用金属材料完全填充的填充型过孔,或者是金属材料沿着通路孔的壁表面形成的共形型过孔。此外,连接过孔层113可具有锥形形状等。由于当形成用于连接过孔层113的通路孔时第一布线层112a的焊盘图案的一部分可用作阻挡件,因此在工艺中有利的是连接过孔层113具有下侧的宽度大于上侧的宽度(基于附图)的锥形形状。然而,在这种情况下,连接过孔层113可与第二布线层112b的图案的一部分一体化。
第一半导体芯片121和第二半导体芯片122中的每个可以是数百至数十万个组件集成在单个芯片中的集成电路芯片。在这种情况下,第一半导体芯片121和第二半导体芯片122可以是同构集成电路芯片,例如,同构存储器芯片。存储器芯片可以是易失性存储器(例如,DRAM)、非易失性存储器(例如,ROM)、闪存等。
第一半导体芯片121和第二半导体芯片122中的每个可基于有效晶圆形成。在这种情况下,主体的基体材料可以是硅(Si)、锗(Ge)、砷化镓(GaAs)等。各种电路可形成在主体上。第一连接焊盘121P和第二连接焊盘122P可将第一半导体芯片121和第二半导体芯片122电连接到其他组件。连接焊盘121P和122P中的每个的材料可以是诸如铝(Al)、铜(Cu)等的金属,但不限于此。其上设置有第一连接焊盘121P的表面和其上设置有第二连接焊盘122P的表面分别是第一有效表面和第二有效表面。与第一有效表面相对的表面和与第二有效表面相对的表面分别是第一无效表面和第二无效表面。钝化层(未示出)可设置在主体上以使相应的第一连接焊盘121P和第二连接焊盘122P暴露,并且钝化层(未示出)可以是氧化物层、氮化物层等。可选地,钝化层(未示出)可以是氧化物层和氮化物层的双层。绝缘层(未示出)等还可设置在其他需要的位置,并且重新分布层(未示出)可形成在有效表面上。在包括这种钝化层(未示出)时,第一有效表面和第二有效表面指的是最上表面或最下表面。
第一半导体芯片121可通过连接结构140的连接过孔143电连接到连接结构140的重新分布层142,并且第二半导体芯片122可通过线电连接到连接结构140的重新分布层142。线可以是包括诸如铜(Cu)、金(Au)等的金属的金属线。
第一包封剂130可保护框架110、第一半导体芯片121等。包封形式不受限制,只要第一包封剂130覆盖第一半导体芯片121的至少一部分即可。例如,第一包封剂130可覆盖框架110的至少一部分和第一半导体芯片121的第一无效表面的至少一部分,并且可填充通孔110H的至少一部分。第一包封剂130的具体材料不受限制。例如,绝缘材料可用作第一包封剂130的材料。绝缘材料可以是,例如,热固性树脂(诸如环氧树脂)、热塑性树脂(诸如聚酰亚胺树脂)、具有诸如无机填料的增强材料浸在热固性树脂或热塑性树脂中的树脂(诸如ABF、FR-4、BT等)。可选地,环氧模塑料(EMC)、感光电介质(PID)等可用作绝缘材料。根据需要,热固性树脂或热塑性树脂浸有无机填料和/或芯材料(诸如玻璃纤维(或玻璃布或玻璃织物))的材料(例如,半固化片)也可用作绝缘材料。
第一半导体芯片121的第一有效表面可与第一包封剂130的设置为与连接结构140接触的表面共面。第一半导体芯片121的第一有效表面也可与框架110的设置为与连接结构140接触的表面(例如,绝缘层111的设置为与连接结构140接触的表面)共面。在这种情况下,连接结构140的绝缘层141不会形成有起伏,这在连接结构140的高密度电路设计中可以是有用的。
连接结构140可使第一半导体芯片121的第一连接焊盘121P和第二半导体芯片122的第二连接焊盘122P重新分布,并且可将第一连接焊盘121P和第二连接焊盘122P彼此电连接。具有各种功能的数十至数百万个第一连接焊盘121P和第二连接焊盘122P可通过连接结构140重新分布,并且可根据它们的功能通过电连接金属160物理连接和/或电连接到外部组件。连接结构140包括:绝缘层141;重新分布层142,设置在绝缘层141上;以及连接过孔143,贯穿绝缘层141并将重新分布层142电连接到第一布线层112a和第一连接焊盘121P。与附图不同,不仅绝缘层141可以是多层,而且重新分布层142和连接过孔143也可以是多层。在这种情况下,连接过孔143中的至少一层可将不同层的重新分布层142彼此电连接。
绝缘层141的材料可以是绝缘材料。绝缘材料可以是感光材料,诸如感光电介质(PID)。例如,绝缘层141可以是感光层。当绝缘层141具有感光特性时,可进一步减薄绝缘层141并且可更容易地实现连接过孔143的精细节距。绝缘层141可以是包括绝缘树脂和无机填料的感光绝缘层。当绝缘层141包括多个层时,多个层的材料可彼此相同,并且根据需要,多个层的材料可彼此不同。当绝缘层141包括多个层时,多个层可彼此一体化,使得它们之间的边界不容易明显。根据需要,形成有重新分布层142和连接过孔143的下绝缘层141可包括上述PID,并且覆盖重新分布层142的上绝缘层141可包括ABF或已知的阻焊剂,但它们的材料不限于此。
重新分布层142可基本上用于使第一连接焊盘121P和第二连接焊盘122P重新分布。重新分布层142的材料可以是诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金的金属材料。重新分布层142可根据相应层的设计而执行各种功能。例如,重新分布层142可包括接地(GND)图案、电力(PWR)图案、信号(S)图案等。信号(S)图案包括除了接地(GND)图案、电力(PWR)图案等之外的各种信号图案(例如,数据信号图案等)。接地(GND)图案和电力(PWR)图案可彼此相同。重新分布层142可包括线焊盘、过孔焊盘、电连接金属焊盘等。根据需要,表面处理层(未示出)可形成在线焊盘的表面上,线焊盘具有被暴露以与线125连接的至少一部分。表面处理层(未示出)可通过例如电镀金、浸镀金、有机可焊性保护(OSP)或浸镀锡、浸镀银、化镍浸金(ENIG)、直接浸金(DIG)镀、热空气焊料均涂(HASL)等形成,但其形成方法不限于此。
框架110的第一布线层112a和第二布线层112b中的每个的厚度可大于连接结构140的重新分布层142的厚度。框架110的厚度可大于或等于第一半导体芯片121的厚度,使得第一布线层112a和第二布线层112b中的每个可根据其规格而具有较大的尺寸。此外,为了连接结构140的高密度设计,连接结构140的重新分布层142可形成为具有比第一布线层112a和第二布线层112b中的每个相对更小的厚度。
连接过孔143可将形成在不同层上的重新分布层142、第一连接焊盘121P等电连接,以在封装件100A中形成电路径。连接过孔的材料可以是诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金的金属材料。连接过孔143可以是利用金属材料完全填充的填充型过孔,或者是金属材料沿着通路孔的壁表面形成的共形型过孔。连接过孔143可具有沿着相同方向的锥形形状。在这种情况下,连接过孔143的锥形方向可与连接过孔层113的连接过孔的锥形方向相反。
另外地,第二包封剂150可被构造为保护第二半导体芯片122。第二包封剂150的包封形式不受限制,只要第二包封剂150覆盖第二半导体芯片122的至少一部分即可。例如,第二包封剂150可设置在连接结构140上,以覆盖第二半导体芯片122的第二有效表面和侧表面。此外,第二包封剂150可包封线。例如,第二包封剂150可覆盖线的至少一部分。第二包封剂150的具体材料不受限制。例如,绝缘材料可用作第二包封剂150的材料。如上所述,绝缘材料可以是例如,热固性树脂(诸如环氧树脂)、热塑性树脂(诸如聚酰亚胺树脂)、具有诸如无机填料的增强材料浸在热固性树脂或热塑性树脂中的树脂(诸如ABF、FR-4、BT等)。可选地,EMC、PID等可用作绝缘材料。根据需要,热固性树脂或热塑性树脂浸有无机填料和/或芯材料(诸如玻璃纤维)的材料(例如,半固化片)也可用作绝缘材料。
另外地,电连接金属160被构造为将半导体封装件100A物理连接和/或电连接到外部组件。例如,半导体封装件100A可通过电连接金属160安装在电子装置的主板上。电连接金属160可利用诸如锡(Sn)或含Sn的合金的低熔点金属形成。更具体地,电连接金属160可利用焊料等形成,但这仅是示例并且其材料不限于此。电连接金属160可以是焊盘、焊球、引脚等。电连接金属160可包括多个层或单个层。当电连接金属160包括多个层时,电连接金属160可包括铜(Cu)柱和焊料。当电连接金属160包括单个层时,电连接金属160可包括锡-银焊料或铜(Cu)。然而,这些也仅是示例,并且电连接金属160的结构和材料不限于此。
电连接金属160的数量、间距、设置形式等不受限制,而是本领域技术人员可根据设计进行充分修改。例如,根据第一连接焊盘121P和第二连接焊盘122P的数量,可提供数十至数万个电连接金属160,并且可提供更多数量或更少数量的电连接金属160。
电连接金属160可全部设置在扇出区域中。术语“扇出区域”是指从垂直于堆叠方向的视角除了设置第一半导体芯片121的区域之外的区域。与扇入型封装件相比,扇出型封装件可具有提高的可靠性,可允许实现多个输入/输出(I/O)端子,并且可促进三维(3D)互连。此外,与球栅阵列(BGA)封装件、栅格阵列(LGA)封装件等相比,扇出型封装件可被制造为具有小的厚度,并且在价格竞争力方面可更优异。
电连接金属160仅设置在扇出区域中,使得在通过重新分布层142使第一半导体芯片121的第一连接焊盘121P和第二半导体芯片122的第二连接焊盘122P重新分布的设计工艺期间基本上不与电连接金属焊盘干涉。因此,可更有效地减少重新分布层142的层数。例如,可省略在与第一包封剂130的其上设置有连接结构140的一侧相对的一侧上设计附加的重新分布层。
虽然未在附图中示出,但是额外的无源组件可与第一半导体芯片121并排地设置在通孔110H中。金属层可设置在通孔110H的壁表面上以屏蔽电磁干扰并获得散热效果。根据需要,凸块下金属可设置在第一包封剂130的开口130h中,以提高与电连接金属160的连接的可靠性。
图11是示出扇出型半导体封装件的另一示例的示意性截面图。
参照图11,根据另一示例实施例的扇出型半导体封装件100B包括框架110,框架110包括:第一绝缘层111a,设置为与连接结构140接触;第一布线层112a,嵌在第一绝缘层111a中并与连接结构140接触;第二布线层112b,设置在第一绝缘层111a的与嵌有第一布线层112a的一侧相对的一侧上;第一连接过孔层113a,贯穿第一绝缘层111a并且将第一布线层112a和第二布线层112b彼此电连接;第二绝缘层111b,设置在第一绝缘层111a的与嵌有第一布线层112a的一侧相对的一侧上;第三布线层112c,设置在第二绝缘层111b的与嵌有第二布线层112b的一侧相对的一侧上;以及第二连接过孔层113b,贯穿第二绝缘层111b并将第二布线层112b和第三布线层112c彼此电连接。第一布线层112a、第二布线层112b和第三布线层112c电连接到重新分布层142。例如,框架110包括更多数量的绝缘层、布线层和连接过孔层,使得连接结构140的设计可被进一步简化,以解决在形成连接结构140时产生的良率问题。其他描述与参照图9和图10描述的基本相同,并且在此将被省略。
图12是示出扇出型半导体封装件的另一示例的示意性截面图。
参照图12,与上述扇出型半导体封装件100A相比,根据本公开的另一示例性实施例的扇出型半导体封装件100C包括框架110,框架110包括:绝缘层111;第一布线层112a和第二布线层112b,分别设置在绝缘层111的两个表面上;以及连接过孔层113,贯穿绝缘层111并将第一布线层112a和第二布线层112b彼此电连接。第一布线层112a和第二布线层112b电连接到重新分布层142。如上所述,框架110可具有图案突出到两侧的结构。在这种情况下,框架110可使用覆铜层压板(CCL)等形成,这可致使简化的制造和优异的刚性。连接过孔层113可具有圆柱形状或沙漏形状。第一半导体芯片121可具有与第一包封剂130和第一布线层112a的分别与连接结构140接触的表面共面的第一有效表面。其他描述与参照图9至图11描述的基本相同,并且在此将被省略。
图13是示出扇出型半导体封装件的另一示例的示意性截面图。
参照图13,与上述扇出型半导体封装件100A相比,扇出型半导体封装件100D包括框架110,框架110包括:第一绝缘层111a;第一布线层112a和第二布线层112b,分别设置在第一绝缘层111a的两个表面上;第二绝缘层111b,设置在第一绝缘层111a的顶表面(基于附图)上,覆盖第一布线层112a;第三布线层112c,设置在第二绝缘层111b的顶表面(基于附图)上;第三绝缘层111c,设置在第一绝缘层111a的底表面(基于附图)上,覆盖第二布线层112b;第四布线层112d,设置在第三绝缘层111c的底表面(基于附图)上;以及第一连接过孔层113a、第二连接过孔层113b和第三连接过孔层113c,分别贯穿第一绝缘层111a、第二绝缘层111b和第三绝缘层111c,并且将第一布线层112a、第二布线层112b、第三布线层112c和第四布线层112d电连接。例如,框架110可包括更多数量的绝缘层、布线层和连接过孔层,从而可进一步简化连接结构140的设计。另外,框架110可使用CCL等形成,这可致使简化的制造和优异的刚性。第一绝缘层111a的厚度可大于第二绝缘层111b和第三绝缘层111c中的每个的厚度。第一绝缘层111a可基本上具有相对较大的厚度以保持刚性,并且可引入第二绝缘层111b和第三绝缘层111c以形成更多数量的布线层112c和112d。第一绝缘层111a可包括覆铜层压板(CCL)或未包覆的CCL,并且第二绝缘层111b和第三绝缘层111c中的每个可包括半固化片或ABF,但是其材料不限于此。其他描述与参照图9至图12描述的基本相同,并且在此将被省略。
图14是示出扇出型半导体封装件的另一示例的示意性截面图。
参照图14,与上述扇出型半导体封装件100A相比,扇出型半导体封装件100E可包括:框架110,具有通孔110H并包括布线层112a和112b;以及第一半导体芯片121,设置在框架110的通孔110H中。第一半导体芯片121可具有第一有效表面和与第一有效表面相对的第一无效表面,在第一有效表面上设置有第一连接焊盘121P。扇出型半导体封装件100E还可包括覆盖第一半导体芯片121的至少一部分的第一包封剂130。第二半导体芯片122可设置在第一半导体芯片121的一个表面上,并且具有第二有效表面和与第二有效表面相对的第二无效表面,在第二有效表面上设置有第二连接焊盘122P。这里,第二无效表面可面对第一半导体芯片121的第一有效表面。
第一半导体芯片121和第二半导体芯片122可被布置为相对于垂直于堆叠方向的方向错位,使得第一连接焊盘121P可被暴露。
第一连接焊盘121P可通过第一线124电连接到一个或更多个布线层112a,并且第二连接焊盘122P可通过第二线125电连接到一个或更多个布线层112a,使得第一连接焊盘121P和第二连接焊盘122P可通过一个或更多个布线层112a彼此电连接。
扇出型半导体封装件100E还可包括第二包封剂150,第二包封剂150设置在框架110的一个表面上并覆盖第二半导体芯片122的至少一部分。
如上所述,可提供即使扇出型半导体封装件包括多个半导体芯片也可变薄并且具有较少的信号损耗的扇出型半导体封装件。
在本公开中,与附图的截面相关的术语“下侧”、“下部”、“下表面”等用于指示朝向半导体封装件的安装表面的方向,术语“上侧”、“上部”、“上表面”等用于指示与由术语“下侧”、“下部”、“下表面”等指示的方向相反的方向。然而,这些方向仅是为了便于解释而定义的,并且权利要求不受如上所述定义的方向的具体限制。
在说明书中,组件“连接”到另一组件的含义包括两个组件之间通过粘合层的间接连接以及两个组件之间的直接连接。此外,“电连接”意味着包括物理连接和物理断开。可理解的是,当用“第一”和“第二”提及元件时,该元件不由此受到限制。这些术语可仅用于将该元件与其它元件区分开的目的,并且可不限制元件的顺序或重要性。在一些情况下,在不脱离权利要求在此所阐述的范围的情况下,第一元件可被称作第二元件。类似地,第二元件也可被称作第一元件。
在此使用的术语“示例实施例”不是始终指相同的示例实施例,而是被提供以强调与另一示例实施例的特定特征或特性不同的特定特征或特性。然而,在此提供的示例实施例被认为能够通过彼此整体组合或者彼此部分组合来实现。例如,除非其中提供相反或相矛盾的描述,否则特定示例实施例中描述的一个元件即使其未在另一示例实施例中描述,也可被理解为与另一示例实施例相关的描述。
在此使用的术语仅用于描述示例实施例,而非限制本公开。在这种情况下,基于具体的上下文,除非必须另外解释,否则单数形式包括复数形式。
虽然以上已经示出和描述了示例实施例,但是对本领域技术人员将明显的是,在不脱离由所附权利要求限定的本公开的范围的情况下,可以进行修改和变型。
Claims (20)
1.一种扇出型半导体封装件,所述扇出型半导体封装件包括:
连接结构,包括一个或更多个重新分布层;
第一半导体芯片,设置在所述连接结构的第一表面上,并具有第一有效表面和与所述第一有效表面相对的第一无效表面,其中,在所述第一有效表面上设置有第一连接焊盘,并且所述第一有效表面面对所述连接结构的所述第一表面;
第一包封剂,设置在所述连接结构的所述第一表面上,覆盖所述第一半导体芯片的至少一部分;以及
第二半导体芯片,设置在所述连接结构的与所述第一表面相对的第二表面上,具有第二有效表面和与所述第二有效表面相对的第二无效表面,其中,在所述第二有效表面上设置有第二连接焊盘,并且所述第二无效表面面对所述连接结构的所述第二表面,
其中,所述第一连接焊盘通过所述连接结构的连接过孔电连接到所述一个或更多个重新分布层,
所述第二连接焊盘通过线电连接到所述一个或更多个重新分布层,并且
所述第一连接焊盘和所述第二连接焊盘通过所述一个或更多个重新分布层彼此电连接。
2.根据权利要求1所述的扇出型半导体封装件,其中,所述第一半导体芯片的所述第一有效表面与所述连接结构的所述第一表面接触,并且
所述第二半导体芯片的所述第二无效表面通过粘合剂附着到所述连接结构的所述第二表面。
3.根据权利要求1所述的扇出型半导体封装件,其中,所述第一半导体芯片的所述第一有效表面与所述第一包封剂的与所述连接结构的所述第一表面接触的表面共面。
4.根据权利要求1所述的扇出型半导体封装件,所述扇出型半导体封装件还包括:
框架,设置在所述连接结构的所述第一表面上,具有通孔并包括一个或更多个布线层,
其中,所述第一半导体芯片设置在所述通孔中,并且
所述第一包封剂覆盖所述框架的至少一部分并且设置在所述通孔的至少一部分中。
5.根据权利要求4所述的扇出型半导体封装件,所述扇出型半导体封装件还包括:
多个开口,贯穿所述第一包封剂的覆盖所述框架的下表面的至少一部分,其中,所述框架的所述下表面与所述框架的设置有所述连接结构的上表面相对,所述多个开口分别使设置在所述框架的所述下表面上的布线层的至少一部分暴露;以及
多个电连接金属,分别设置在所述多个开口中,每个所述电连接金属电连接到暴露的所述布线层。
6.根据权利要求5所述的扇出型半导体封装件,其中,所述多个电连接金属仅设置在扇出区域中,从垂直于堆叠方向的视角所述扇出区域包括除了设置所述第一半导体芯片的区域之外的区域。
7.根据权利要求4所述的扇出型半导体封装件,其中,所述框架包括:
第一绝缘层;
第一布线层,设置为与所述连接结构接触并嵌在所述第一绝缘层中;
第二布线层,设置在所述第一绝缘层的与所述第一绝缘层的嵌有所述第一布线层的上侧相对的下侧上;以及
第一连接过孔层,贯穿所述第一绝缘层并且将所述第一布线层和所述第二布线层彼此电连接,并且
所述第一布线层和所述第二布线层电连接到所述一个或更多个重新分布层。
8.根据权利要求7所述的扇出型半导体封装件,其中,所述第一半导体芯片的所述第一有效表面与所述第一绝缘层的与所述连接结构的所述第一表面接触的表面共面。
9.根据权利要求7所述的扇出型半导体封装件,其中,所述框架还包括:
第二绝缘层,设置在所述第一绝缘层的所述下侧上并覆盖所述第二布线层;
第三布线层,设置在所述第二绝缘层的与所述第二绝缘层的嵌有所述第二布线层的上侧相对的下侧上;以及
第二连接过孔层,贯穿所述第二绝缘层并将所述第二布线层和所述第三布线层彼此电连接,并且
所述第三布线层电连接到所述一个或更多个重新分布层。
10.根据权利要求7所述的扇出型半导体封装件,其中,所述第一绝缘层的设置为与所述连接结构的所述第一表面接触的表面相对于所述第一布线层的设置为与所述连接结构的所述第一表面接触的表面具有台阶。
11.根据权利要求4所述的扇出型半导体封装件,其中,所述框架包括:
第一绝缘层;
第一布线层和第二布线层,分别设置在所述第一绝缘层的两个表面上;以及
第一连接过孔层,贯穿所述第一绝缘层并将所述第一布线层和所述第二布线层彼此电连接,并且
所述第一布线层和所述第二布线层电连接到所述一个或更多个重新分布层。
12.根据权利要求11所述的扇出型半导体封装件,其中,所述框架还包括:
第二绝缘层,设置在所述第一绝缘层的一个表面上以覆盖所述第一布线层;
第三布线层,设置在所述第二绝缘层的与所述第二绝缘层的嵌有所述第一布线层的下侧相对的上侧上;
第二连接过孔层,贯穿所述第二绝缘层并将所述第一布线层和所述第三布线层彼此电连接;
第三绝缘层,设置在所述第一绝缘层的另一表面上以覆盖所述第二布线层;
第四布线层,设置在所述第三绝缘层的与所述第三绝缘层的嵌有所述第二布线层的上侧相对的下侧上;以及
第三连接过孔层,贯穿所述第三绝缘层并将所述第二布线层和所述第四布线层彼此电连接,并且
所述第三布线层和所述第四布线层电连接到所述一个或更多个重新分布层。
13.根据权利要求12所述的扇出型半导体封装件,其中,所述第一绝缘层的厚度大于所述第二绝缘层和所述第三绝缘层中的每个的厚度。
14.根据权利要求1所述的扇出型半导体封装件,所述扇出型半导体封装件还包括:
第二包封剂,设置在所述连接结构的所述第二表面上,覆盖所述第二半导体芯片和所述线中的每个的至少一部分。
15.根据权利要求1所述的扇出型半导体封装件,其中,所述第一半导体芯片和所述第二半导体芯片是同构集成电路芯片。
16.根据权利要求15所述的扇出型半导体封装件,其中,所述第一半导体芯片和所述第二半导体芯片是同构存储器芯片。
17.根据权利要求1所述的扇出型半导体封装件,所述扇出型半导体封装件还包括第二包封剂,所述第二包封剂设置在所述连接结构的所述第二表面上,覆盖所述第二半导体芯片的至少一部分。
18.根据权利要求17所述的扇出型半导体封装件,其中,所述第二包封剂覆盖所述第二半导体芯片的第二有效表面和侧表面,并且
所述第二包封剂覆盖所述线的至少一部分。
19.一种扇出型半导体封装件,所述扇出型半导体封装件包括:
框架,具有通孔并包括一个或更多个布线层;
第一半导体芯片,设置在所述框架的所述通孔中,具有第一有效表面和与所述第一有效表面相对的第一无效表面,其中,在所述第一有效表面上设置有第一连接焊盘;
第一包封剂,覆盖所述第一半导体芯片的至少一部分;以及
第二半导体芯片,设置在所述第一半导体芯片的一个表面上,具有第二有效表面和与所述第二有效表面相对的第二无效表面,其中,在所述第二有效表面上设置有第二连接焊盘,所述第二无效表面面对所述第一半导体芯片的所述第一有效表面,
其中,所述第一半导体芯片和所述第二半导体芯片被布置为相对于垂直于堆叠方向的方向错位,使得所述第一连接焊盘被暴露,
所述第一连接焊盘通过第一线电连接到所述一个或更多个布线层,
所述第二连接焊盘通过第二线电连接到所述一个或更多个布线层,并且
所述第一连接焊盘和所述第二连接焊盘通过所述一个或更多个布线层彼此电连接。
20.根据权利要求19所述的扇出型半导体封装件,所述扇出型半导体封装件还包括第二包封剂,所述第二包封剂设置在所述框架的一个表面上,并覆盖所述第二半导体芯片的至少一部分。
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DE102018132143B4 (de) * | 2018-12-13 | 2023-10-12 | Infineon Technologies Ag | Leiterplatte, Chip-Kühlgehäuse, Baugruppe und Verfahren zum Kühlen eines Halbleiterchips |
US11637054B2 (en) * | 2020-01-31 | 2023-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method of manufacturing the same |
CN113206072A (zh) * | 2020-01-31 | 2021-08-03 | 台湾积体电路制造股份有限公司 | 半导体封装 |
CN112164677A (zh) * | 2020-08-25 | 2021-01-01 | 珠海越亚半导体股份有限公司 | 一种线路预排布散热嵌埋封装结构及其制造方法 |
US20230139175A1 (en) * | 2021-11-01 | 2023-05-04 | Micron Technology, Inc. | Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same |
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