CN107408541B - 系统级封装扇出叠层架构以及工艺流程 - Google Patents

系统级封装扇出叠层架构以及工艺流程 Download PDF

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CN107408541B
CN107408541B CN201680012959.4A CN201680012959A CN107408541B CN 107408541 B CN107408541 B CN 107408541B CN 201680012959 A CN201680012959 A CN 201680012959A CN 107408541 B CN107408541 B CN 107408541B
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die
rdl
molding compound
package
conductive pillars
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CN107408541A (zh
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翟军
胡坤忠
K-Y·赖
庞蒙志
钟重华
S·Y·杨
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Apple Inc
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Apple Inc
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Abstract

描述了封装以及形成方法。在实施方案中，系统级封装(SiP)包括第一(130)再分配层(RDL)和第二(180)再分配层、以及附接到该第一RDL的正面和背面的多个裸片(110,150)。该第一RDL和第二RDL与从第一RDL的背面延伸到第二RDL的正面的多个导电柱(140)耦接在一起。

Description

系统级封装扇出叠层架构以及工艺流程
技术领域
本文所述的实施方案涉及半导体封装。更具体地，实施方案涉及系统级封装(SiP)结构及其制造方法。
背景技术
对便携式和移动电子设备诸如移动电话、个人数字助理(PDA)、数字相机、便携式播放器、游戏设备、和其他移动设备的当前市场需求要求将更多性能和特征集成到越来越小的空间中。结果，各种多裸片或部件封装解决方案诸如系统级封装(SiP)变得更加普及，以满足对较高裸片/部件密度设备的需求。存在用于将多个裸片布置在SiP中的许多不同的可能。例如，将裸片竖直集成在SiP结构中已演进到2.5D解决方案和3D解决方案。在2.5D解决方案中，多个裸片可在包括通孔以及扇出布线的内插器上粘结倒装芯片。在3D解决方案中，多个裸片可堆叠在SiP衬底上的彼此的顶部，并且与芯片外引线键合或焊料凸块连接在一起。
另外存在用于集成产品的各种程度的SiP集成。在一个具体实施中，多个小SiP被安装在较大SiP中，这被称为封装中封装(PiP)。在另一具体实施中，SiP被安装在另一个SiP的顶部上，这被称为堆叠封装(PoP)。SiP结构和PoP结构可被组装在内插器上，以扇出集成产品的电端子。
发明内容
描述了扇出系统级封装(SiP)结构及其制造方法。在实施方案中，封装包括第一(例如，顶部)再分配层(RDL)和附接到第一RDL的正面的第一(例如，顶部)裸片。第一RDL的再分配线沿第一裸片的底表面直接形成在第一接触垫上。第一模制化合物将第一裸片包封在第一RDL的正面上。第二(例如，底部)裸片的顶表面附接到第一RDL的背面。多个导电柱140从第一RDL的背面延伸到第二RDL的正面，而第二模制化合物将第二裸片和多个导电柱包封在第一RDL的背面与第二RDL的正面之间。多个导电凸块可被形成在第二RDL的背面上。
在实施方案中，第一模制化合物未完全覆盖第一裸片的顶表面。在实施方案中，第二模制化合物未完全覆盖与第二RDL相邻的第二裸片的底表面。在此配置中，这可允许减小封装的总体z高度。在裸片的接触垫上直接形成再分配线也可减小z高度。通过使用RDL的电子布线可另外有助于减小封装z高度。在实施方案中，第二RDL包括直接被形成在多个导电柱中的一个导电柱上的另一再分配线。
第二(底部)裸片可背向或向上朝向第一RDL。在实施方案中，第二裸片利用裸片附接膜而被附接到第一RDL。例如，此类第二裸片可以是背向的。第二RDL可包括直接形成在背向第二裸片的导电触点上的另一再分配线。在实施方案中，背向第二裸片的导电触点的底表面和导电柱阵列的底表面共面。
在实施方案中，第二裸片利用焊料凸块而被粘结到第一RDL。例如，此类第二裸片可以是面朝上的。在实施方案中，第二模制化合物未完全覆盖与第二RDL相邻的面朝上的第二裸片的底表面。
在实施方案中，第三裸片可附接到第二RDL的正面。该第三裸片可连同第二(底部)裸片和多个导电柱而被包封在模制化合物中。在实施方案中，第二RDL的另一再分配线沿第三裸片的底表面直接形成在第三接触垫上。
在实施方案中，一种形成扇出系统级封装的方法包括：将第一裸片(例如，顶部裸片)放置在承载衬底上；利用第一模制化合物来将第一裸片包封在承载衬底上；移除承载衬底；以及在第一模制化合物和第一裸片上形成第一再分配层(RDL)。第一RDL的再分配线可沿第一裸片的底表面直接形成在接触垫上。多个导电柱可形成在第一RDL的背面上，并且第二裸片附接到多个导电柱的周边内部的第一RDL的背面。第二裸片和多个导电柱可随后利用第二模制化合物来包封，随后在第二模制化合物和多个导电柱上形成第二RDL。在实施方案中，减小第一模制化合物的厚度以暴露第一裸片，并且任选地减小第一裸片的厚度。在实施方案中，在将第二裸片和多个导电柱包封在第二模制化合物中之后并且在形成第二RDL之前，第二模制化合物和多个导电柱的厚度减小。还任选地减小第二裸片的厚度。在实施方案中，开口被形成在第二模制化合物中，以在形成第二RDL之前暴露第二裸片的着陆垫。
形成第二RDL可包括在多个导电柱上直接形成多个再分配线。形成第二RDL可包括在第二裸片的接触垫上直接形成再分配线。在实施方案中，背向第二裸片利用粘合剂层而被附接到第一RDL。
在实施方案中，第二承载衬底可在形成封装期间使用。这可包括将第三裸片或部件放置在第二承载衬底上，并且利用第二模制化合物来将三裸片或部件包封在承载衬底上。在利用第二模制化合物来包封第二裸片、多个导电柱、以及第三裸片或部件之后移除第二承载衬底，随后在第三裸片或部件、第二模制化合物、以及多个导电柱上形成第二RDL。
附图说明
图1是根据实施方案的被安装在承载衬底上的多个裸片和部件的横截面侧视图图示。
图2是根据实施方案的被包封在模制化合物中的多个裸片和部件的横截面侧视图图示。
图3是根据实施方案的在移除承载衬底之后的重构结构的横截面侧视图图示。
图4是根据实施方案的在重构结构上形成顶部RDL的横截面侧视图图示。
图5是根据实施方案的在顶部RDL上形成导电柱的横截面侧视图图示。
图6A是根据实施方案的附接到顶部RDL的背向裸片的横截面侧视图图示。
图6B是根据实施方案的附接到顶部RDL的面朝上裸片的横截面侧视图图示。
图7A是根据实施方案的被包封在模制化合物中的背向裸片和多个导电柱的横截面侧视图图示。
图7B是根据实施方案的被包封在模制化合物中的面朝上的裸片和多个导电柱的横截面侧视图图示。
图8A是根据实施方案的具有暴露表面的包封的背向裸片和多个导电柱的横截面侧视图图示。
图8B是根据实施方案的选择性地图案化的模制化合物的横截面侧视图图示。
图9A是根据实施方案的选择性地图案化的模制化合物的横截面侧视图图示。
图9B是根据实施方案的具有暴露表面的包封的面朝上的裸片和多个导电柱的横截面侧视图图示。
图10是根据实施方案的包括顶部RDL和底部RDL的封装的横截面侧视图图示。
图11是根据实施方案的包括背向的底部裸片和具有暴露顶表面的顶部裸片的封装的横截面侧视图图示。
图12是根据实施方案的包括面朝上的底部裸片和具有暴露顶表面的顶部裸片的封装的横截面侧视图图示。
图13是根据实施方案的包括具有暴露顶表面的多个顶部裸片的封装的横截面侧视图图示。
图14-图16是根据实施方案的使用多个承载衬底来形成封装的方法的横截面侧视图图示。
具体实施方式
实施方案描述了扇出系统级封装(SiP)结构及其制造方法，尤其是利用扇出晶圆级封装(FOWLP)技术的方法。在各种实施方案中，参照附图来进行描述。然而，某些实施方案可在不存在这些具体细节中的一个或多个具体细节或者不与其他已知的方法和构型相结合的情况下被实施。在以下的描述中，示出许多具体细节诸如特定构型、尺寸工艺等，以提供对实施方案的透彻理解。在其他情况下，未对熟知的半导体工艺和制造技术进行特别详细地描述，以免不必要地模糊实施方案。整个说明书中所提到的“一个实施方案”是指结合实施方案所描述的特定特征、结构、构型或特性被包括在至少一个实施方案中。因此，整个说明书中多处出现短语“在一个实施方案中”不一定是指相同的实施方案。此外，特定特征、结构、构型或特性可以任何适当的方式组合在一个或多个实施方案中。
本文所使用的术语“在...之上”、“在...上方”、“至”、“在...之间”和“在...上”可指一层相对于其他层的相对位置。一层在另一层“之上”、“上方”或“上”或者键合“至”另一层或者与另一层“接触”可为直接与其他层接触或可具有一个或多个居间层。一层在多层“之间”可为直接与该多层接触或可具有一个或多个居间层。
在一个方面，实施方案描述了利用多个裸片的电子端子的扇出的再分配层(RDL)的SiP结构。此类配置可允许利用对应RDL来扇出每个个体裸片。而且，此类配置可允许相异裸片集成诸如逻辑/存储器(例如，专用集成电路(ASIC)/动态随机存取存储器(DRAM))，而无需在PoP和SiP集成中通常使用的附加硅或有机内插器。
具体地，在实施方案中，堆叠的裸片布置包括粘结到用于扇出的顶部再分配层(RDL)的正面的顶部裸片、以及粘结到顶部RDL的背面的底部裸片。顶部RDL位于具有多个导电柱的较低RDL上并且电耦接至该较低RDL。因此，实施方案描述了具有双面RDL布置的SiP结构，其中裸片附接到顶部RDL的正面和背面两者。在实施方案中，顶部RDL的再分配线沿顶部裸片的底表面直接形成在第一接触垫上。此类配置可允许通过消除顶部裸片的焊料凸块减小总封装z高度，例如如同传统倒装芯片附接工艺。在一个方面，实施方案描述了用于制造利用单个承载衬底的具有多个RDL的SiP结构的工艺流程。在此类工艺流程中，与多个承载衬底相反使用单个承载衬底允许在顶部裸片上直接形成顶部RDL，由此有益于z高度的整体减小。
在其他方面，实施方案描述了断开了在PoP解决方案中常见的裸片与竖直导体的厚度关联的双面RDL布置，其中厚度关联描述了底部裸片与底部裸片上方的布线层之间的对立高度。根据实施方案，此类对立高度可通过将底部裸片附接到顶部RDL的背面来消除，并且由此可减小总封装z高度。而且，在一些实施方案中，底部裸片厚度可在附接到顶部RDL之后变薄，进一步有利于总体封装z高度减小。类似地，根据实施方案，顶部裸片厚度还可变薄，进一步有利于总体z高度减小。
在下文描述和附图中，示出并描述了用于制造SiP结构的各种工艺流程。尽管在附图中示出了单个SiP结构，但是应当理解，根据FOWLP技术，这些可能是跨承载衬底或重构晶片/面板的重复结构。
现参考图1，横截面侧视图图示提供了多个裸片110和被安装在承载衬底102上的可选的部件116，诸如硅晶片、玻璃面板、金属面板等。承载衬底102可另外包括用于安装多个裸片和一个或多个部件的粘合剂层。在实施方案中，每个裸片110或部件116包括具有一个或多个暴露接触垫112的底表面113和另选的钝化层114。在实施方案中，裸片110可为逻辑部件、存储器、或其他裸片。在实施方案中，裸片110为存储器(例如，DRAM)裸片。部件116可为钝化设备，诸如电容器或电感器、MEMS设备、传感器等。
如图2所示，多个裸片110和一个或多个可选部件116随后被包封在承载衬底102上的第一模制化合物120中。例如，该第一模制化合物120可包括热固性交联树脂(例如，环氧树脂)，尽管其他材料可如已知那样用于电子封装中。包封可使用合适的技术诸如但不限于传递模制、压缩模制和层压来完成。如本文所使用的，“包封的”不要求所有表面被包封在模制化合物内。在图2所示的实施方案中，裸片110和部件116的横向侧被包封在模制化合物120中，并且模制化合物也被形成在最高裸片110的顶表面111上方，尽管不需要模制化合物覆盖最高裸片110或部件116的顶表面111。在实施方案中，模制化合物120跨承载衬底102为连续的，从而覆盖多组裸片110、与将随后被切割的独立SiP对应的一个或多个部件116。
包括任何可选的粘合剂层的承载衬底102随后可被移除，以暴露如图3所示的裸片110和可选部件116的底表面113，从而导致重构晶片或面板125的形成。给定制造方法，在实施方案中，第一模制化合物120的底表面122可与裸片110和一个或多个部件116的底表面113共面，并且因此与接触垫112和与裸片110的底表面113的钝化层114的暴露表面共面。
现在参考图4，第一再分配层(RDL)130被形成在图3的重构晶片/面板125上，其中第一RDL 130的正表面131被形成在第一模制化合物120和一个或多个裸片110以及一个或多个部件116上。第一RDL 130可包括单个再分配线132或多个再分配线132、以及电介质层138。第一RDL 130可通过逐层工艺形成，并且可使用此薄膜技术形成。在实施方案中，第一RDL 130具有小于50μm的总厚度，或更具体地小于30μm，诸如约20μm。在实施方案中，第一RDL 130包括嵌入式再分配线132(嵌入式迹线)。例如，再分配线132可通过首先形成种子层随后形成金属(例如，铜)图案来创建。另选地，再分配线可通过沉积(例如，溅射)和蚀刻来形成。再分配线132的材料可包括但不限于金属材料，诸如铜、钛、镍、金及其组合或合金。再分配线132的金属图案随后被嵌入任选地图案化的电介质层138中。电介质层138可为任何合适的材料，诸如氧化物或聚合物(例如，聚酰亚胺)。
在所示的实施方案中，再分配线132沿裸片110和部件116的底表面113直接形成在接触垫112上。更具体地，再分配线132的接触垫134直接形成在接触垫112上。在实施方案中，第一RDL 130的背面133包括接触垫或凸块下合金(UBM)垫。例如，UBM垫136B被形成用于与附加裸片粘结，并且UBM垫136A被形成作为种子层以用于导电柱140的生长，如图5中所示。导电柱140的材料可包括但不限于金属材料，诸如铜、钛、镍、金及其组合或合金。导电柱140可使用合适的处理技术来形成，并且可由各种合适的材料(例如，铜)和层形成。在实施方案中，导电柱140通过镀覆技术来形成，诸如使用图案化光刻胶层电镀来限定柱结构尺寸，随后移除该图案化光刻胶层。
现在参考图6A-图6B，一个或多个底部裸片150使用重构晶片/面板125作为承载而被附接到第一RDL 130的背面133。在特定实施方案中，裸片150为逻辑裸片，诸如ASIC裸片。在所示的实施方案中，裸片150附接到多个导电柱140的周边内部的第一RDL 130。根据实施方案中，底部裸片150可背向(图6A)第一RDL 130和重构晶片/面板125，或者向上(图6B)朝向第一RDL 130和重构晶片/面板125。
在图6A中所示的实施方案中，裸片150的顶表面151利用裸片附接膜160而被附接到第一RDL 130的背面133。在该配置中，裸片背向重构晶片/面板125。例如，可在切割第一RDL 130并附接到第一RDL 130之前将裸片附接膜160应用于裸片150的阵列。例如，裸片附接膜160可通过层压、印刷或分配而被应用。在实施方案中，裸片附接膜160由粘合剂材料形成。裸片附接膜160可另外地为用于热扩散的导热粘合剂。裸片附接膜160任选地可在裸片附接之后通过例如化学、热或紫外光而被固化。在图6A中所示的实施方案中，裸片150可能未直接电耦接到第一RDL 130。如图所示，包括钝化层154和导电触点152的裸片的底表面153面向远离第一RDL 130。在所示的实施方案中，导电触点152被形成作为柱，尽管这不是必须的。
在图6B中所示的实施方案中，裸片150的顶表面151利用导电凸块162诸如焊料凸块而被附接到第一RDL 130的背面133。在该配置中，裸片向上朝向重构晶片/面板125。裸片150的顶表面151包括导电触点152和钝化层154，并且裸片150直接电耦接到第一RDL 130，例如电耦接到着陆垫或UBM垫136B。在此类实施方案中，裸片的底表面153不包括任何导电触点152。
现在参考图7A-图7B，根据实施方案，底部裸片150和导电柱140被包封在第二模制化合物170中。第二模制化合物170可具有与第一模制化合物120相同的材料。图7A为在实施方案中利用第二模制化合物170进行包封之后的来自图6A的结构的示图。图7B为在实施方案中利用第二模制化合物170进行包封之后的来自图6B的结构的示图。在图7A-图7B所示的实施方案中，模制化合物170的背面171覆盖底部裸片150的底表面153、以及导电柱140的底表面141。然而，此类配置并非是必需的。实际上，裸片150的底表面和/或导电柱140的底表面可在包封之后暴露。
参考图8A，示出了实施方案，其中底部裸片150为背向，并且导电柱的底表面141和底部裸片150的导电触点152的底表面155被暴露。这可能是包封工艺的结果。这另选地可能是蚀刻或后磨的结果，例如通过化学机械抛光(CMP)。如上参考图6A所述的，导电触点152可被形成作为柱。柱形导电触点152的厚度可在蚀刻或后磨期间减小。在实施方案中，第二模制化合物170的背面171与导电柱140的背面以及导电触点152的表面155共面。
实施方案不限于其中裸片150的导电触点152的暴露表面155与第二模制化合物170的背面171共面的结构。图8B为模制和图案化过程的横截面侧视图图示。在所示的实施方案中，初始包封操作可使得模制化合物170在裸片150上方以及潜在地在导电柱140的上方展开。在包封之后，模制化合物170如图8B所示被图案化以形成开口172，从而暴露裸片150的导电触点152的表面155和/或导电柱140的底表面141。因此，不同于全局研磨或回蚀，可使用选择性的图案化技术诸如激光钻孔或化学蚀刻来暴露导电触点152和导电柱140。
现在参考图9A，其示出了其中裸片150向上朝向重构晶片/面板的实施方案。在此类实施方案中，模制化合物170使用合适的图案化技术而被选择性地图案化，以暴露导电柱140的底表面141。参考图9B，其示出了其中执行蚀刻或后磨操作(例如，CMP)以暴露导电柱140的底表面141。第二模制化合物170的背面171可与导电柱140的背面以及可选的裸片150的底表面153共面。蚀刻或后磨操作可另外减小第二模制化合物170、导电柱140、以及可选的裸片150的厚度。在此方面，此类厚度减小可转换为完整的SiP结构的整体z高度减小。
尽管分别示出了图6A-图6B、图7A-图7B、图8A-图8B和图9A-图9B，但是过程不必彼此排他并且在一些实施方案中可被组合，或者可具有变型。以图6A为例，其可被切割为单个单元并且被放置在承载衬底上。
现在参考图10，在具有背向底部裸片150的实施方案中，第二RDL 180被形成在第二模制化合物170的背面171、裸片150的导电触点152的暴露表面155、以及导电柱140的暴露底表面141上方。第二RDL 180可类似于第一RDL 130而形成，并且可包括单个或多个再分配线182。第二RDL 180可通过逐层工艺形成，并且可使用薄膜技术来形成。例如，第一RDL130和第二RDL 180可各自具有小于50μm的厚度，或更具体地小于30μm，诸如约20μm。
在实施方案中，再分配线182以及更具体地再分配线182的接触垫184可直接形成在导电触点152的暴露表面155以及导电柱140的暴露底表面141上。因此，裸片150利用再分配线182和形成第二RDL的电介质层188而被粘结到第二RDL 180。在其中裸片150向上朝向重构晶片/面板的实施方案中，再分配线182未直接形成在裸片150的导电触点152上，并且裸片150未直接电耦接到第二RDL 180，如下文参考图12进一步详细所述的。
根据实施方案，双面RDL布置可允许减小的总体封装厚度。例如，不必包括对立高度，其中导电柱140(竖直导体)将大体上高于底部裸片150。例如，不必包括适应在典型PoP解决方案中利用焊料球来将顶部封装粘结到底部封装的设计容限，其中传统焊料球高度约为100μm-200μm。而且，使用顶部和底部RDL允许电子端子的扇出的细线和空间定义具有比常用内插器大体较低的厚度。
在形成第二RDL 180之后，导电凸块190可附接到第二RDL 180的着陆垫186(其也可为UBM)以及分割的个体封装100或生长在其上。各种结构可用于导电凸块190。例如，导电凸块190可为附接的焊料球，如图所示，或者镀覆的柱。
向上直到该点，顶部裸片110的顶表面111已被示出为由第一模制化合物120的顶表面121覆盖。在图11-图13所示的实施方案中，至少一个裸片110或部件116的顶表面111被暴露并且未由第一模制化合物120覆盖。例如，这可有利于初始包封工艺，或者另选地通过蚀刻或后磨操作来完成，其可在初始包封工艺之后或者形成第二RDL 180之后执行。
图11为类似于参考图10所述和所示的具有背向底部裸片150的实施方案的横截面侧视图图示，其中至少一个裸片110或部件116的顶表面111被暴露并且未由第一模制化合物120覆盖。
图12为类似于参考图7B所述和所示的在形成第二RDL 180和导电凸块190之后具有向上朝向的底部裸片150的实施方案的横截面侧视图图示，其中至少一个裸片110或部件116的顶表面111被暴露并且未由第一模制化合物120覆盖。尽管未单独示出，但是第二RDL180可被形成在各种向上朝向的底部裸片150配置(包括但不限于图9A-图9B中所述和所示的那些配置)上方。
图13为包括具有未由第一模制化合物120的顶侧121覆盖的暴露顶表面111的多个顶部裸片110(或者另选地为部件116)的实施方案的横截面侧视图图示。尽管图13所示的特定实施方案示出了背向裸片150，但是此类实施方案同样与向上朝向的底部裸片150兼容。
应当理解，尽管参考图10-图13描述和示出了特定封装配置，但是实施方案并不限于此并且许多配置可彼此组合并且与本文所述的其他结构组合，尤其是其中此类组合可有助于总体封装z高度的减小。
现在参考图14-图16，根据利用附加承载衬底的实施方案来示出工艺流程。在上述实施方案中，所有裸片和部件已被描述和示出为附接到顶部RDL 130。现在参考图14，在实施方案中，类似于图6B中所示的结构的结构临时放置在承载衬底202上，在该承载衬底上先前已放置裸片250。裸片250可类似于前述的裸片150，包括具有暴露接触垫212和钝化层214的底表面213。裸片250还可利用类似于前述部件116的部件替换。
在转移到承载衬底202之后，底部裸片150,250和导电柱140利用第二模制化合物270而被包封。现在参考图16，承载衬底202被移除并且第二RDL 180可随后如前所述被形成作为再分配线182，并且更具体地，再分配线182的接触垫184直接形成在裸片250的接触垫212上。在形成第二RDL 180之后，导电凸块190可被附接并且各个SiP结构100如前所述被分割。
在利用实施方案的各个方面中，对本领域技术人员显而易见的是，对于形成包括多个再分配层的系统级封装扇结构，以上实施方案的组合或变型是可能的。尽管以特定于结构特征和/或方法行为的语言对实施方案进行了描述，但应当理解，所附权利要求并不一定限于所描述的特定特征或行为。所公开的特定特征和行为相反应当被理解为用于进行例示的权利要求的实施方案。

Claims (20)

1.一种封装，包括：
第一再分配层RDL，所述第一再分配层RDL包括至少一个电介质层和至少一个再分配线；
附接到第一RDL的正面的第一裸片，其中所述第一RDL的至少一个再分配线的第一再分配线沿所述第一裸片的底表面直接形成在第一接触垫上；
将所述第一裸片包封在所述第一RDL的所述正面上的第一模制化合物；
附接到所述第一RDL的背面的第二裸片的顶表面；
第二RDL；
从所述第一RDL的所述背面延伸到所述第二RDL的正面的多个导电柱；
将所述第二裸片、所述第一RDL和所述多个导电柱包封在所述第一RDL的所述背面和所述第二RDL的所述正面之间的第二模制化合物，其中所述第二模制化合物横向围绕所述第一RDL。
2.根据权利要求1所述的封装，还包括位于所述第二RDL的背面上的多个导电凸块。
3.根据权利要求1所述的封装，其中所述第一模制化合物未完全覆盖所述第一裸片的顶表面。
4.根据权利要求3所述的封装，其中所述第二模制化合物未完全覆盖与所述第二RDL相邻的所述第二裸片的底表面。
5.根据权利要求1所述的封装，其中所述第二RDL包括直接形成在所述多个导电柱中的一个导电柱上的第二再分配线。
6.根据权利要求5所述的封装，其中所述第二裸片利用裸片附接膜而被附接到所述第一RDL。
7.根据权利要求6所述的封装，其中所述第二RDL包括直接形成在所述第二裸片的导电触点上的第三再分配线。
8.根据权利要求6所述的封装，其中所述第二裸片的导电触点的底表面和导电柱阵列的底表面共面。
9.根据权利要求5所述的封装，其中所述第二裸片利用焊料凸块而被粘结到所述第一RDL。
10.根据权利要求9所述的封装，其中所述第二模制化合物未完全覆盖与所述第二RDL相邻的所述第二裸片的底表面。
11.根据权利要求9所述的封装，还包括附接到所述第二RDL的所述正面的第三裸片或部件，其中所述第二RDL的第三再分配线直接形成在所述第三裸片或部件的底表面上的第三接触垫上。
12.一种形成扇出系统级封装的方法：
将第一裸片放置在承载衬底上；
利用第一模制化合物来将所述第一裸片包封在所述承载衬底上；
移除所述承载衬底；
在所述第一模制化合物和所述第一裸片上形成第一再分配层RDL，所述第一再分配层RDL包括至少一个电介质层和至少一个再分配线，其中第一RDL的至少一个再分配线的再分配线沿所述第一裸片的底表面直接形成在接触垫上；
在所述第一RDL的背面上形成多个导电柱；
将第二裸片附接到所述多个导电柱的周边内部的所述第一RDL的所述背面；
利用第二模制化合物来包封所述第二裸片、所述第一RDL和所述多个导电柱，其中所述第二模制化合物横向围绕所述第一RDL；以及
在所述第二模制化合物和所述多个导电柱上形成第二RDL。
13.根据权利要求12所述的方法，其中形成所述第二RDL包括在所述多个导电柱上直接形成多个再分配线。
14.根据权利要求12所述的方法，其中形成所述第二RDL包括在所述第二裸片的接触垫上直接形成再分配线。
15.根据权利要求12所述的方法，还包括利用粘合剂层来将所述第二裸片附接到所述第一RDL。
16.根据权利要求12所述的方法，还包括减小所述第一模制化合物的厚度，以暴露所述第一裸片。
17.根据权利要求12所述的方法，还包括在将所述第二裸片和所述多个导电柱包封在所述第二模制化合物中之后并且在形成所述第二RDL之前，减小所述第二模制化合物和所述多个导电柱的厚度。
18.根据权利要求12所述的方法，还包括在所述第二模制化合物中形成开口，以在形成所述第二RDL之前暴露所述第二裸片的着陆垫。
19.根据权利要求12所述的方法，还包括：
将第三裸片或部件放置在第二承载衬底上；以及
利用所述第二模制化合物来将所述第三裸片或部件包封在所述承载衬底上。
20.根据权利要求19所述的方法，还包括：
在利用所述第二模制化合物来包封所述第二裸片、所述多个导电柱、以及所述第三裸片或部件之后移除所述第二承载衬底；以及
在所述第三裸片或部件、所述第二模制化合物、和所述多个导电柱上形成所述第二RDL。
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