TWI646655B - 薄低翹曲扇出封裝中之雙側安裝記憶體整合 - Google Patents

薄低翹曲扇出封裝中之雙側安裝記憶體整合 Download PDF

Info

Publication number
TWI646655B
TWI646655B TW105108575A TW105108575A TWI646655B TW I646655 B TWI646655 B TW I646655B TW 105108575 A TW105108575 A TW 105108575A TW 105108575 A TW105108575 A TW 105108575A TW I646655 B TWI646655 B TW I646655B
Authority
TW
Taiwan
Prior art keywords
die
package
rdl
molding compound
dies
Prior art date
Application number
TW105108575A
Other languages
English (en)
Other versions
TW201703229A (zh
Inventor
軍 翟
胡坤忠
仲崇華
孟枝 龐
梁世暎
Original Assignee
蘋果公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 蘋果公司 filed Critical 蘋果公司
Publication of TW201703229A publication Critical patent/TW201703229A/zh
Application granted granted Critical
Publication of TWI646655B publication Critical patent/TWI646655B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Semiconductor Memories (AREA)

Abstract

本發明描述封裝及形成方法。在一實施例中，一種封裝包括直接地形成於一頂部晶粒上之一重佈層(RDL)，及安裝於該RDL之一背表面上之一底部晶粒。

Description

薄低翹曲扇出封裝中之雙側安裝記憶體整合
本文中所描述之實施例係關於半導體封裝。更特定而言，實施例係關於扇出封裝及製造方法。
針對諸如行動電話、個人數位助理(PDA)、數位攝影機、攜帶型播放器、遊戲裝置及其他行動裝置之攜帶型及行動電子裝置的當前市場需求要求將較多效能及特徵整合至愈來愈小之空間中。因此，諸如系統級封裝(SiP)及疊層封裝(PoP)之各種多晶粒封裝解決方案已變得愈來愈風行以滿足針對較高晶粒/組件密度裝置之需求。在一個實施方案中，記憶體晶粒或封裝(例如，動態隨機存取記憶體(DRAM))堆疊於邏輯晶粒或封裝(例如，特殊應用積體電路(ASIC))或系統單晶片(SoC)之頂部上。隨著攜帶型及行動電子裝置之市場的發展，要求記憶體晶粒或封裝具有較大記憶體能力。在一個實施方案中，多個記憶體晶粒經垂直地堆疊以增加頂部記憶體晶粒封裝中之記憶體。堆疊式晶粒可使用導線接合件或矽穿孔而互連。
本發明描述雙側封裝結構及製造方法。在一實施例中，一種封裝包括接合至一重佈層(RDL)之一前側之一或多個第一晶粒，及安裝於該RDL之一背側上之一或多個第二晶粒。舉例而言，該第二晶粒可 使用一合適表面黏著技術而安裝，該技術係諸如覆晶及導電凸塊，諸如焊料凸塊。該RDL之一第一重佈線直接地形成於一第一晶粒之一第一接觸墊上，且一第一模製化合物將該一或多個第一晶粒囊封於該RDL之該前側上。複數個導電柱自該RDL之該背側延伸，且一第二模製化合物將該一或多個第二晶粒及該複數個導電柱囊封於該RDL之該背側上。複數個導電凸塊可定位於該複數個導電柱上。
根據實施例，多種組態可用以縮減封裝高度。舉例而言，該第一模製化合物可不完全地覆蓋該一或多個第一晶粒之一頂部表面，及/或該第二模製化合物可不完全地覆蓋該一或多個第二晶粒之一底部表面。該一或多個第一晶粒之該頂部表面與該模製化合物之一頂部表面可共平面。同樣地，該一或多個第二晶粒之一底部表面、該複數個導電柱之一底部表面及/或該第二模製化合物之一底部表面可共平面。舉例而言，該等共平面表面可藉由一蝕刻或背面研磨操作而達成。在一特定實施例中，該一或多個頂部及底部晶粒為記憶體晶粒。
在一實施例中，一種扇出封裝係藉由以下操作而形成：將一或多個第一晶粒置放於一載體基板上，且運用一第一模製化合物將該一或多個第一晶粒囊封於該載體基板上。接著移除該載體基板，且在該第一模製化合物及該第一晶粒上形成一重佈層(RDL)，其中該RDL之一重佈線沿著該第一晶粒之一底部表面直接地形成於一接觸墊上。在該RDL之一背側上形成複數個柱，且在該複數個導電柱之一周界內部將一或多個第二晶粒安裝於該RDL之該背側上。舉例而言，該第二晶粒可使用一合適表面黏著技術而安裝，該技術係諸如覆晶及導電凸塊，諸如焊料凸塊。運用一第二模製化合物來囊封該一或多個第二晶粒，且可在該複數個導電柱上形成一或多個導電凸塊。
根據實施例，多種組態可用以縮減封裝高度。舉例而言，可縮減該第一模製化合物之一厚度以曝露該一或多個第一晶粒。此外，根 據一實施例，亦可縮減該第一晶粒之一厚度，從而得到一平面頂部封裝表面。同樣地，可縮減該第二模製化合物之一厚度以曝露該一或多個第二晶粒。此外，亦可縮減該第二晶粒之一厚度，從而得到一平面底部封裝表面。
100‧‧‧扇出封裝
102‧‧‧載體基板
110‧‧‧第一(頂部)晶粒
111‧‧‧第一(頂部)晶粒之頂部表面
112‧‧‧接觸墊
113‧‧‧第一(頂部)晶粒之底部表面
114‧‧‧鈍化層
120‧‧‧第一模製化合物
121‧‧‧第一模製化合物之頂部表面
122‧‧‧第一模製化合物之底部表面
125‧‧‧經重建晶圓/面板
130‧‧‧重佈層(RDL)
131‧‧‧RDL之前表面
132‧‧‧重佈線
133‧‧‧RDL之背側
134‧‧‧接觸墊
136A‧‧‧凸塊下金屬層(UBM)墊
136B‧‧‧凸塊下金屬層(UBM)墊
138‧‧‧介電層
140‧‧‧導電柱
141‧‧‧導電柱之底部表面
150‧‧‧第二(底部)晶粒
151‧‧‧第二(底部)晶粒之頂部表面
152‧‧‧導電接點
153‧‧‧第二(底部)晶粒之底部表面
154‧‧‧鈍化層
162‧‧‧導電凸塊
170‧‧‧第二模製化合物
171‧‧‧第二模製化合物之底部表面
172‧‧‧開口
190‧‧‧導電凸塊
192‧‧‧電絕緣材料
1010‧‧‧操作
1020‧‧‧操作
1030‧‧‧操作
1040‧‧‧操作
1050‧‧‧操作
1060‧‧‧操作
圖1為根據一實施例之置放於載體基板上之複數個晶粒的橫截面側視圖說明。
圖2為根據一實施例之囊封於第一模製化合物中之複數個晶粒的橫截面側視圖說明。
圖3為根據一實施例之在移除載體基板之後的經重建結構的橫截面側視圖說明。
圖4為根據一實施例之形成於經重建結構上之RDL的橫截面側視圖說明。
圖5A為根據一實施例之形成於經重建結構上之RDL的橫截面側視圖說明。
圖5B為根據一實施例之形成於經重建結構上之RDL的特寫橫截面側視圖說明。
圖6為根據一實施例之導電柱於RDL上之形成的橫截面側視圖說明。
圖7A至圖7B為根據一實施例之將複數個晶粒安裝於RDL上的橫截面側視圖說明。
圖8為根據一實施例之施加底填充物材料的特寫橫截面側視圖說明。
圖9為根據一實施例之經囊封底部晶粒及複數個導電柱的橫截面側視圖說明。
圖10為根據一實施例之具有經曝露底部表面的經囊封之複數個 導電柱的橫截面側視圖說明。
圖11為根據一實施例之具有經曝露底部表面之經囊封底部晶粒及具有經曝露底部表面之複數個導電柱的橫截面側視圖說明。
圖12為根據一實施例之經選擇性圖案化模製化合物的橫截面側視圖說明。
圖13為根據一實施例之包括複數個導電柱之底部表面上的導電凸塊之經單體化封裝的橫截面側視圖說明。
圖14為根據一實施例之包括經薄化頂部及底部晶粒以及模製化合物之經單體化封裝的橫截面側視圖說明。
圖15為根據一實施例之說明形成扇出封裝之製程的流程圖。
實施例描述扇出封裝及製造方法，特別是利用扇出晶圓級封裝(FOWLP)技術之方法。晶粒向下扇出技術為可用於處理針對較高晶粒/組件密度裝置之需求的通用扇出晶圓級封裝(FOWLP)技術。FOWLP可需要以模製化合物將晶粒囊封於載體基板上、移除載體基板，且接著在晶粒及模製化合物之上建置重佈層(RDL)。模製化合物提供用於電扇出且視情況用於較高I/O計數之額外區域。
實施例描述雙側安裝扇出封裝，其中晶粒安裝於RDL之兩個側上。在各種態樣中，根據所描述實施例之封裝組態可允許總封裝z高度縮減、增加裝置密度(或記憶體容量)，及/或封裝翹曲控制，其可另外允許在受控翹曲公差內形成較寬封裝。
在一實施例中，一種封裝包括接合至RDL之前側之一或多個第一(頂部)晶粒，其中RDL之第一重佈線直接地形成於該等頂部晶粒中之一者之第一接觸墊上。第一模製化合物將一或多個頂部晶粒囊封於RDL之前側上。一或多個第二(底部)晶粒可接合至RDL之背側，且複數個導電柱自RDL之背側延伸。舉例而言，一或多個底部晶粒可在複 數個導電柱之周邊內。第二模製化合物將一或多個底部晶粒囊封於RDL之背側上。
在一項態樣中，實施例描述一種可允許總封裝z高度縮減之雙側安裝扇出封裝結構。舉例而言，直接地在頂部晶粒上形成RDL可允許藉由消除與表面黏著製程相關聯之支座高度(諸如與習知覆晶附接製程相關聯之焊料凸塊高度)來縮減總封裝z高度。總封裝z高度之縮減可另外歸因於RDL用於扇出之使用，該高度可顯著地薄於習知聚合物或層壓基板，且允許消除通常用於PoP及SiP整合中之額外矽或有機插入件。此外，總封裝z高度縮減可歸因於斷開底部晶粒與通常在PoP解決方案中發現之垂直導體之厚度相關性，其中此厚度相關性描述底部晶粒與底部晶粒上方之佈線層之間的支座高度。根據實施例，藉由將底部晶粒安裝至RDL之背側來消除此支座高度。總封裝z高度縮減可進一步歸因於面對RDL之一或多個頂部及底部晶粒。在此組態中，可有可能背面研磨頂部晶粒及底部晶粒中之任一者或兩者以及模製化合物之厚度，從而進一步有助於總封裝z高度縮減。
在又一態樣中，控制頂部晶粒及底部晶粒以及模製化合物之厚度的能力可允許對封裝翹曲的一定程度之控制。因此，根據實施例，封裝z高度之控制另外允許封裝翹曲之控制。控制封裝翹曲之能力可另外允許形成較寬封裝，以及允許將多個晶粒並列地定位於RDL之前側及背側上。
實施例可應用於諸如且不限於低功率及/或高I/O寬度記憶體架構之應用中。實施例可藉由使用RDL及直接晶片附接來實現至相鄰功能單元(例如，SOC、晶片組等等)之短雙資料速率(DDR)通道。實施例可特別適用於在包括高速度及寬I/O寬度之目標效能下需要低功率DDR的行動應用。採用高端應用係可能的，其中針對寬I/O互連具有精細RDL重佈線寬度及間隔，且按比例增加適當記憶體密度。可藉由 在RDL之前部及背部上雙重安裝記憶體晶粒來繼承按比例調整性。在應用中，封裝可整合至PoP結構中，例如，作為PoP堆疊中之頂部記憶體封裝，以及用於直接地安裝至系統板上。可另外經由使可相同之封裝單元以彼此疊加之方式堆疊來促進朝向高密度(雙順位)之進一步按比例增加。
在各種實施例中，參考圖來進行描述。然而，可在沒有此等特定細節中之一或多者的情況下或與其他已知方法及組態組合而實踐某些實施例。在以下描述中，闡述諸如特定組態、尺寸及製程等等之眾多特定細節，以便提供對實施例之透徹理解。在其他情況下，尚未特定詳細地描述熟知之半導體製程及製造技術以免不必要地混淆實施例。貫穿本說明書而對「一個實施例」之參考意謂結合該實施例所描述之特定特徵、結構、組態或特性包括於至少一個實施例中。因此，貫穿本說明書之各種地方處的片語「在一個實施例中」之出現未必係指同一實施例。此外，可在一或多個實施例中以任何合適方式組合特定特徵、結構、組態或特性。
如本文中所使用之術語「上方」、「之上」、「至」、「之間」及「上」可指一個層相對於其他層之相對位置。在另一層「上方」、「之上」或「上」或接合「至」另一層或與另一層「接觸」之一個層可直接地與另一層接觸或可具有一或多個介入層。在若干層「之間」的一個層可直接地與該等層接觸或可具有一或多個介入層。
現在參看圖1，提供安裝於載體基板102(諸如矽晶圓、玻璃面板、金屬面板等等)上之複數個第一(頂部)晶粒110的橫截面側視圖說明。載體基板102可另外包括用於安裝複數個晶粒之黏接層。在一實施例中，每一晶粒110包括具有一或多個經曝露接觸墊112之底部表面113，且視情況包括鈍化層114。在一特定實施例中，晶粒110為諸如但不限於動態隨機存取記憶體(DRAM)之記憶體晶粒。晶粒110可為具 有相同大小、形狀及記憶體容量之相同晶粒。替代地，晶粒110可為不同類型之晶粒，或為(例如)具有不同大小、形狀及/或容量之記憶體晶粒。
雖然實施例描述扇出封裝，且尤其是扇出記憶體封裝，但實施例未必限於記憶體晶粒，且所描述之特定封裝組態及序列可用於其他封裝且包括不同類型之晶粒(例如，邏輯)或組件，諸如包括電容器或電感器、微機電系統(MEMS)裝置、感測器等等之被動裝置。
如圖2所展示，接著以第一模製化合物120將複數個晶粒110囊封於載體基板102上。舉例而言，第一模製化合物120可包括熱固性交聯樹脂(例如，環氧樹脂)，但可使用其他材料，如電子封裝中所知。可使用諸如但不限於轉注模製、壓縮模製及層壓之合適技術來實現囊封。如本文中所使用，「囊封」並不要求將所有表面包裝於模製化合物內。在圖2所說明之實施例中，晶粒110之橫向側包裝於模製化合物120中，且模製化合物120之頂部表面121亦形成於最高晶粒110之頂部表面111之上，但並不要求模製化合物覆蓋最高晶粒110之頂部表面111。在一實施例中，模製化合物120橫越載體基板102係連續的，從而覆蓋隨後將(例如)沿著點線而單體化以形成單獨封裝之晶粒110之複數個分組。
根據實施例，每一封裝中包括一或多個晶粒110。在一實施例中，每一封裝中包括複數個晶粒110。如下文進一步詳細地所描述，控制RDL之相對側上之晶粒及模製化合物之厚度且因此控制封裝翹曲的能力可另外允許形成較寬封裝，以及允許將多個晶粒並列地定位於RDL之前側及背側上。
可接著移除包括任何選用黏接層之載體基板102以曝露晶粒110之底部表面113，如圖3所說明，從而引起形成經重建晶圓或面板125。在該製造方法的情況下，在一實施例中，第一模製化合物120之底部 表面122可與晶粒110之底部表面113共平面，且因此與接觸墊112之經曝露表面共平面且視情況與對應於晶粒110之底部表面113的鈍化層114共平面。
現在參看圖4，重佈層(RDL)130形成於圖3之經重建晶圓/面板125上，其中RDL 130之前表面131形成於第一模製化合物120及一或多個晶粒110上。RDL 130可包括單一重佈線132或多個重佈線132及介電層138。RDL 130可藉由逐層製程而形成，且可使用薄膜技術而形成。在一實施例中，RDL 130包括嵌入式重佈線132(嵌入式跡線)。舉例而言，可藉由首先形成晶種層，隨後形成金屬(例如，銅)圖案來產生重佈線132。替代地，可藉由沈積(例如，濺鍍)及蝕刻來形成重佈線。重佈線132之材料可包括但不限於諸如銅、鈦、鎳、金及其組合或合金之金屬材料。接著將重佈線132之金屬圖案嵌入於視情況被圖案化之介電層138中。介電層138可為諸如氧化物或聚合物(例如，聚醯亞胺)之任何合適材料。
根據實施例，RDL 130可具有小於習知有機或層壓基板之厚度。舉例而言，習知六層有機或層壓基板可具有300μm至500μm之厚度。RDL 130之厚度可由導電重佈線132及介電層138之數目以及形成方式判定。根據實施例，導電重佈線可具有大約3μm至10μm之厚度，且介電層具有2μm至5μm之厚度。與習知有機或層壓基板相比較，根據實施例之RDL可另外允許較窄線間隔寬度(精細間距)及較細線。在一實施例中，RDL 130之總厚度小於50μm，或更尤其為大約30μm或更小，諸如大約20μm。在所說明實施例中，重佈線132沿著晶粒110之底部表面113直接地形成於接觸墊112上(例如，無凸塊形成)。更具體而言，重佈線132之接觸墊134直接地形成於接觸墊112上。
現在參看圖5A，在一實施例中，RDL 130之背側133包括諸如凸 塊下金屬層(UBM)墊136A、136B之著陸墊。圖5B中說明RDL 130之特寫說明，其包括UBM墊136A、136B，及直接地形成於晶粒110之接觸墊112上的重佈線132之接觸墊134。舉例而言，UBM墊136A可具有諸如大約200μm之較大寬度以用於後續導電柱凸塊形成，而UBM墊136B可具有諸如大約50μm之相對較小寬度以用於後續晶粒附接。
參看圖6，導電柱140形成於UBM墊136A之頂部上。導電柱140之材料可包括但不限於諸如銅、鈦、鎳、金及其組合或合金之金屬材料。導電柱140可使用合適處理技術而形成，且可由多種合適材料(例如，銅)及層形成。在一實施例中，導電柱140係藉由鍍覆技術而形成，諸如使用經圖案化光阻層進行電鍍以界定柱結構尺寸，隨後移除經圖案化光阻層。
現在參看圖7A至圖7B，一或多個第二(底部)晶粒150可使用經重建晶圓/面板125作為載體而附接至RDL 130之背側133。在一特定實施例中，晶粒150為記憶體晶粒。舉例而言，晶粒150可為與晶粒110相同或不同之記憶體晶粒，且可各者具有相同或不同大小、形狀及/或記憶體容量。在所說明實施例中，一或多個晶粒150在複數個導電柱140之周邊內安裝於RDL 130上。舉例而言，晶粒150可使用諸如覆晶之表面黏著技術而安裝。圖7A至圖7B將導電柱140說明為高於晶粒150厚度。然而，晶粒150可具有與導電柱140高度之近似相同的厚度，或晶粒150可厚於導電柱140高度。
在所說明實施例中，晶粒150之頂部表面151係運用導電凸塊162(諸如焊料凸塊或螺桿凸塊)而附接至(例如，表面黏著至)RDL 130之背側133。晶粒150之頂部表面151包括導電接點152及鈍化層154，且晶粒150直接地電耦接至RDL 130，例如，電耦接至諸如UBM墊136B之著陸墊。在此組態中，每一晶粒150面向至經重建晶圓/面板125。非導電膏(NCP)或非導電膜(NCF)可視情況橫向地環繞導電凸塊162。 在此實施例中，可使用熱壓縮來實現接合。導電凸塊162可由諸如金或焊料材料之材料形成，該材料可與諸如UBM墊136B之著陸墊形成接合接頭(例如，金屬間化合物或合金)。在一實施例中，晶粒150係運用直接地在晶粒150之導電凸塊162與諸如RDL 130之UBM墊136之著陸墊之間的各向異性導電膜(ACF)而表面黏著於RDL 130之背側133上。在一實施例中，晶粒150之底部表面153不包括任何導電接點152。
現在參看圖8，電絕緣材料192可視情況施加於晶粒150與RDL 130之間。舉例而言，材料192可為用於覆晶接合之毛細管型底填充物(CUF)材料，諸如瞬間固化底填充物。例示性底填充物材料包括但不限於聚合物或環氧樹脂。材料192亦可為非導電膏。在其他實施例中，不使用CUF製程。
現在參看圖9，根據實施例，以第二模製化合物170囊封一或多個第二(底部)晶粒150及導電柱140。第二模製化合物170可為與第一模製化合物120相同之材料。在所說明實施例中，模製化合物170之底部表面171覆蓋晶粒150之底部表面153，以及導電柱140之底部表面141。然而，無需此組態。實際上，可在囊封製程期間或在囊封之後曝露晶粒150之底部表面及/或導電柱140之底部表面。在一實施例中，使用經模製底填充物(MUF)製程，其中使用第二模製化合物170以填充晶粒150與RDL 130之間的空間，而非CUF材料。
參看圖10，說明導電柱140之底部表面141被曝露且未由第二模製化合物170覆蓋的實施例。此可為囊封製程之結果。此可替代地為(例如)藉由化學機械拋光(CMP)進行之蝕刻或背面研磨之結果。可視情況在蝕刻或背面研磨期間縮減導電柱140之厚度。在一實施例中，第二模製化合物170之底部表面171係與導電柱140之底部表面141共平面。
雖然晶粒150之底部表面153在圖10中被說明為由第二模製化合 物170覆蓋，但無需如此。舉例而言，在圖11所說明之實施例中，晶粒150之底部表面153被曝露且未由第二模製化合物覆蓋。此可為囊封製程之結果。此可替代地為(例如)藉由CMP進行之蝕刻或背面研磨之結果。可視情況在蝕刻或背面研磨期間縮減導電柱140、第二模製化合物170及/或晶粒150之厚度。在一實施例中，第二模製化合物170之底部表面171係與導電柱140之底部表面141及晶粒150之底部表面153共平面。根據實施例，控制RDL之相對側上之晶粒及模製化合物之厚度的能力允許形成較薄封裝。控制該厚度可另外允許對封裝翹曲之額外控制。
實施例並不限於導電柱140由於囊封製程或背面研磨而被曝露的結構。圖12為模製及圖案化程序之橫截面側視圖說明。在所說明實施例中，初始囊封操作可引起模製化合物170遍及導電柱140且視情況遍及晶粒150之底部表面153而散佈。在囊封之後，模製化合物170經圖案化以形成開口172來曝露導電柱140之底部表面141。因此，可使用選擇性圖案化技術(諸如雷射鑽孔或化學蝕刻)以曝露導電柱140，而非全域地研磨或回蝕。
雖然已分離地描述圖10至圖12，但該等製程未必彼此排斥且在一些實施例中可進行組合，或可具有變化。
在形成及處理第二模製化合物170之後，可將導電凸塊190附接至或生長於導電柱140之經曝露底部表面141及如圖13所說明而單體化之個別封裝100上。針對導電凸塊190可使用多種結構。舉例而言，導電凸塊190可為經附接焊料凸塊(如所說明)或經鍍覆柱。
直至此時，已將晶粒110之頂部表面111說明為由第一模製化合物120之頂部表面121覆蓋。在圖14所說明之實施例中，至少一個晶粒110之頂部表面111被曝露且未由第一模製化合物120覆蓋。舉例而言，此可歸因於初始囊封製程，或替代地經由蝕刻或背面研磨操作而 實現，該蝕刻或背面研磨操作可在運用第一模製化合物120之初始囊封製程之後執行，或在運用第二模製化合物170之囊封之後執行。在一實施例中，第一模製化合物120之頂部表面121係與晶粒110之頂部表面111共平面。根據實施例，控制RDL之相對側上之晶粒及模製化合物之厚度的能力允許形成較薄封裝。由於此封裝在RDL 130之兩個側上具有囊封材料及矽內容物，故控制該厚度可另外允許對封裝翹曲之額外控制。除了控制厚度以外，囊封材料亦可用以經由使用在RDL 130之兩個側上具有不同屬性及/或厚度之材料來控制封裝翹曲。因此，可達成極低高溫翹曲(~20μm或更小)封裝。在一實施例中，封裝100具有大約300μm或更小之總厚度(或z高度)，排除導電凸塊190之高度。舉例而言，圖14中之頂部表面111、121與底部表面141、153、171之間的距離可為大約300μm或更小。
圖15為根據一實施例之說明形成扇出封裝100(諸如雙側安裝扇出記憶體封裝)之方法的流程圖。在操作1010處，運用第一模製化合物120將第一晶粒110囊封於載體基板102上。接著，在操作1020處，移除載體基板120，且在操作1030處，在第一模製化合物120及第一晶粒110上形成RDL 130。舉例而言，可形成RDL 130，使得RDL之重佈線132沿著第一晶粒110之底部表面113直接地形成於接觸墊112上。在操作1040處，在RDL之背側133上形成複數個導電柱140，且在操作1050處，在複數個導電柱140之周界內將第二晶粒150安裝於RDL 130之背側133上。接著，在操作1060處，運用第二模製化合物170來囊封第二晶粒150及複數個導電柱140。在利用實施例之各種態樣時，對於熟習此項技術者而言將顯而易見，用於形成扇出封裝的以上實施例之組合或變化(包括但不限於上文所說明及描述之變化中之任一者)係可能的。儘管已用特定於結構特徵及/或方法動作之語言而描述實施例，但應理解，所附申請專利範圍未必限於所描述之特定特徵或動 作。所揭示之特定特徵及動作代替地應被理解為有用於說明的申請專利範圍之實施例。

Claims (27)

  1. 一種封裝，其包含：一重佈層(RDL)；一第一晶粒，其接合至該RDL之一前側，其中該RDL之一第一重佈線形成於該第一晶粒之一第一接觸墊上；一第一模製化合物，其將該第一晶粒囊封於該RDL之該前側上；一第二晶粒，其安裝於該RDL之一背側上；複數個導電柱，其自該RDL之該背側延伸；及一第二模製化合物，其將該第二晶粒、該RDL及該複數個導電柱囊封於該RDL之該背側上，其中該第二模製化合物完全橫向環繞該RDL。
  2. 如請求項1之封裝，其進一步包含在該複數個導電柱上之複數個導電凸塊。
  3. 如請求項1之封裝，其中該第一模製化合物不完全地覆蓋該第一晶粒之一頂部表面。
  4. 如請求項1之封裝，其中該第二模製化合物不完全地覆蓋該第二晶粒之一底部表面。
  5. 如請求項4之封裝，其中該第一模製化合物不完全地覆蓋該第一晶粒之一頂部表面，且該第二模製化合物不完全地覆蓋該第二晶粒之一底部表面。
  6. 如請求項1之封裝，其中該第一晶粒之一頂部表面與該第一模製化合物之一頂部表面共平面。
  7. 如請求項1之封裝，其中該第二晶粒之一底部表面、該複數個導電柱之一底部表面與該第二模製化合物之一底部表面共平面。
  8. 如請求項1之封裝，其中：該第一晶粒之一頂部表面與該第一模製化合物之一頂部表面共平面；且該第二晶粒之一底部表面、該複數個導電柱之一底部表面與該第二模製化合物之一底部表面共平面。
  9. 如請求項8之封裝，其中該第一晶粒及該第二晶粒為記憶體晶粒。
  10. 如請求項1之封裝，其中該第二晶粒係運用一導電凸塊而接合至該RDL。
  11. 如請求項1之封裝，其進一步包含接合至該RDL之該前側之複數個第一晶粒，及安裝於該RDL之該背側上之複數個第二晶粒。
  12. 如請求項11之封裝，其中：該複數個第一晶粒之一頂部表面與該第一模製化合物之一頂部表面共平面；且該複數個第二晶粒之一底部表面、該複數個導電柱之一底部表面與該第二模製化合物之一底部表面共平面。
  13. 如請求項12之封裝，其中該複數個第一晶粒及該複數個第二晶粒為記憶體晶粒。
  14. 如請求項11之封裝，其中該複數個第二晶粒定位於該複數個導電柱之一周邊之中，且沒有導電柱定位於該複數個第二晶粒之間
  15. 如請求項14之封裝，其中該RDL具有小於30微米的一總厚度。
  16. 如請求項15之封裝，其進一步包含該第一模製化合物之一頂表面及該第二模製化合物之一底表面，其中該頂表面及該底表面由300微米或更小之一厚度隔開。
  17. 如請求項16之封裝，其進一步包含該複數個第二晶粒及該RDL之間的一電絕緣材料。
  18. 如請求項17之封裝，其中該RDL包括一第一複數個第一凸塊下金屬層(UBM)墊及一第二複數個第二UBM墊，其中該複數個第二晶粒安裝至該第一複數個第一UBM墊，且該複數個導電柱形成於該第二複數個第二UBM墊上，且該等第二UBM墊比該等第一UBM墊寬。
  19. 如請求項18之封裝，其中該第一晶粒及該第二晶粒為記憶體晶粒。
  20. 如請求項19之封裝，其中該記憶體晶粒為動態隨機存取記憶體(DRAM)晶粒。
  21. 一種形成一扇出封裝之方法，其包含：運用一第一模製化合物將一第一晶粒囊封於一載體基板上；移除該載體基板；在該第一模製化合物及該第一晶粒上形成一重佈層(RDL)，其中該RDL之一重佈線沿著該第一晶粒之一底部表面直接地形成於一接觸墊上；在該RDL之一背側上形成複數個導電柱；在該複數個導電柱之一周界內將一第二晶粒安裝於該RDL之該背側上；及運用一第二模製化合物來囊封該第二晶粒、該RDL及該複數個導電柱，其中該第二模製化合物完全橫向環繞該RDL。
  22. 如請求項21之方法，其進一步包含在該複數個導電柱上形成複數個導電凸塊。
  23. 如請求項21之方法，其進一步包含縮減該第一模製化合物之一厚度以曝露該第一晶粒。
  24. 如請求項21之方法，其進一步包含縮減該第一模製化合物及該第一晶粒之一厚度，從而得到一平面頂部封裝表面。
  25. 如請求項21之方法，其進一步包含縮減該第二模製化合物之一厚度以曝露該第二晶粒。
  26. 如請求項21之方法，其進一步包含縮減該第二模製化合物、該第二晶粒及該複數個導電柱之一厚度，從而得到一平面底部封裝表面。
  27. 如請求項21之方法，其進一步包含：縮減該第一模製化合物及該第一晶粒之一厚度，從而得到一平面頂部封裝表面；及縮減該第二模製化合物、該第二晶粒及該複數個導電柱之一厚度，從而得到一平面底部封裝表面。
TW105108575A 2015-04-07 2016-03-18 薄低翹曲扇出封裝中之雙側安裝記憶體整合 TWI646655B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/680,539 2015-04-07
US14/680,539 US9659907B2 (en) 2015-04-07 2015-04-07 Double side mounting memory integration in thin low warpage fanout package

Publications (2)

Publication Number Publication Date
TW201703229A TW201703229A (zh) 2017-01-16
TWI646655B true TWI646655B (zh) 2019-01-01

Family

ID=55527682

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105108575A TWI646655B (zh) 2015-04-07 2016-03-18 薄低翹曲扇出封裝中之雙側安裝記憶體整合

Country Status (5)

Country Link
US (1) US9659907B2 (zh)
KR (1) KR101949076B1 (zh)
CN (1) CN107408552A (zh)
TW (1) TWI646655B (zh)
WO (1) WO2016164119A1 (zh)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10325853B2 (en) * 2014-12-03 2019-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US10535634B2 (en) * 2015-07-22 2020-01-14 Intel Corporation Multi-layer package
US10141288B2 (en) * 2015-07-31 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Surface mount device/integrated passive device on package or device structure and methods of forming
US20170098629A1 (en) * 2015-10-05 2017-04-06 Mediatek Inc. Stacked fan-out package structure
KR20170085833A (ko) * 2016-01-15 2017-07-25 삼성전기주식회사 전자 부품 패키지 및 그 제조방법
DE112016006656T5 (de) * 2016-03-25 2018-12-06 Intel Corporation Substratfreies system in der gehäuseausgestaltung
US9935080B2 (en) * 2016-04-29 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Three-layer Package-on-Package structure and method forming same
US20170338204A1 (en) * 2016-05-17 2017-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Device and Method for UBM/RDL Routing
US11469215B2 (en) 2016-07-13 2022-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US9825007B1 (en) * 2016-07-13 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
JP7084702B2 (ja) * 2016-09-02 2022-06-15 アイデックス バイオメトリクス エーエスエー 指紋センサに適したカバー部材を製造する方法
US9768133B1 (en) * 2016-09-22 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
CN106876290A (zh) 2017-03-10 2017-06-20 三星半导体(中国)研究开发有限公司 晶圆级扇出型封装件及其制造方法
US10515927B2 (en) 2017-04-21 2019-12-24 Applied Materials, Inc. Methods and apparatus for semiconductor package processing
US10943869B2 (en) * 2017-06-09 2021-03-09 Apple Inc. High density interconnection using fanout interposer chiplet
US10217720B2 (en) * 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10283474B2 (en) 2017-06-30 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US20190067145A1 (en) * 2017-08-22 2019-02-28 Micron Technology, Inc. Semiconductor device
US10304805B2 (en) 2017-08-24 2019-05-28 Micron Technology, Inc. Dual sided fan-out package having low warpage across all temperatures
JP2019149507A (ja) * 2018-02-28 2019-09-05 東芝メモリ株式会社 半導体装置及びその製造方法
US10742217B2 (en) 2018-04-12 2020-08-11 Apple Inc. Systems and methods for implementing a scalable system
US11276676B2 (en) * 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US10854552B2 (en) 2018-06-29 2020-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
KR102534734B1 (ko) 2018-09-03 2023-05-19 삼성전자 주식회사 반도체 패키지
CN110880481A (zh) * 2018-09-05 2020-03-13 凤凰先驱股份有限公司 电子封装件及其制法
KR102536269B1 (ko) * 2018-09-14 2023-05-25 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR102538181B1 (ko) 2018-10-24 2023-06-01 삼성전자주식회사 반도체 패키지
US11075167B2 (en) 2019-02-01 2021-07-27 Dialog Semiconductor (Uk) Limited Pillared cavity down MIS-SIP
CN111627867A (zh) * 2019-02-28 2020-09-04 富泰华工业（深圳）有限公司 芯片封装结构及其制作方法
US11024616B2 (en) * 2019-05-16 2021-06-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11251132B1 (en) * 2019-08-08 2022-02-15 Dialog Semiconductor (Uk) Limited Integrated type MIS substrate for thin double side SIP package
CN110634830B (zh) * 2019-09-20 2021-11-09 上海先方半导体有限公司 一种多芯片集成的封装方法和结构
US12021156B2 (en) * 2019-09-30 2024-06-25 Texas Instruments Incorporated Windowed wafer assemblies having interposers
CN110783210A (zh) * 2019-10-30 2020-02-11 华天科技（西安）有限公司 一种两面封装的存储类产品封装结构及制造方法
US11309246B2 (en) * 2020-02-05 2022-04-19 Apple Inc. High density 3D interconnect configuration
US11201127B2 (en) * 2020-03-09 2021-12-14 Qualcomm Incorporated Device comprising contact to contact coupling of packages
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11532582B2 (en) * 2020-08-25 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device package and method of manufacture
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11908757B2 (en) * 2021-06-18 2024-02-20 Taiwan Semiconductor Manufacturing Company Limited Die corner removal for molding compound crack suppression in semiconductor die packaging and methods for forming the same
CN114927500B (zh) * 2022-07-19 2022-10-04 武汉大学 基于分布式的双扇出型异构集成三维封装结构及工艺

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110037169A1 (en) * 2009-08-12 2011-02-17 Stats Chippac, Ltd. Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structures

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008084959A (ja) * 2006-09-26 2008-04-10 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US20080157316A1 (en) 2007-01-03 2008-07-03 Advanced Chip Engineering Technology Inc. Multi-chips package and method of forming the same
US7763976B2 (en) 2008-09-30 2010-07-27 Freescale Semiconductor, Inc. Integrated circuit module with integrated passive device
US20100213589A1 (en) 2009-02-20 2010-08-26 Tung-Hsien Hsieh Multi-chip package
US8754514B2 (en) * 2011-08-10 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip wafer level package
US20130154091A1 (en) 2011-12-14 2013-06-20 Jason R. Wright Semiconductor device packaging using encapsulated conductive balls for package-on-package back side coupling
US8878360B2 (en) * 2012-07-13 2014-11-04 Intel Mobile Communications GmbH Stacked fan-out semiconductor chip
KR101429344B1 (ko) 2012-08-08 2014-08-12 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US8975726B2 (en) * 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
US9847284B2 (en) 2013-01-29 2017-12-19 Apple Inc. Stacked wafer DDR package
US8963318B2 (en) 2013-02-28 2015-02-24 Freescale Semiconductor, Inc. Packaged semiconductor device
US8669140B1 (en) 2013-04-04 2014-03-11 Freescale Semiconductor, Inc. Method of forming stacked die package using redistributed chip packaging
US8822268B1 (en) 2013-07-17 2014-09-02 Freescale Semiconductor, Inc. Redistributed chip packages containing multiple components and methods for the fabrication thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110037169A1 (en) * 2009-08-12 2011-02-17 Stats Chippac, Ltd. Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structures

Also Published As

Publication number Publication date
US20160300813A1 (en) 2016-10-13
WO2016164119A1 (en) 2016-10-13
KR20170137140A (ko) 2017-12-12
KR101949076B1 (ko) 2019-02-15
CN107408552A (zh) 2017-11-28
TW201703229A (zh) 2017-01-16
US9659907B2 (en) 2017-05-23

Similar Documents

Publication Publication Date Title
TWI646655B (zh) 薄低翹曲扇出封裝中之雙側安裝記憶體整合
TWI627716B (zh) 系統級封裝扇出堆疊架構及製程流程
US9935087B2 (en) Three layer stack structure
TWI605526B (zh) 扇出系統級封裝及用於形成其之方法
US9679801B2 (en) Dual molded stack TSV package
US11037819B2 (en) Wafer level chip scale packaging intermediate structure apparatus and method
US11037910B2 (en) Semiconductor device having laterally offset stacked semiconductor dies
US10181455B2 (en) 3D thin profile pre-stacking architecture using reconstitution method
TWI578413B (zh) 散出型晶圓級封裝之３ｄ整合
US8829666B2 (en) Semiconductor packages and methods of packaging semiconductor devices
CN111566799A (zh) 用于形成半导体装置的后柱方法