CN102931173A - 多芯片晶圆级封装 - Google Patents

多芯片晶圆级封装 Download PDF

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Publication number
CN102931173A
CN102931173A CN2012100637951A CN201210063795A CN102931173A CN 102931173 A CN102931173 A CN 102931173A CN 2012100637951 A CN2012100637951 A CN 2012100637951A CN 201210063795 A CN201210063795 A CN 201210063795A CN 102931173 A CN102931173 A CN 102931173A
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semiconductor element
layer
material layer
photosensitive material
semiconductor
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CN2012100637951A
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CN102931173B (zh
Inventor
余俊辉
董志航
邵栋梁
余振华
史达元
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种多芯片晶圆级封装件包括三个堆叠的半导体管芯。第一半导体管芯内嵌在第一感光材料层中。在第一半导体管芯顶面上堆叠第二半导体管芯，其中，第二半导体管芯面对面连接至第一半导体管芯。第三半导体管芯背对背附接至第二半导体管芯。第二半导体管芯和第三半导体管芯内嵌均在第二感光材料层中。多芯片晶圆级封装件进一步包括：形成在第一感光材料层和第二感光材料层中的多个通孔。

Description

多芯片晶圆级封装
技术领域
本发明总体上涉及半导体领域，更具体地，涉及多芯片晶圆级封装。
背景技术
由于集成电路的发明，所以半导体工业已经经历了由于不断改进各种电子元件(例如，晶体管、二极管、电阻器、电容器等)的集成密度所导致的快速发展。通常，这种集成密度的改进源于反复降低最小特征尺寸，从而允许更多的元件集成在给定区域内。随着最近对于甚至更小的电子器件的需求不断增长，对于更小的和更有创造性的半导体管芯的封装技术的需要不断增长。
随着半导体技术发展，作为有效备选，出现了基于多芯片晶圆级封装的半导体器件，从而进一步减小了半导体芯片的物理尺寸。在基于晶圆级封装的半导体器件中，在不同晶圆上制造诸如逻辑电路、存储电路、以及处理电路等的有源电路，并且使用拾取和放置技术在另一晶圆级管芯的顶面上堆叠每个晶圆级管芯。可以通过利用多芯片半导体器件实现更高的密度。此外，多芯片半导体器件可以实现更小的形状因数、成本效率、提高的性能、以及更低的功耗。
多芯片半导体器件可以包括顶部有源电路层、底部有源电路层、以及多个中间层。在多芯片半导体器件中，可以通过多个微凸块将两个管芯接合在一起，并且通过多个穿透硅通孔将两个管芯彼此电连接。微凸块和穿透硅通孔提供了在多芯片半导体器件的垂直轴上的电互连。因此，在两个半导体管芯之间的信号路径比传统多芯片器件更短，在传统多芯片器件中，使用诸如基于引线接合的芯片叠层封装的互连技术将不同芯片接合在一起。多芯片半导体器件可以包括堆叠在一起的各种半导体管芯。在切割晶圆以前，封装多个半导体管芯。晶圆级封装技术具有许多优点。晶圆级封装多半导体管芯的一个有利特征是多芯片晶圆级封装技术可以降低制造成本。基于晶圆级封装的多芯片半导体器件的另一有利特征是通过利用微凸块和穿透硅通孔降低了寄生损耗。
发明内容
为解决上述问题，本发明提供了一种器件，包括：第一半导体管芯，被内嵌在第一感光材料层中；第二半导体管芯，堆叠在第一半导体管芯的顶部上，其中，第二半导体管芯面对面地连接至第一半导体管芯；第二感光材料层，形成在第一感光材料层的顶部上，其中，第二半导体管芯内嵌在第二感光材料层中；以及多个通孔，形成在第一感光材料层和第二感光材料层中。
该器件进一步包括：第三半导体器件，位于第二半导体管芯的上方，其中，通过第一粘合材料层将第三半导体管芯的背面附接至第二半导体管芯的背面，其中，将第三半导体管芯内嵌在第二感光材料层中。
其中，多个通孔包括：第一组通孔，形成在第三半导体管芯的正面和第二感光材料层的顶部之间；第二组通孔，形成在第一半导体管芯的正面和第一感光材料层的顶部之间；以及第三组通孔，形成为穿过第二感光材料层。
该器件进一步包括：基底层，通过第二粘合材料层附接至第一半导体管芯的背面；多个金属凸块，形成在第一半导体管芯和第二半导体管芯之间；第一再分布层，形成在第一感光材料层的顶部上；第二再分布层，形成在第二感光材料层的顶部上；底部填充材料层，形成在第二半导体管芯和第一再分布层之间；以及多个焊球，形成在第二再分布层的顶部上。
其中，第一再分布层和多个金属凸块被配置成使得：通过由第一再分布层和多个金属凸块所形成的连接路径将位于第一半导体管芯中的各种有源电路连接至位于第二半导体管芯中的各种有源电路。
其中，第一再分布层、多个金属凸块、多个通孔、以及第二再分布层被配置成使得：通过由第一再分布层、多个金属凸块、多个通孔、以及第二再分布层所形成的连接路径将位于第一半导体管芯中的各种有源电路和位于第二半导体管芯中的各种有源电路连接至多个焊球。
其中，多个通孔和第二再分布层被配置成使得：通过由多个通孔和第二再分布层所形成的连接路径将位于第三半导体管芯中的各种有源电路连接至多个焊球。
其中，第一半导体管芯的水平长度小于第二半导体管芯的水平长度。
此外，本发明提供了一种器件，包括：第一半导体层，包括：第一半导体管芯，被内嵌在第一感光材料层中；以及多个通孔，形成在第一感光材料层中；第二半导体层，包括：第二半导体管芯和第三半导体管芯，通过粘合材料层背对背地堆叠在一起；第二感光材料层，其中，将第二半导体管芯和第三半导体管芯内嵌在第二感光材料层中；多个通孔，形成在第三半导体管芯的顶部上；第三半导体层，具有与第二半导体层相同的结构；第一组金属凸块，形成在第一半导体层和第二半导体层之间；以及第二组金属凸块，形成在第二半导体层和第三半导体层之间。
该器件进一步包括：第一组焊球，形成在第三半导体层的顶部上，其中，将第一组焊球用作器件的输入/输出焊盘。
其中，形成在第一半导体层、第二半导体层、以及第三半导体层中的多个通孔和第一组金属凸块被配置成使得：通过由第一组金属凸块和多个通孔所形成的连接路径将位于第一半导体管芯中的多个有源电路连接至第一组焊盘。
该器件进一步包括：第二组焊球，形成在第一半导体层的背面上，其中，将第二组焊球用作器件的输入/输出焊盘。
其中，形成在第一半导体层中的多个通孔和第一组金属凸块被配置成使得：通过由第一组金属凸块和多个通孔所形成的连接路径将位于第一半导体管芯中的多个有源电路连接至第二组焊球。
此外，还提供了一种方法，包括：通过将第一半导体管芯内嵌在第一感光材料层中形成重新配置的晶圆；在第一感光材料层中形成第一组通孔；通过多个金属凸块将第二半导体管芯与第一半导体管芯连接；使用第一粘合层将第三半导体管芯背对背地附接至第二半导体管芯；形成第二感光材料层，第二感光材料层含有第二半导体管芯和第三半导体管芯；以及在第二感光材料层中形成第二组通孔。
该方法进一步包括：使用粘合层将第一半导体管芯附接在基底层上；以及将基底层与第一半导体管芯分离。
该方法进一步包括：在第一半导体管芯和第二半导体管芯之间形成多个金属凸块；在第一感光材料层的顶部上形成第一再分布层；在第二感光材料层的顶部上形成第二再分布层；在第二半导体管芯和第一再分布层之间形成底部填充材料层；以及在第二再分布层的顶部上形成多个焊球。
该方法进一步包括：在第一感光材料层的背面上形成第二组焊球。
该方法进一步包括：在第三半导体管芯的正面和第二感光材料层的正面之间形成第一组开口；在第一半导体管芯的正面和第一感光材料层的正面之间形成第二组开口；以及形成第三组开口，第三组开口穿过第二感光材料层。
该方法进一步包括：在第一组开口中电镀导电材料；在第二组开口中电镀导电材料；以及在第三组开口中电镀导电材料。
该方法进一步包括：将重新配置的晶圆切割成多个封装件，其中，每个封装件包括多个半导体管芯。
附图说明
为了更好地理解本实施例，现在将结合附图所进行的以下描述作为参考，其中：
图1示出了根据实施例的多芯片半导体器件的横截面图；
图2示出了根据另一实施例的多芯片半导体器件的横截面图；
图3至图14为在根据实施例制造多芯片半导体器件的中间阶段的横截面图；
图15示出了根据另一实施例的另一多芯片半导体器件；以及
图16示出了根据另一实施例的另一多芯片半导体器件的横截面图。
除非另有说明，在不同附图中的相应的数字和标号通常指的是相应的部件。为了清晰地示出各个实施例的相关方面，绘制附图，并且没有必要按比例绘制。
具体实施方式
下面，详细讨论本实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的发明概念。所讨论的具体实施例仅仅示出制造和使用本发明的具体方式，而不用于限制本发明的范围。
最初，参考图1，根据实施例示出了多芯片半导体器件的横截面图。多芯片半导体器件100包括：第一半导体管芯CHIP 1、第二半导体管芯CHIP 2、以及第三半导体管芯CHIP 3。如图1所示，第一半导体管芯CHIP1、第二半导体管芯CHIP 2、以及第三半导体管芯CHIP 3堆叠在一起，从而形成多芯片半导体器件100。更具体地，第一半导体管芯CHIP 1、第二半导体管芯CHIP 2使用多个金属凸块122堆叠在一起。使用环氧树脂层124将第三半导体管芯CHIP 3背对背粘附至第二半导体管芯CHIP 2。
多芯片半导体器件100进一步包括多个焊球110作为输入/输出(I/O)焊盘，使用多个凸块下金属化(UBM)结构112将多个焊球110安装在多芯片半导体器件100的顶面上。为了提供对各个实施例的发明方面的基本理解，绘制了第一半导体管芯CHIP 1、第二半导体管芯CHIP 2、以及第三半导体管芯CHIP 3，而没有绘制细节内容。然而，应该注意，第一半导体管芯CHIP 1、第二半导体管芯CHIP 2、以及第三半导体管芯CHIP 3可以包括基本半导体层，例如，有源电路层、衬底层、层间介电(ILD)层、以及金属间介电(IMD)层(未示出)。
根据实施例，第一半导体管芯CHIP 1可以包括多个逻辑电路，例如，中央处理单元(CPU)和图形处理单元(GPU)等。第二半导体管芯CHIP2和第三半导体管芯CHIP 3可以包括多个存储电路，例如，静态随机存取存储器(SRAM)和动态随机存取存储器(DRAM)等。应该注意，第一半导体管芯CHIP 1、第二半导体管芯CHIP 2、以及第三半导体管芯CHIP 3可以具有多个实施例，该多个实施例也在本发明的范围内。
多芯片半导体器件100可以包括：两个感光材料层106和108。在第一感光材料层108的顶面上形成第二感光材料层106。如图1所示，将第一半导体管芯CHIP 1内嵌在第一感光材料层108中。形成的多个通孔(TSV)104穿过第一感光材料层108。应该注意，虽然图1示出了形成在第一感光材料层108中的多个TAV 104，但是本发明的一些实施例可能不包括位于第一感光材料层108中的TAV 104。因为没有必要通过位于第一感光材料层108中的TAV 104将第一半导体管芯CHIP 1的有源电路与多芯片器件100的输入/输出焊盘连接，所以TAV 104是任选的。
第二感光材料层106可以内嵌第二半导体管芯CHIP 2、第三半导体管芯CHIP 3、多个TAV 102、以及多个TAV 116。应该注意，如图1所示，在第二感光材料层106中形成TAV 102和TAV 116。然而，在第三半导体管芯CHIP 103和多芯片半导体器件100的焊球侧之间形成TAV 116。反之，形成的TAV 102穿过第二感光材料层106，并且将TAV 102进一步连接至形成在第一感光材料层108的顶面上的第一再分布层126。将参考图3至图14详细描述感光材料层106、108、以及位于每层中的相应的TAV的形成工艺。
通过多个金属凸块122将第一半导体管芯CHIP 1的有源电路层(未示出)连接至第二半导体管芯CHIP 2的有源电路层(未示出)。此外，第一再分布层126和TAV 104和TAV 102可以形成各种连接路径，从而使得第一半导体管芯CHIP 1和第二半导体管芯CHIP 2的有源电路可以与焊球110连接。同样地，第二再分布层114和TAV 116可以形成各种连接路径，从而使得第三半导体管芯CHIP 3的有源电路(未示出)可以与焊球110连接。
多芯片半导体器件100可以包括：形成在第一半导体管芯CHIP 1的背面上的基底层120。基底层120可以由导电材料形成，例如，铜、银、金、钨、铝、或者其组合。可选地，基底层120可以由各种材料形成，该各种材料包括：玻璃、硅、陶瓷、以及聚合体等。根据实施例，可以通过包括环氧树脂等的诸如热界面材料的粘合剂将基底层120粘结在半导体管芯CHIP 1的背面上。
如图1所示，直接与第一半导体管芯CHIP 1邻近地形成基底层120。因此，基底层120可以有助于耗散通过第一半导体管芯CHIP 1所生成的热。因此，基底层120可以有助于降低第一半导体管芯CHIP 1的结温度。与没有基底层的半导体管芯相比较，第一半导体管芯CHIP 1受益于通过基底层120的热耗散，从而使得可以改善第一半导体管芯CHIP 1的可靠性和性能。根据实施例，基底层120的厚度在从5μm至50μm的范围内。应该注意，完全为了说明的目的，选择基底层的厚度范围，不是为了将本发明的各个实施例限于任何特定厚度。本领域普通技术人员可以识别多种改变、替换、以及更改。
图2示出了根据另一实施例的多芯片半导体器件的横截面图。如图2所示，除了可以通过封装材料层109替换第一感光材料层108以外，多芯片半导体器件200的结构与在图1中所示的多芯片半导体器件100的结构类似。如本领域中公知的，封装材料层可以包括模塑料(moldingcompound)，例如，环氧树脂等。形成在多芯片半导体器件200中的模塑料可以有助于保护第一半导体管芯CHIP 1防止受热、振动、受潮、以及腐蚀。本领域众所周知封装材料层的形成，因此，本文中没有详细讨论。
图3至图14为根据实施例制造多芯片半导体器件的中间阶段的横截面图。图3示出了将第一半导体管芯CHIP 1置于基底层120上的横截面图。如图3所示，将第一半导体管芯CHIP 1的背面安装在基底层120上。第一半导体管芯CHIP 1可以包括有源层、衬底层、ILD层、以及IMD层(未示出)。第一半导体管芯CHIP 1可以进一步包括：多个金属焊盘，通过再分布层重新分布该金属焊盘的连接。在通篇描述中，可选地，将具有金属焊盘的半导体管芯的侧面称作半导体管芯的正面。另一方面，将没有金属焊盘的半导体管芯的侧面称作半导体管芯的背面。应该注意，虽然图2示出了安装在基底层120上的两个管芯，但是基底层120可以包括任何数量的半导体管芯。
图4示出了第一感光材料层108的横截面图。在第一半导体管芯CHIP1的顶面上形成第一感光材料层108。如图4所示，将第一半导体管芯CHIP1内嵌在第一感光材料层108中。感光材料层可以包括：聚苯并恶唑(PBO)、SU-8感光环氧树脂、和/或膜型聚合材料等。应该注意，虽然图4示出了感光材料层，但是第一感光材料层108可以由聚合材料形成，该聚合材料包括：非感光材料，例如模塑料和/或橡胶等。根据实施例，在多个第一半导体管芯CHIP 1上方层压或者涂覆感光材料，从而形成包括多个半导体管芯CHIP 1的重新配置的晶圆。具有在第一半导体管芯CHIP 1顶面上层压或涂覆的感光材料层的一个有利特征是CHIP 1的有效管芯面积扩大，从而使得第二半导体管芯CHIP 2(没有示出，而是在图8中示出)可以比第一半导体管芯CHIP 1更大或者更小。换句话说，不是通过随后在第一半导体管芯CHIP 1的顶面上堆叠的管芯的尺寸限定第一半导体管芯CHIP 1的尺寸。
图5示出了在第一感光材料层108中形成多个开口的横截面图。考虑电和热要求，第一感光材料层108的选择面积暴露在光下。因此，暴露在光下的感光区域的物理性能改变。根据实施例，当将显影剂施加给第一感光材料层108时，曝光区域的物理性能的改变导致曝光区域被腐蚀掉。因此，形成各种开口502。在第一感光材料层108中形成开口502包括公知的光刻操作，因此，本文中没有更详细地讨论。
图6示出了多个TAV和再分布层的形成。如图6所示，导电材料使用电镀工艺填充开口502(没有示出，而是在图5中示出)。因此，在第一感光材料层108中形成多个TAV 602。导电材料可以为铜，但是可以为任何导电材料，例如，铜合金、铝、钨、银、以及其组合。为了重新分配与TAV 602的电连接，可以在第一感光材料层108的顶面上形成再分布层604。可以通过电镀机械装置形成再分布层604。
图7示出了多个UBM结构和金属凸块的形成。在再分布层604的顶面上形成多个UBM结构702。UBM结构702可以有助于防止在多芯片半导体器件的焊球和集成电路之间的扩散，同时提供了低阻电连接。金属凸块是连接位于多芯片半导体器件中的两个半导体管芯的有源电路的有效方式。
图8示出了在第一半导体管芯CHIP 1的顶面上堆叠第二半导体管芯CHIP 2和第三半导体管芯CHIP 3的工艺。通过利用诸如环氧树脂和/或热界面材料等的粘合剂804将第三半导体管芯CHIP 3的背面粘合在第二半导体管芯CHIP 2的背面的顶面上。通过由金属凸块、UBM结构、再分布线、以及金属焊盘所形成的连接路径将第二半导体管芯CHIP 2面对面连接至第一半导体管芯CHIP 1。
可以在再分布层和第二半导体管芯CHIP 2之间的间隙中形成底部填充材料802。根据实施例，底部填充材料802可以是环氧树脂，将该底部填充材料分配在再分布层和第二半导体管芯CHIP 2之间的间隙中。可以施加液态的环氧树脂，并且该环氧树脂可以在固化工艺以后硬化。本领域技术人员意识到，在将第二半导体管芯CHIP 2附接至重新配置的晶圆以后，分配底部填充材料802仅为形成底部填充材料层的一种方式。本领域技术人员应该理解，可以具有多个本发明实施例的变型例。例如，可以将液态或半液态环氧树脂预先施加在第一半导体管芯CHIP 1的顶面上。随后，第二半导体管芯CHIP 2挤过(pushed through)由环氧树脂所形成的涂覆层，直到第二半导体管芯CHIP 2与位于第一半导体管芯CHIP 1的顶部上的相应凸块704接触。可选地，可以将底部填充材料施加在第一半导体管芯CHIP1的顶面上，从而形成冷涂层(icy coating)。通过热固化工艺，第二半导体管芯CHIP 2与位于第一半导体管芯CHIP 1的顶面上的相应凸块704接触。具有底部填充材料802的有利特征是底部填充材料可以在多芯片半导体器件的制造工艺期间有助于降低机械应力和热应力。
图9示出了第二感光材料层106的横截面图。在第一感光材料层108的顶面上形成第二感光材料层106。如图9所示，第二半导体管芯CHIP 2和第三半导体管芯CHIP 3内嵌在第二感光材料层106中。以上参考图4已经描述了形成感光材料层的工艺，因此为了避免重复，没有进行讨论。
图10示出了在第二感光材料层106中形成多个开口的横截面图。考虑电和热要求，第二感光材料层106的选择区域暴露在光下。因此，形成具有不同深度的各种开口。更具体地来说，形成的多个长开口102穿过第二感光材料层106，并且在第二感光材料层106的顶面和第三半导体管芯CHIP 3的正面之间形成多个短开口116。
图11示出了形成位于第二感光材料层106中的多个TAV和位于第二感光材料106的顶面上的再分布线。如图11所示，导电材料填充开口102和116。导电材料可以为铜，但是可以为任何其他导电材料，例如，铜合金、铝、钨、银、以及其组合。为了重新分布与TAV 102和116的电连接，可以在第二感光材料层106的顶面上形成再分布线114。可以通过电镀机械装置形成再分布层。
图12示出了多个UBM结构和互连焊盘的形成。在再分布层114和焊球110之间形成多个UBM结构。UBM结构有助于防止在焊球和多芯片半导体器件的集成电路之间的扩散，同时提供了低阻电连接。互连焊盘为多芯片半导体器件的I/O焊盘。根据实施例，互连焊盘可以为多个焊球110。可选地，互连焊盘可以为多个焊盘网格阵列(land grid array(LGA))焊盘。
图13示出了从多芯片半导体器件去除基底层120的工艺。根据实施例，基底层120为多芯片半导体器件的任选元件。可以从多芯片半导体器件分离基底层120。可以采用各种分离工艺，从而将多芯片半导体器件与基底层分离。各种分离工艺可以包括化学溶剂和UV曝光等。图14示出了使用切割工艺将重新配置的晶圆分离为单独的芯片封装件1402和1404的工艺。本领域众所周知切割工艺，因此本文中没有详细讨论。
图15示出了根据另一实施例的另一多芯片半导体器件。如图15所示，除了具有与第二层1502相同的结构的一个额外层1504以外，多芯片半导体器件1500的结构与在图1中所示的多芯片半导体器件100的结构类似。通过位于第二层1502和第三层1504之间的多个微凸块电连接位于第三层1504中的半导体芯片和位于第二层1502中的半导体芯片。
图16示出了根据另一实施例的另一多芯片半导体器件的横截面图。如图16所示，除了可以存在形成在第一感光材料层108的背面上的多个焊球1602以外，多芯片半导体器件1600的结构与在图1中所示的多芯片半导体器件100的结构类似。以上参考图12已经描述了在感光材料层上形成焊球，因此为了避免重复，没有再次讨论。具有形成在第一感光材料层108的背面上的第二组焊球1602的一个有利特征是可以在彼此的顶面上堆叠多个多芯片半导体器件1600，并且通过焊球1602使之电互连。
尽管已经详细地描述了实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明的公开，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (10)

1.一种器件，包括：
第一半导体管芯，被内嵌在第一感光材料层中；
第二半导体管芯，堆叠在所述第一半导体管芯的顶部上，其中，所述第二半导体管芯面对面地连接至所述第一半导体管芯；
第二感光材料层，形成在所述第一感光材料层的顶部上，其中，所述第二半导体管芯内嵌在所述第二感光材料层中；以及
多个通孔，形成在所述第一感光材料层和所述第二感光材料层中。
2.根据权利要求1所述的器件，进一步包括：
第三半导体器件，位于所述第二半导体管芯的上方，其中，通过第一粘合材料层将所述第三半导体管芯的背面附接至所述第二半导体管芯的背面，其中，将所述第三半导体管芯内嵌在所述第二感光材料层中。
3.根据权利要求2所述的器件，其中，所述多个通孔包括：
第一组通孔，形成在所述第三半导体管芯的正面和所述第二感光材料层的顶部之间；
第二组通孔，形成在所述第一半导体管芯的正面和所述第一感光材料层的顶部之间；以及
第三组通孔，形成为穿过所述第二感光材料层。
4.根据权利要求2所述的器件，进一步包括：
基底层，通过第二粘合材料层附接至所述第一半导体管芯的背面；
多个金属凸块，形成在所述第一半导体管芯和所述第二半导体管芯之间；
第一再分布层，形成在所述第一感光材料层的顶部上；
第二再分布层，形成在所述第二感光材料层的顶部上；
底部填充材料层，形成在所述第二半导体管芯和所述第一再分布层之间；以及
多个焊球，形成在所述第二再分布层的顶部上。
5.根据权利要求4所述的器件，其中，所述第一再分布层和所述多个金属凸块被配置成使得：
通过由所述第一再分布层和所述多个金属凸块所形成的连接路径将位于所述第一半导体管芯中的各种有源电路连接至位于所述第二半导体管芯中的各种有源电路。
6.根据权利要求4所述的器件，其中，所述第一再分布层、所述多个金属凸块、所述多个通孔、以及所述第二再分布层被配置成使得：
通过由所述第一再分布层、所述多个金属凸块、所述多个通孔、以及所述第二再分布层所形成的连接路径将位于所述第一半导体管芯中的各种有源电路和位于所述第二半导体管芯中的各种有源电路连接至所述多个焊球。
7.根据权利要求4所述的器件，其中，所述多个通孔和所述第二再分布层被配置成使得：
通过由所述多个通孔和所述第二再分布层所形成的连接路径将位于所述第三半导体管芯中的各种有源电路连接至所述多个焊球。
8.根据权利要求1所述的器件，其中，所述第一半导体管芯的水平长度小于所述第二半导体管芯的水平长度。
9.一种器件，包括：
第一半导体层，包括：
第一半导体管芯，被内嵌在第一感光材料层中；以及
多个通孔，形成在所述第一感光材料层中；
第二半导体层，包括：
第二半导体管芯和第三半导体管芯，通过粘合材料层背对背地堆叠在一起；
第二感光材料层，其中，将所述第二半导体管芯和所述第三半导体管芯内嵌在所述第二感光材料层中；
多个通孔，形成在所述第三半导体管芯的顶部上；
第三半导体层，具有与所述第二半导体层相同的结构；
第一组金属凸块，形成在所述第一半导体层和所述第二半导体层之间；以及
第二组金属凸块，形成在所述第二半导体层和所述第三半导体层之间。
10.根据权利要求9所述的器件，进一步包括：第一组焊球，形成在所述第三半导体层的顶部上，其中，将所述第一组焊球用作所述器件的输入/输出焊盘。
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