CN107808855B - 芯片封装结构及其制造方法 - Google Patents

芯片封装结构及其制造方法 Download PDF

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CN107808855B
CN107808855B CN201710622346.9A CN201710622346A CN107808855B CN 107808855 B CN107808855 B CN 107808855B CN 201710622346 A CN201710622346 A CN 201710622346A CN 107808855 B CN107808855 B CN 107808855B
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semiconductor element
conductive pillars
pillars
conductive
chip
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CN107808855A (zh
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徐宏欣
林南君
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Powertech Technology Inc
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Powertech Technology Inc
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Abstract

本发明提供一种芯片封装结构，其包括半导体元件、多个导电柱、密封体以及重布线路层。半导体元件包括多个接垫。导电柱形成于接垫上，其中各个导电柱为包括顶表面以及底表面的实心柱，且顶表面的直径与底表面的直径基本上相同。密封体包覆半导体元件以及导电柱，其中密封体暴露出各个导电柱的顶表面。重布线路层形成于密封体上，且重布线路层与导电柱电性连接。本发明另提供其制造方法。

Description

芯片封装结构及其制造方法
技术领域
本发明涉及一种芯片封装结构及其制造方法，尤其涉及一种堆叠型(stackedtype)的芯片封装结构及其制造方法。
背景技术
近年来，一种称之为内装芯片基板(substrate with a built-in chip)的半导体元件已受到很大关注，其是将芯片及其类似物埋入由树脂等制成的基板及其类似物以及半导体元件中，并且将绝缘层以及线路层形成于芯片上。在具有内装芯片基板的半导体元件中，必须将芯片埋入绝缘层中，并且通过在绝缘层中形成通孔(via hole)，以将位于芯片上的接垫电性连接至外部端子。
一般而言，通常是通过使用激光光束以形成通孔。在这种情况下，激光光束通过绝缘层，并且由铝或类似物所制成的芯片接垫可以于激光光的照射下而被分开。如此一来，会对具有半导体芯片的元件造成破坏性的损坏。
发明内容
本发明提供一种芯片封装结构，其具有良好的可靠性(reliability)、较低的生产成本以及较薄的整体厚度。
本发明更提供一种芯片封装结构的制造方法，其提升了堆叠型芯片封装结构的可靠性及产量，并且降低了堆叠型芯片封装结构的生产成本以及整体厚度。
本发明提供一种芯片封装结构，其包括第一半导体元件、多个第一导电柱，第一密封体以及第一重布线路层。第一半导体元件包括多个第一接垫。第一导电柱设置于第一接垫上，其中各个第一导电柱为包括顶表面及底表面的实心圆柱，且顶表面的直径基本上与底表面的直径相同。第一密封体包覆第一半导体元件以及第一导电柱，其中第一密封体暴露出各个第一导电柱的顶表面。第一重布线路层设置于第一密封体上且电性连接至第一导电柱。
本发明提供一种芯片封装结构的制造方法，所述方法包括以下步骤。设置第一半导体元件于第一载板上，其中第一半导体元件包括第一主动面以及设置于第一主动面上的多个第一接垫。形成多个第一导电柱于第一接垫上，其中各个第一导电柱为包括顶表面及底表面的实心圆柱，且顶表面的直径基本上与底表面的直径相同。形成第一密封体以包覆第一半导体元件以及第一导电柱，其中第一密封体暴露出各个第一导电柱的顶表面。形成第一重布线路层于第一密封体上，其中第一重布线路层电性连接至第一导电柱。移除第一载板。
基于上述，在本发明中，至少一个半导体元件设置于第一载板上，且导电柱形成于半导体元件上。然后，形成密封体以包覆半导体元件并暴露出导电柱的顶表面，且形成重布线路层于密封体上以电性连接半导体元件。然后，于重布线路层上堆叠多个半导体元件，且可以重复形成导电柱/贯通柱、密封体以及重布线路层的步骤，以形成堆叠型芯片封装结构。如此一来，可以进一步减小芯片封装结构的厚度，且可以省略通过激光钻孔形成用于半导体元件的导通孔(conductive vias)的处理，从而降低芯片封装结构的制造成本。此外，由于于此省略了激光钻孔处理，从而可以避免因激光引起的对半导体元件的接垫的损坏。除此之外，本发明的导电柱是预先形成于半导体元件上的实心圆柱，而通过激光处理所形成的通孔为内部具有空隙的锥形。因此，导电柱可以具有较好的电性，并且可以减小任何两相邻的导电柱之间的间隙。
附图说明
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
图1至图7是依据本发明一实施例的芯片封装结构的制造方法的剖面示意图；
图8是依据本发明一实施例的芯片封装结构的剖面示意图；
图9是依据本发明一实施例的芯片封装结构的剖面示意图；
图10至图13是依据本发明一实施例的芯片封装结构的制造方法的剖面示意图；
图14是依据本发明一实施例的芯片封装结构的剖面示意图；
图15是依据本发明一实施例的芯片封装结构的剖面示意图；
图16至图19是依据本发明一实施例的芯片封装结构的制造方法的剖面示意图。
附图标号说明：
100、100a、100b、100d、100e、100f、100g：芯片封装结构
10：第一载板
20：第二载板
110：第一半导体元件
112：第一主动面
114：第一接垫
116：第一导电柱
120：第一密封体
122：第一重布线路层
130：第二半导体元件
132：第二导电柱
134：芯片
136：模封材料
138：重布线路
139、144：贯通柱
140：第三半导体元件
142：第三导电柱
150：第二密封体
152：第二重布线路层
154：贯通柱
160：第四半导体元件
162：第四导电柱
170：焊球
180、190：子芯片封装
具体实施方式
图1至图7是依据本发明一实施例的芯片封装结构的制造方法的剖面示意图。本实施例中，芯片封装结构的制造过程可以包括以下步骤。请参照图1，形成第一半导体元件110于如图1所示的第一载板10上。第一半导体元件110可以为芯片。第一半导体元件110可以包括第一主动面112以及设置于第一主动面112上的多个第一接垫114。然后，形成多个第一导电柱116于第一接垫114上。各个第一导电柱116为实心柱。第一导电柱116可以包括顶表面以及平行且相对于顶表面的底表面。如图1所示，各个第一导电柱116的顶表面的尺寸与各个第一导电柱116的底表面的尺寸基本上相同。各个第一导电柱116从顶部到底部可以具有一致的尺寸。在一实施例中，各个第一导电柱116为实心圆柱。各个第一导电柱116的顶表面的直径与各个第一导电柱116的底表面的直径基本上相同。各个第一导电柱116从顶部到底部可以具有一致的直径。在本实施例中，第一导电柱116可以通过电镀处理形成，但是本发明不限于此。
请参照图2，形成第一密封体120以包覆第一半导体元件110以及第一导电柱116。第一密封体120暴露出各个第一导电柱116的顶表面。在本实施例中，第一密封体120可以完全覆盖第一半导体元件110以及第一导电柱116。接着，可以对第一密封体120进行研磨处理(grinding process)，直到露出各个第一导电柱116的顶表面。如此一来，如图2所示，第一密封体120的顶表面与各个第一导电柱116的顶表面共面。通过这样的结构，可以进一步减小芯片封装结构的厚度。此外，可以省略通过激光钻孔以形成用于第一半导体元件110的导通孔的处理。因此，可以降低芯片封装结构的制造成本。此外，由于于此省略了激光钻孔处理(laser drilling process)，因此可以避免第一接垫114因为激光所造成的损坏。除此之外，预先形成的导电柱116是实心圆柱，而通过激光处理所形成的通孔为内部具有空隙的锥形。因此，导电柱116可以具有较好的电性，并且可以减小任何两相邻的导电柱116之间的间隙。
接着，请参照图3，形成第一重布线路层122于如图2所示的第一密封体120上，并且可以移除第一载板10。第一重布线路层122通过第一导电柱116电性连接至第一半导体元件110。此外，可以形成多个焊球170于第一重布线路层122上并且电性连接至第一重布线路层122，以使芯片封装结构100可以通过焊球170电性连接至外部元件。此时，基本上完成了芯片封装结构100的制造过程。
在一实施例中，子芯片封装180可以设置于芯片封装结构100的第一焊球170上，并且电性连接至第一焊球170。举例而言，形成子芯片封装180的方法可以包括以下步骤。首先，请参照图4，于第二载板20上形成第二半导体元件130。在本实施例中，第二半导体元件130可以包括第二主动面以及设置于第二主动面上的多个第二接垫。然后，形成多个第二导电柱132于第二半导体元件130的第二接垫上。在本实施例中，各个第二导电柱132为实心柱。各个第二导电柱132的顶表面的尺寸与各个第二导电柱132的底表面的尺寸基本上相同。在一实施例中，各个第二导电柱132为实心圆柱。各个第二导电柱132的顶表面的直径与各个第二导电柱132的底表面的直径基本上相同。在本实施例中，第二导电柱132类似于第一导电柱116，除了各个第二导电柱132的长度可以比各个第一导电柱116短。然后，形成多个贯通柱154于第二载板20上。在本实施例中，贯通柱154围绕第二半导体元件130。
接着，请参照图5，形成第二密封体150以密封第二半导体元件130、第二导电柱132以及贯通柱154。在本实施例中，第二密封体150暴露出各个第二导电柱132的上表面以及各个贯通柱154的上表面。类似地，第二密封体150可以完全覆盖第二半导体元件130、第二导电柱132以及贯通柱154。接着，可以对第二密封体150进行研磨处理，直到露出第二导电柱132以及贯通柱154的上表面，以与之后形成的第二重布线路层152电性连接。
接着，请参照图6，形成第二重布线路层152于第二密封体150上且电性连接至第二导电柱132以及贯通柱154。此外，形成多个焊球170于第二重布线路层152上，并且可以移除第二载板20。此时，基本上完成了子芯片封装180的制造过程。
接着，请参照图7，子芯片封装180可以通过焊球170设置于如图3所示的芯片封装结构100上。在本实施例中，可以通过重复图4至图6的类似处理以形成另一子芯片封装190，然后可以将子芯片封装190设置于子芯片封装180上以形成如图7所示的芯片封装结构100a。值得注意的是，本实施例仅供参考。于本发明中对于子芯片封装的数量及其形成方式并不加以限制。
图8是依据本发明一实施例的芯片封装结构的剖面示意图。请参照图8，在本实施例中，芯片封装结构100b与图3所显示的芯片封装结构100类似，其相同或类似的构件以相同或类似的标号表示，且具有相同或类似的功能，并省略描述。
请参照图8，在本实施例中，于形成第一密封体120之前，例如为图2所显示的步骤之前，设置第二半导体元件130于第一半导体元件110的第一主动面112上。接着，将第一密封体120包覆第一半导体元件110以及第二半导体元件130，且第二半导体元件130被配置以电性连接至第一重布线路层122。在本实施例中，第二半导体元件130可以为如图8所示具有多个贯通柱的中介板，且第一重布线路层122电性连接至第二半导体元件130。
图9是依据本发明一实施例的芯片封装结构的剖面示意图。请参照图9，在本实施例中，芯片封装结构100c与图3所显示的芯片封装结构100类似，其相同或类似的构件以相同或类似的标号表示，且具有相同或类似的功能，并省略描述。
请参照图9，在本实施例中，第二半导体元件130可以为包括芯片134、模封材料136、多个贯通柱139以及重布线路138的芯片封装。芯片134的接垫面向第一半导体元件110，且模封材料136包覆芯片134。重布线路138设置于模封材料136上且设置于第一主动面112以及模封材料136之间。重布线路138电性连接至芯片134，且贯通柱139贯穿模封材料136以电性连接至第一重布线路层122以及重布线路138。
图10至图13是依据本发明一实施例的芯片封装结构的制造方法的剖面示意图。请参照图10至图13，在本实施例中，芯片封装结构100d的制造过程与图1至图3所显示的芯片封装结构100的制造过程类似。其相同或类似的构件以相同或类似的标号表示，且具有相同或类似的功能，并省略描述。
请参照图10，在本实施例中，于形成第一密封体120之前，例如为图2所显示的步骤之前，设置第二半导体元件130于第一半导体元件110的第一主动面112上。然后，形成多个第二导电柱132于第二半导体元件130的接垫上。各个第二导电柱132为类似于第一导电柱116的实心柱。
接着，第一密封体120包覆第一半导体元件110、第二半导体元件130、第一导电柱116以及第二导电柱132。第一密封体120暴露出第一导电柱116以及第二导电柱132的上表面，以使第一导电柱116以及第二导电柱132电性连接至后续形成的第一重布线路层122。在本实施例中，第一密封体120可以完全覆盖第一半导体元件110、第二半导体元件130、第一导电柱116以及第二导电柱132。接着，可以对第一密封体120进行研磨处理，直到露出第一导电柱116以及第二导电柱132的顶表面。如此一来，如图11所示，第一密封体120的顶表面、第一导电柱116的顶表面以及第二导电柱132的顶表面共面。
通过这样的配置，可以进一步减小芯片封装结构的厚度。此外，可以省略通过激光钻孔以形成用于半导体元件110、130的导通孔的处理。因此，可以降低芯片封装结构的制造成本。此外，由于于此省略了激光钻孔处理，因此可以避免半导体元件110、130的接垫因为激光所造成的损坏。除此之外，预先形成的导电柱116、132是实心圆柱，而通过激光处理所形成的通孔为内部具有空隙的锥形。因此，导电柱116、132可以具有较好的电性，并且可以减小任何两相邻的导电柱116、132之间的间隙。
接着，请参照图12，形成第一重布线路层122于如图12所示的第一密封体120上，并且可以移除第一载板10。第一重布线路层122通过第一导电柱116以及第二导电柱132电性连接至第一半导体元件110以及第二半导体元件130。此外，请参照图13，可以形成多个焊球170于第一重布线路层122上并且电性连接至第一重布线路层122，以使芯片封装结构100d可以通过焊球170电性连接至外部元件。此时，基本上完成了芯片封装结构100d的制造过程。
图14是依据本发明一实施例的芯片封装结构的剖面示意图。请参照图14，在本实施例中，芯片封装结构100e与图13所显示的芯片封装结构100d类似，其相同或类似的构件以相同或类似的标号表示，且具有相同或类似的功能，并省略描述。
在本实施例中，第二半导体元件130可以包括芯片134、模封材料136以及重布线路138。芯片134的接垫面向远离于第一半导体元件110，且模封材料136包覆芯片134。重布线路138设置于模封材料136上且电性连接至芯片134以及第二导电柱132。
图15是依据本发明一实施例的芯片封装结构的剖面示意图。请参照图15，在本实施例中，芯片封装结构100f与图14所显示的芯片封装结构100e类似，其相同或类似的构件以相同或类似的标号表示，且具有相同或类似的功能，并省略描述。
请参照图15，在本实施例中，第二导电柱132形成于第二半导体元件130上，且第二导电柱132连接于第一半导体元件110的第一主动面112以及第二半导体元件130之间，以使第二半导体元件130通过第二导电柱132电性连接至第一半导体元件110。在本实施例中，第二半导体元件130包括芯片134、模封材料136以及重布线路138。芯片134的接垫面向第一半导体元件110，且模封材料136包覆芯片134。重布线路138设置于模封材料136上，以使重布线路138设置于第一半导体元件110的第一主动面112以及模封材料136之间。重布线路138被配置以电性连接芯片134以及第一半导体元件110。
在形成第一密封体120之前，于第二半导体元件130上形成多个第二导电柱132。在本实施例中，第二导电柱132可以首先形成于第二半导体元件130上以与重布线路138电性连接。接着，将第二半导体元件130以及第二导电柱132配置于第一半导体元件110的第一主动面112上，但本发明不限于此。在本实施例中，各个第二导电柱132为类似于第一导电柱116的实心柱，并且第二导电柱132被第一密封体120包覆且连接于第一主动面112以及第二半导体元件130之间，以使第二半导体元件130通过第二导电柱132电性连接至第一半导体元件110。
图16至图19是依据本发明一实施例的芯片封装结构的制造方法的剖面示意图。请参照图16至图19，在本实施例中，芯片封装结构100g的制造过程与图10至图13所显示的芯片封装结构100d的制造过程类似。其相同或类似的构件以相同或类似的标号表示，且具有相同或类似的功能，并省略描述。
在本实施例中，图16至图19所显示的制造过程可以于图12所显示的步骤之后进行，也就是例如为于第一重布线路层122形成于第一密封体120上，且移除第一载板10的步骤之后进行。请参照图16，形成第三半导体元件140于第一重布线路层122上。接着，于第三半导体元件140的接垫上形成多个第三导电柱142以与第三半导体元件140电性连接。各个第三导电柱142为类似于第一导电柱116的实心柱。也就是说，各个第三导电柱142的上表面的尺寸与各个第三导电柱142的下表面的尺寸大致相同。接着，于第一重布线路层122上形成多个贯通柱144。各个贯通柱144也是类似于第一导电柱116的实心柱。也就是说，各个贯通柱144的上表面的尺寸与各个贯通柱144的下表面的尺寸大致相同。
请参照图17，形成第四半导体元件160于第三半导体元件140上。接着，于第四半导体元件160的接垫上形成多个第四导电柱162以与第四半导体元件160电性连接。各个第四导电柱162为实心柱。在本实施例中，各个第四导电柱162的上表面的尺寸与各个第四导电柱162的下表面的尺寸大致相同。
接着，请参照图18，形成第二密封体150以密封第三半导体元件140、第四半导体元件160、第三导电柱142、第四导电柱162以及贯通柱144。第二密封体150暴露出第三导电柱142的上表面、第四导电柱162的上表面以及贯通柱142的上表面。在本实施例中，第二密封体150可以先完全覆盖第三导电柱142的上表面、第四导电柱162的上表面以及贯通柱142的上表面。接着，可以对第二密封体150进行研磨处理，直到露出第三导电柱142的上表面、第四导电柱162的上表面以及贯通柱144的上表面。通过这样的结构，可以进一步减小芯片封装结构的厚度。此外，可以省略形成半导体元件140、160的导通孔的处理。因此，可以降低芯片封装结构的制造成本。接着，形成第一重布线路层122于如图2所示的第一密封体120上。第一重布线路层122通过第一导电柱116电性连接至第一半导体元件110。此外，由于于此省略了激光钻孔处理，因此可以避免半导体元件140、160的接垫因为激光所造成的损坏。除此之外，预先形成的导电柱162、142、144是实心圆柱，而通过激光处理所形成的通孔为内部具有空隙的锥形。因此，导电柱162、142、144可以具有较好的电性，并且可以减小任何两相邻的导电柱162、142、144之间的间隙。
接着，请参照图19，形成第二重布线路层152于第二密封体150上，并且移除第一载板10。第二重布线路层152电性连接至第三导电柱142、贯通柱144以及第四导电柱162。此外，可以形成多个焊球170于第二重布线路层152上并且电性连接至第二重布线路层152，以使芯片封装结构100g可以通过焊球170电性连接至外部元件。此时，基本上完成了芯片封装结构100g的制造过程。
综上所述，在本发明中，至少一半导体元件设置于载板上，且导电柱形成于半导体元件上。然后，形成密封体以包覆半导体元件并暴露出导电柱的顶表面，且形成重布线路层于密封体上以电性连接半导体元件。然后，于重布线路层上堆叠多个半导体元件，且可以重复形成导电柱/贯通柱、密封体以及重布线路层的步骤，以形成堆叠型芯片封装结构。
通过这样的结构，可以进一步减小芯片封装结构的厚度，且可以省略通过激光钻孔形成用于半导体元件的导通孔的处理，从而降低芯片封装结构的制造成本。此外，由于于此省略了激光钻孔处理，因此可以避免半导体元件的接垫因为激光所造成的损坏。除此之外，本发明的导电柱是预先形成于半导体元件上的实心圆柱，而通过激光处理所形成的通孔为内部具有空隙的锥形。因此，导电柱可以具有较好的电性，并且可以减小任何两相邻的导电柱之间的间隙。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中技术人员，在不脱离本发明的精神和范围内，当可作些许的更改与润饰，故本发明的保护范围当视后附的权利要求书所界定的为准。

Claims (4)

1.一种芯片封装结构，其特征在于，包括：
第一半导体元件，具有第一主动面，且所述第一半导体元件包括位于所述第一主动面上的多个第一接垫；
多个第一导电柱，形成于所述多个第一接垫上，其中各个所述多个第一导电柱为包括第一顶表面以及第一底表面的实心柱，且所述第一顶表面的尺寸与所述第一底表面的尺寸基本上相同；
第二半导体元件，配置于所述第一主动面上，其中所述第二半导体元件包括：
芯片，所述芯片的接垫面向远离所述第一半导体元件；
模封材料，包覆所述芯片；以及
重布线路，形成于所述模封材料上，且所述重布线路与所述芯片电性连接；
多个第二导电柱，形成于所述第二半导体元件上，其中各个所述多个第二导电柱为包括第二顶表面以及第二底表面的实心圆柱；
第一密封体，包覆所述第一半导体元件、所述多个第一导电柱、所述第二半导体元件以及所述多个第二导电柱，其中：
所述第一密封体暴露出各个所述多个第一导电柱的所述第一顶表面；
所述第一密封体暴露出各个所述多个第二导电柱的所述第二顶表面；且
各个所述多个第一导电柱的所述第一顶表面、各个所述多个第二导电柱的所述第二顶表面以及所述第一密封体的顶表面共面；
第一重布线路层，形成于所述第一密封体上，且所述第一重布线路层与所述多个第一导电柱以及所述多个第二导电柱电性连接，以使所述第二半导体元件经由所述多个第二导电柱、所述第一重布线路层以及所述多个第一导电柱电性连接所述第一半导体元件；
第三半导体元件，配置于所述第一重布线路层上；
多个第三导电柱，形成于所述第三半导体元件上且电性连接所述第三半导体元件，其中各个所述多个第三导电柱为实心圆柱；
多个贯通柱，形成于所述第一重布线路层上，其中各个所述多个贯通柱为实心圆柱；以及
第二密封体，包覆所述第三半导体元件、所述多个第三导电柱以及所述多个贯通柱，其中所述第二密封体暴露出各个所述多个第三导电柱的上表面以及各个所述多个贯通柱的上表面。
2.根据权利要求1所述的芯片封装结构，其特征在于，还包括：
第四半导体元件，配置于所述第三半导体元件上；
多个第四导电柱，形成于所述第四半导体元件上且电性连接所述第四半导体元件，其中各个所述多个第四导电柱为实心圆柱，其中所述第二密封体包覆所述第四半导体元件以及所述多个第四导电柱，且所述第二密封体暴露出各个所述多个第四导电柱的上表面；以及
第二重布线路层，形成于第二密封体上，且所述第二重布线路层与所述多个第三导电柱、所述多个贯通柱以及所述多个第四导电柱电性连接。
3.一种芯片封装结构，其特征在于，包括：
第一半导体元件，具有第一主动面，且所述第一半导体元件包括位于所述第一主动面上的多个第一接垫；
多个第一导电柱，形成于所述多个第一接垫上，其中各个所述多个第一导电柱为包括第一顶表面以及第一底表面的实心柱，且所述第一顶表面的尺寸与所述第一底表面的尺寸基本上相同；
第二半导体元件，配置于所述第一主动面上，其中所述第二半导体元件包括：
芯片，所述芯片的接垫面向所述第一半导体元件；
模封材料，包覆所述芯片；以及
重布线路，形成于所述模封材料上，且所述重布线路与所述芯片电性连接，其中所述重布线路形成于所述第一主动面以及所述模封材料之间；
多个第二导电柱，形成于所述第二半导体元件上，其中各个所述多个第二导电柱为包括第二顶表面以及第二底表面的实心圆柱，其中所述多个第二导电柱连接于所述第一主动面以及所述重布线路之间；
第一密封体，包覆所述第一半导体元件、所述多个第一导电柱、所述第二半导体元件以及所述多个第二导电柱，其中：
所述第一密封体暴露出各个所述多个第一导电柱的所述第一顶表面；
所述第一密封体暴露出各个所述多个第二导电柱的所述第二顶表面；且
各个所述多个第一导电柱的所述第一顶表面以及所述第一密封体的顶表面共面；
第一重布线路层，形成于所述第一密封体上，且所述第一重布线路层与所述多个第一导电柱电性连接；
第三半导体元件，配置于所述第一重布线路层上；
多个第三导电柱，形成于所述第三半导体元件上且电性连接所述第三半导体元件，其中各个所述多个第三导电柱为实心圆柱；
多个贯通柱，形成于所述第一重布线路层上，其中各个所述多个贯通柱为实心圆柱；以及
第二密封体，包覆所述第三半导体元件、所述多个第三导电柱以及所述多个贯通柱，其中所述第二密封体暴露出各个所述多个第三导电柱的上表面以及各个所述多个贯通柱的上表面。
4.一种封装结构的制造方法，其特征在于，包括：
形成第一半导体元件于第一载板上，其中所述第一半导体元件具有第一主动面，且所述第一半导体元件包括位于所述第一主动面上的多个第一接垫；
形成多个第一导电柱于所述多个第一接垫上，其中各个所述多个第一导电柱为包括顶表面以及底表面的实心圆柱，且所述顶表面的直径与所述底表面的直径基本上相同；
配置第二半导体元件于所述第一主动面上，其中所述第二半导体元件包括芯片且所述芯片的接垫面向远离所述第一半导体元件，包覆所述芯片的模封材料以及形成于所述模封材料上的重布线路且所述重布线路与所述芯片电性连接；
形成多个第二导电柱于所述第二半导体元件上，其中各个所述多个第二导电柱为包括第二顶表面以及第二底表面的实心圆柱；
形成第一密封体以包覆所述第一半导体元件、所述多个第一导电柱、所述第二半导体元件以及所述多个第二导电柱，其中所述第一密封体暴露出各个所述多个第一导电柱的所述顶表面以及各个所述多个第二导电柱的所述第二顶表面，且各个所述多个第一导电柱的所述顶表面、各个所述多个第二导电柱的所述第二顶表面以及所述第一密封体的顶表面共面；
形成第一重布线路层于所述第一密封体上，其中所述第一重布线路层与所述多个第一导电柱以及所述多个第二导电柱电性连接，以使所述第二半导体元件经由所述多个第二导电柱、所述第一重布线路层以及所述多个第一导电柱电性连接所述第一半导体元件；
配置第三半导体元件于所述第一重布线路层上；
形成多个第三导电柱于所述第三半导体元件上且电性连接所述第三半导体元件，其中各个所述多个第三导电柱为实心圆柱；
形成多个贯通柱于所述第一重布线路层上，其中各个所述多个贯通柱为实心圆柱；
形成第二密封体以包覆所述第三半导体元件、所述多个第三导电柱以及所述多个贯通柱，其中所述第二密封体暴露出各个所述多个第三导电柱的上表面以及各个所述多个贯通柱的上表面；以及
移除所述第一载板。
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