CN106169459A - 半导体封装组件及其形成方法 - Google Patents

半导体封装组件及其形成方法 Download PDF

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Publication number
CN106169459A
CN106169459A CN201610302315.0A CN201610302315A CN106169459A CN 106169459 A CN106169459 A CN 106169459A CN 201610302315 A CN201610302315 A CN 201610302315A CN 106169459 A CN106169459 A CN 106169459A
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China
Prior art keywords
semiconductor
assembly
encapsulation
semiconductor packages
conducting wire
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CN201610302315.0A
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Inventor
林子闳
萧景文
彭逸轩
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MediaTek Inc
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MediaTek Inc
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Publication of CN106169459A publication Critical patent/CN106169459A/zh
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Abstract

本发明公开了一种半导体封装组件及其形成方法，可以提高设计时的灵活性。其中，该半导体封装组件包括：第一封装和第二封装，并且该第二封装接合至该第一封装。其中，该第一封装包括：第一组件和第一RDL(重分布层)结构，该第一RDL结构耦接至该第一组件并且该第一RDL结构含有第一导电线路。该第二封装包括：第二组件和第二RDL结构。其中，该第二RDL结构耦接至该第二组件并且该第二RDL结构含有第二导电线路，其中该第二导电线路直接接触前述的第一导电线路。

Description

半导体封装组件及其形成方法
技术领域
本发明涉及封装技术领域，尤其涉及一种三维(3D)半导体封装组件及其形成方法。
背景技术
由于对电子产品的微型化及多功能性的需求，使得半导体工业经历了持续快速的增长。提高了的集成密度允许更多的芯片(chip)或晶粒(die)集成于半导体封装中，例如2维(2D)半导体封装。但是，2D半导体封装存在物理限制。例如，当将2颗以上的具有不同功能的晶粒放置于2D半导体设备中时，对需要的更复杂的设计和布局的开发变得更加困难。
尽管发展并普遍使用了3D集成电路及堆叠晶粒，但是集成于传统3D半导体封装中的多个晶粒被限制在具有相同的尺寸。另外，3D半导体封装技术遭受各种可能导致制造良品率下降的问题。
因此，需要开发一种半导体封装组件及其形成方法，能够缓解或消除上述的问题。
发明内容
有鉴于此，本发明提供一种半导体封装组件及其形成方法，可以提高设计灵活性。
本发明提供了一种半导体封装组件，包括第一封装和第二封装，该第二封装接合至该第一封装；其中，该第一封装包括：第一组件和第一重分布层结构，该第一重分布层结构耦接至该第一组件，并且该第一重分布层结构包括：第一导电线路；其中，该第二封装包括：第二组件和第二重分布层结构，该第二重分布层结构耦接至该第二组件，并且该第二重分布层结构包括：第二导电线路，直接接触该第一导电线路。
其中，该第一封装为第一半导体封装，该第一组件为第一半导体晶粒，该第二封装为第二半导体封装，该第二组件为第二半导体晶粒；其中，该第二半导体晶粒的主动面朝向该第一半导体晶粒的主动面。
其中，该第一封装为第一半导体封装，该第一组件为第一半导体晶粒，并且该第二组件为无源设备。
其中，该第一封装包括：多于一个的该第一组件，及/或者，该第二封装包括：多于一个的该第二组件。
其中，该第一导电线路和该第二导电线路均包括铜。
其中，该第一重分布层结构还包括：第一介电层，围绕该第一导电线路；该第二重分布层结构还包括：第二介电层，围绕该第二导电线路并且直接接触该第一介电层。
其中，该第一封装还包括：第一成型模料，围绕该第一组件的侧壁。
其中，该第一重分布层结构覆盖该第一成型模料。
其中，该第一封装还包括：通孔结构，穿过该第一成型模料并耦接至该第一重分布层结构。
其中，还包括：导电组件，耦接至该通孔结构，其中该第一组件设置在该第一重分布层结构和该导电组件之间。
其中，该第二封装还包括：第二成型模料，围绕该第二组件的侧壁。
其中，该第二重分布层结构覆盖该第二成型模料。
其中，该第一组件和该第二组件之一为有源设备，另一为无源设备。
其中，该第一封装包括：一个或多于一个的该第一组件，该第二封装包括：一个或多于一个的该第二组件，并且至少一个该第一组件与至少一个该第二组件具有不同的尺寸。
本发明还提供了一种形成半导体封装组件的方法，包括：形成第一半导体封装，其中该第一半导体封装包括：第一半导体晶粒和第一重分布层结构，该第一重分布层结构耦接至该第一半导体晶粒并且该第一重分布层结构包括第一导电线路；形成第二半导体封装，其中该第二半导体封装包括：第二半导体晶粒，其中该第二半导体晶粒的主动面朝向该第一半导体晶粒的主动面，以及第二重分布层结构，耦接至该第二半导体晶粒以及包括：第二导电线路；以及将该第二半导体封装接合至该第一半导体封装，其中，该第一导电线路直接接触该第二导电线路。
其中，该第二半导体封装使用熔融接合方式接合至该第一半导体封装。
其中，进一步包括：在将该第二半导体封装接合至该第一半导体封装期间，对该第一半导体封装及该第二半导体封装应用超声能量。
其中，形成该第二半导体封装的步骤包括：在第二载体基底上形成通孔结构；将该第二半导体晶粒接合至该第二载体基底上；在该第二载体基底上形成第二成型模料，其中，该第二成型模料围绕该通孔结构和该第二半导体晶粒的侧壁，其中该第二成型模料露出该通孔结构的顶面以及该第二半导体晶粒的顶面；以及在该第二半导体晶粒和该第二成型模料上形成该第二重分布层结构。
其中，进一步包括：在将该第二半导体封装接合至该第一半导体封装之后，移除该第二载体基底。
其中，进一步包括：在移除该第二载体基底之后，在该第二半导体封装之上形成导电组件。
其中，形成该第一半导体封装的步骤包括：将该第一半导体晶粒接合至第一载体基底之上；在该第一载体基底上形成第一成型模料，其中，该第一成型模料围绕该第一半导体晶粒的侧壁并且露出该第一半导体晶粒的顶面；以及在该第一半导体晶粒和该第一成型模料上形成该第一重分布层结构。
其中，进一步包括：在将该第二半导体封装接合至该第一半导体封装之后，移除该第一载体基底；以及对该第一半导体封装和该第二半导体封装执行切割工艺。
其中，该第一半导体封装的形成包括：将多于一颗的该半导体晶粒接合至该第一载体基底；其中该第一成型模料进一步围绕该第一半导体晶粒的侧壁，并且露出该第一半导体晶粒的顶面。
本发明提供了一种形成半导体封装组件的方法，包括：形成第一半导体封装，其中该第一半导体封装包括：第一半导体晶粒和第一重分布层结构，该第一重分布层结构耦接至该第一半导体晶粒并且包括：第一导电线路；形成第二封装，其中该第二封装包括：无源设备和第二重分布层结构，该第二重分布层结构耦接至该无源设备并且包括：第二导电线路；以及将该第二封装接合至该第一半导体封装，其中，该第一导电线路直接接触该第二导电线路。
本发明实施例的有益效果是：
以上的半导体封装组件及其形成方法，通过将两个封装(如半导体封装)接合起来，并使两个封装的导电线路直接接触，从而形成半导体封装组件，因此支持该两个封装在接合起来之前分别制造，从而提高了设计灵活性。
附图说明
通过阅读接下来的详细描述以及参考所附的附图所做的示例，可以更全面地理解本发明，其中：
图1A～1C为根据本发明一些实施例的各个阶段的形成半导体封装的方法的横截面示意图。
图2A～2C为根据本发明一些实施例的各个阶段的形成半导体封装的方法的横截面示意图。
图3A～3E为根据本发明一些实施例的各个阶段的形成半导体封装组件的方法的横截面示意图。
图4为根据本发明一些实施例的半导体封装组件的横截面示意图。
图5为根据本发明一些实施例的半导体封装组件的横截面示意图。
具体实施方式
以下描述为实现本发明的一种可预期的模式。该描述用于说明本发明的一般原理的目的，并且不应当理解为具有限制性意义。通过参考所附的权利要求可确定本发明的范围。
本发明将参考特定实施例及参考确定的附图来描述，但是本发明不限制于此，并且本发明仅由权利要求来限制。描述的附图仅是原理图并且不作为限制。在附图中，出于说明目的而夸大了某些组件的尺寸，并且该些组件的尺寸并非按比例绘制。尺寸和相对尺寸不对应本发明实践中的真实尺寸。
本发明的实施例提供了一种3D系统封装(System-In-Package，SIP)半导体封装组件。该半导体封装组件集成了2个以上的组件或晶粒，从而可以降低使用该半导体封装组件的电子产品的尺寸。分别制造该些组件或晶粒，接着将该些组件或晶粒集成于半导体封装组件中。如此，该些组件或晶粒不限制于具有相同的尺寸及/或功能。显著地改善了半导体封装组件的设计灵活性。另外，提前测量该些组件或晶粒，以确保半导体封装组件仅包含合格组件或合格晶粒。如此，可以显著地减轻或消除由于多个缺陷组件或缺陷晶粒所导致的良率损失。因此，降低了半导体封装组件的制造成本。
图1A～1C为本发明一些实施例的各个阶段的形成半导体封装的方法的横截面示意图。在图1A～1C中描述的各个阶段之前、期间和/或之后，可以提供附加的操作。对于不同实施例，可以替换或者省略上述各个阶段中的一部分。附加的特征可以添加至半导体封装中。对于不同实施例，可以替换或者省略以下描述的特征中的一部分。
如图1A所示，提供了第一载体基底100A。在一些实施例中，该第一载体基底100A可以是晶圆或者面板(panel)。第一载体基底100A可以包括：玻璃或者其他合适的支撑材料。
如图1A所示，多个第一组件110A接合在该第一载体基底100A之上。根据本发明一些实施例，该多个第一组件110A均为已知合格(known-good)组件。换句话说，无缺陷组件接合(bond)在该第一载体基底100A之上。在一些实施例中，该多个第一组件110A和该第一载体基底100A可以通过诸如胶水或其他合适的胶黏材料等的胶黏层胶黏在一起。
在一些实施例中，第一组件110A可以为有源设备并且可被称为第一半导体晶粒(或芯片)110A。第一半导体晶粒110A可以包括：晶体管或者其他合适的有源元件。例如，第一半导体晶粒110A可以为逻辑晶粒，该逻辑晶粒包括：CPU(Central Processing Unit，中央处理单元)、GPU(Graphics Processing Unit，图形处理单元)、DRAM(Dynamic Random Access Memory，动态随机存取内存)控制器或他们的任意组合。在其他一些实施例中，第一组件110A可以为诸如IPD(Integrated Passive Devices，集成无源设备)等的无源设备。第一组件110A可以包括：电容、电阻、电感、变容二极管或者其他合适的无源元件。
如图1B所示，在第一载体基底100A之上形成第一成型模料(moldingcompound)120A。该第一成型模料120A围绕第一组件110A的侧壁，并且没有覆盖第一组件110A的顶面和底面。
在一些实施例中，第一成型模料120A由诸如环氧树脂、树脂、可塑聚合物或者其他合适的模塑材料等非导电材料形成。在一些实施例中，第一成型模料120A在大致上为液体时应用，然后通过化学反应固化。在其他一些实施例中，第一成型模料是UV(紫外)或热固化聚合物，并且作为胶体或可塑固体而应用，然后通过UV或热固化工艺进行固化。第一成型模料120A可以按照模型来固化。
在一些实施例中，沉积的第一成型模料120A覆盖第一组件110A的顶面，接着执行研磨(grinding)工艺以使该沉积的第一成型模料120A薄化。如此，薄化的第一成型模料120A露出第一组件110A的顶面。在一些实施例中，第一成型模料120A的顶面和底面分别与第一组件110A的顶面和底面共平面。
如图1C所示，在第一成型模料120A上形成第一RDL(Redistribution Layer，重分布层)结构130A，并且该第一RDL结构130A耦接至该第一组件110A，该第一RDL结构130A也称为扇出(fan-out)结构。如此，形成第一(半导体)封装A。在一些实施例中，该第一(半导体)封装A为晶圆级扇出封装。
该第一RDL结构130A覆盖第一成型模料120A并且直接接触该第一成型模料120A。在一些实施例中，该第一RDL结构130A包括：一个或更多的导电线路140A，设置在IMD(Inter-Metal Dielectric，金属间介电)层150A内并由该IMD层150A围绕。第一组件110A电性连接至第一RDL结构130A中的导电线路140A。IMD层150A可以包括：多个次介电层，依次地堆叠在第一成型模料120A及第一组件110A之上。例如，第一层位的导电线路140A设置在第一层位的次介电层上，并且由第二层位的次介电层覆盖。第二层位的导电线路140A设置在第二层位的次介电层上，并且由第三层位的次介电层覆盖。
在一些实施例中，IMD层150A可以由有机材料或非有机材料形成，其中该有机材料包括：聚合物基(polymer base)材料，该非有机材料包括：氮化硅(SiNx)、氧化硅(SiOx)、石墨烯，等等。在一些实施例中，IMD层150A为高k值介电层(k为介电层的介电常数)。在其他一些实施例中，IMD层150A可以由光敏性材料形成，包括：干膜光阻。
导电线路140A的接垫部分从第一RDL结构130A的顶面露出。例如，导电线路140A的接垫部分从IMD层150A的开口露出，并连接至接下来形成的导电组件。需要注意的是，附图中所示的导电线路140A和IMD层150A的数量和配置仅是示例而不是对本发明的限制。在一些实施例中，导电线路140A包括：铜或者其他合适的具有良好扩散性的导电材料。
图2A～2C为根据本发明一些实施例的各个阶段的形成半导体封装的方法的横截面示意图。在图2A～2C中描述的各个阶段之前、期间和/或之后，可以提供附加的操作。针对不同实施例，可以替换或者省略描述的各个阶段中的一部分。附加的特征可以添加至半导体封装中。对于不同实施例，可以替换或者省略以下描述的特征中的一部分。
如图2A所示，提供了第二载体基底100B。在一些实施例中，该第二载体基底100B可以为晶圆或者面板。第二载体基底100B可以包括：玻璃或者其他合适的支撑材料。
如图2A所示，多个通孔结构(vias)160形成在第二载体基底100B上。该通孔结构160可以是TIV(Through Interposer Vias，中介层通孔结构)。在一些实施例中，该通孔结构160可以是铜柱或者其他合适的导电结构。在一些实施例中，通过电镀工艺或者其他合适的工艺形成通孔结构160。
如图2A所示，多个第二组件110B接合在第二载体基底100B上。根据本发明一些实施例，第二组件110B为已知合格组件。换句话说，无缺陷组件接合在第二载体基底100B上。在一些实施例中，第二组件110B及第二载体基底100B通过胶黏层(诸如胶水或者其他合适的胶黏材料)而胶黏在一起。在一些实施例中，每个第二组件110B设置在两个通孔结构160之间。在一些实施例中，在两个第二组件110B之间设置一个或更多的通孔结构160。
在一些实施例中，第二组件110B可以为有源设备并且可以被称为第二半导体晶粒(或芯片)110B。第二半导体晶粒110B可以包括：晶体管或者其他合适的有源元件。例如，第二半导体晶粒110B可以是逻辑晶粒，该逻辑晶粒包括：CPU、GPU、DRAM控制器或者他们的任意组合。在其他一些实施例中，第二组件110B可以为无源设备，诸如IPD。第二组件110B可以包括：电容、电阻、电感、变容二极管和其他合适的无源元件。
如图2B所示，在第二载体基底100B上形成第二成型模料120B。第二成型模料120B围绕通孔结构160以及第二组件110B的侧壁，并且没有覆盖第二组件110B的顶面和底面及通孔结构160的顶面和底面。也就是，通孔结构160穿透或者穿过第二成型模料120B。
在一些实施例中，第二成型模料120B由非导电材料形成，诸如环氧树脂、树脂、可塑聚合物或者其他合适的成型模料。在一些实施例中，第二成型模料120B在大致上为液体时应用，接着通过化学反应固化。在其他一些实施例中，第二成型模料120B为UV或热固化聚合物，并且作为胶体或可塑固体而应用，然后通过UV或热固化工艺进行固化。第二成型模料120B可以按照模型固化。
在一些实施例中，沉积的第二成型模料120B覆盖第二组件110B的顶面及通孔结构160的顶面，接着执行研磨工艺薄化第二成型模料120B。如此，薄化后的第二成型模料120B露出第二组件110B的顶面及通孔结构160的顶面。在一些实施例中，第二成型模料120B的顶面和底面分别与第二组件110B的顶面和底面共平面。在一些实施例中，第二成型模料120B的顶面和底面分别与通孔结构160的顶面和底面共平面。
根据本发明一些实施例，在将第二组件110B接合至第二载体基底100B之前，预先薄化第二组件110B。如此，第二组件110B和通孔结构160大致上具有相同的厚度，从而有利于第二组件110B和通孔结构160的露出。例如，薄化半导体晶圆并且接着将其切割成半导体晶粒(或芯片)，从而形成第二组件110B。第二组件110B可以通过机械研磨工艺、化学机械磨光(polishing)工艺、铣削(milling)工艺或者其他合适的工艺而薄化。
如图2C所示，在第二成型模料120B上形成第二RDL结构130B，该第二RDL结构130B耦接至该第二组件110B和通孔结构160。如此，形成第二(半导体)封装B。在一些实施例中，第二(半导体)封装B为晶圆级扇出封装。第二RDL结构130B覆盖第二成型模料120B并且可以直接接触第二成型模料120B。在一些实施例中，第二RDL结构130B包括：一个或更多的导电线路140B，设置在IMD层150B内并由IMD层150B围绕。第二组件110B电性连接至第二RDL结构130B的导电线路140B。导电线路140B的接垫部分从第二RDL结构130B的顶面露出。第二RDL结构130B的结构类似或相同于第一RDL结构130A，细节如前所述。需要注意的是，附图中所示的导电线路140B和IMD层150B的数量和配置仅为示例而不是对本发明的限制。在一些实施例中，导电线路140B包括：铜或者其他合适的具有良好扩散性的导电材料。
图3A～3E为根据本发明一些实施例的各个阶段的形成半导体封装组件的方法的横截面示意图。在图3A～3C中描述的各个阶段之前、期间和/或之后，可以提供附加的操作。针对不同实施例，可以替换或者省略描述的各个阶段中的一部分。附加的特征可以添加至半导体封装组件中。对于不同实施例，可以替换或者省略以下描述的特征中的一部分。
如图3A所示，第二封装B接合至第一封装A，使得第一RDL结构130A夹在第一组件110A和第二RDL结构130B之间。第一RDL结构130A的导电线路140A直接电性连接至第二RDL结构130B的导电线路140B。例如，导电线路140A和140B的接垫部分彼此直接接触。第一RDL结构130A的IMD层150A和第二RDL结构130B的IMD层150B也彼此直接接触。在一些实施例中，第一组件110A的主动面朝向第二组件110B的主动面。
根据本发明一些实施例，第一封装A和第二封装B使用熔融接合(fusionbonding)方式接合在一起。在一些实施例中，第一封装A和第二封装B使用铜熔融接合方式接合在一起。例如，导电线路140A和140B均包括铜，以便于第一封装A和第二封装B通过铜接合处接合在一起。第一封装A和第二封装B之间的接合处不包括焊锡。
第二封装B放置在第一封装A之上。导电线路140A直接贴近导电线路140B。在一些实施例中，导电线路140A大致对齐导电线路140B。在一些实施例中，导电线路140A与导电线路140B具有相同的布局。导电线路140A与导电线路140B大致上完全重叠。在其他一些实施例中，导电线路140A与导电线路140B具有不同的布局。导电线路140A与导电线路140B至少部分重叠，以便于建立第一封装A和第二封装B之间的电连接路径。
然后，对第一封装A和第二封装B执行热处理。如此，导电线路140A和导电线路140B中的熔化的金属(铜)使得第二封装B与第一封装A连接。导电线路140A直接连接至导电线路140B，而无需接合结构(如导电柱、导电凸块或者导电膏结构)。在一些实施例中，在150℃～250℃的温度范围内执行热处理，但是本发明不限制于此。
在一些实施例中，在热处理期间，将超声能量应用至第一封装A和第二封装B。超声能量有利于导电线路140A和导电线路140B之间的金属扩散。如此，加强了第一封装A和第二封装B之间的接合处，使得第一封装A和第二封装B紧紧地接合在一起。
在一些实施例中，在将第二封装B放置在第一封装A上之前，对第一封装A和/或第二封装B执行平面化(planarization)工艺。该平面化工艺用于降低表面粗糙度并且提供具有平坦接合面的第一封装A和/或第二封装B。例如，在将第二封装B放置在第一封装A上之前，第一RDL结构130A和/或第二RDL结构130B的表面已经预先平面化。如此，第二封装B可以紧密地接合至第一封装A。
如图3B所示，从第二封装B移除第二载体基底100B。如此，露出第二组件110B和通孔结构160。第二组件110B的侧壁及通孔结构160仍然由第二成型模料120B围绕。在一些实施例中，移除胶黏层的胶黏性能，以使第二载体基底100B脱胶，该胶黏层用于接合第二组件110B和第二载体基底100B。
如图3C所示，导电组件190形成在第二封装B上并且远离第一封装A。换句话说，导电组件190和第一封装A设置在第二封装B的两相对侧上。第二组件110B设置在第二RDL结构130B和导电组件190之间。
在一些实施例中，导电组件190通过通孔结构160和第二RDL结构130B电性连接或耦接至第二组件110B。在一些实施例中，导电组件190进一步通过通孔结构160、第二RDL结构130B及第一RDL结构130A电性连接至第一组件110A。
在一些实施例中，导电组件190由RDL结构200及该RDL结构200上的导电结构210构成。在一些实施例中，该RDL结构200包括：一个或更多的导电线路220，设置在IMD层230中并由IMD层230围绕。导电线路220的接垫部分从RDL结构200的顶面露出。RDL结构200的结构类似或者相同于RDL结构130A的结构，详细如前所述。
导电结构210电性连接至导电线路220中露出的接垫部分。通孔结构160通过导电线路220电性连接或耦接至导电结构210。在一些实施例中，导电结构210为接合球(如焊锡球)，或者其他合适的导电结构。需要注意，附图中所示的导电结构210和导电线路220的数量和配置仅是示例而不是对本发明的限制。
在其他一些实施例中，导电组件190由导电结构210构成。通孔结构160直接电性连接至导电结构210。通孔结构160可以通过一个或更多的导电层(诸如UBM(Under Bump Metallization，凸块下金属)层)电性连接至导电结构210。
如图3D所示，从第一封装A移除第一载体基底100A。如此，露出第一组件110A。第一组件110A的侧壁仍由第一成型模料120A围绕。在一些实施例中，移除胶黏层的胶黏性能，以使第一载体基底100A脱胶，该胶黏层用于接合第一组件110A和第一载体基底100A。
然后，对已接合的封装A和B执行切割(singulation)工艺。沿切割道L切割已接合的封装A和B，以将已接合的封装A和B分为多个半导体封装组件300。该半导体封装组件300均为SIP半导体封装组件，并且晶圆级扇出封装集成于该半导体封装组件300中。
如图3E所示，每个半导体封装组件300包括：一个第一组件110A和两个第二组件110B。半导体封装组件300可以包括：多于2个的第二组件110B。在一些实施例中，第一组件110A的尺寸不同于第二组件110B的尺寸。例如，第一组件110A的尺寸大于第二组件110B的尺寸。在一些实施例中，多个第二组件110B具有相同的尺寸。在其他一些实施例中，该第二组件110B具有不同的尺寸。
在一些实施例中，第一组件110A和第二组件110B具有相同的功能。因此，半导体封装组件300为同质集成(homogeneous integration)。在其他一些实施例中，第一组件110A的功能不同于一个或多个第二组件110B的功能。因此，半导体封装组件300为异质集成(heterogeneous integration)。
在一些实施例中，第一组件110A和第二组件110B之一为SOC(system-on-chip，片上系统)，另一为无源设备。在一些实施例中，第一组件110A和第二组件110B之一为AP(Analog Processor，模拟处理器)，另一为DP(DigitalProcessor，数字处理器)。在一些实施例中，第一组件110A和第二组件110B之一为BB(baseband，基带)组件，另一为RF(Radio-Frequency，射频)组件。
例如，在一些实施例中，第一组件110A为有源设备，同时该第二组件110B为彼此具有相同或不同功能的无源设备。在一些实施例中，第二组件110B之一和第一组件110A为具有相同或不同功能的有源设备，同时另一第二组件110为无源设备。在其他一些实施例中，第一组件110A和第二组件110B为具有不同功能的有源设备。
可选地，在一些实施例中，第一组件110A为无源设备，同时该多个第二组件110B为彼此具有相同或不同功能的有源设备。在一些实施例中，多个第二组件110B之一和第一组件110A为具有相同或不同功能的无源设备，同时另一第二组件110为有源设备。
可以对本发明实施例做出许多变形和/或修改。图4和图5均为根据本发明一些实施例的半导体封装组件的横截面示意图。图4和图5中相同于图3E的组件，采用与图3E相同的参考符号来标记，并且出于简洁而不再描述。
参考图4，示出了一种半导体封装组件400。该半导体封装组件400相似于图3E中所示的半导体封装组件300。半导体封装组件300和400之间的主要不同在于：半导体封装组件300包括：一个第一组件110A，而半导体封装组件400包括：两个第一组件110A。半导体封装组件400还可以包括：多于两个的第一组件110A。
在一些实施例中，多个第一组件110A之间具有相同的尺寸。在其他一些实施例中，多个第一组件110A之间具有不同的尺寸。在一些实施例中，第一组件110A的尺寸不同于第二组件110B的尺寸。例如，第一组件110A的尺寸大于第二组件110B的尺寸。在一些实施例中，多个第一组件110A之间具有相同的功能。在其他一些实施例中，多个第一组件110A之间具有不同的功能。
参考图5，示出了一种半导体封装组件500。该半导体封装组件500类似于图3E所示的半导体封装组件300。半导体封装组件300和500之间的主要不同在于：半导体封装组件300的通孔结构160形成于第二封装B之中，而半导体封装组件500的通孔结构160形成于第一封装A之中。如此，半导体封装组件300的导电组件形成在第二封装B之上，而半导体封装组件500的导电组件190形成在第一封装A之上。
在图5中，通孔结构160穿透第一成型模料120A并且电性连接或耦接至第一RDL结构130A。导电组件190和第二封装B设置在第一封装A的两相对侧上。第一组件110A设置在第一RDL结构130A和导电组件190之间。
根据本发明实施例的半导体封装组件及其形成方法提供了各种优势。根据前述实施例，两个以上的组件或晶粒可以集成于半导体封装组件之中。该些组件或晶粒于不同的工艺中制造，并且为已知合格组件或晶粒。如此，该些组件或晶粒的尺寸和/或功能不受限制，从而有利于改善设计灵活性。半导体封装组件的制造良率更进一步显著地增强。
另外，根据前述实施例，使用熔融接合方式将两个封装接合在一起，以形成半导体封装组件。没有必要形成附加的接合结构(诸如导电柱、导电凸块或者导电膏结构)或者附加的胶黏层。相应地，简化了半导体封装组件的工艺流程，并且降低了制造成本。
由于两个封装没有通过任何中介层而直接接合，因此显著地缩短了两个封装之间的信号传送路径/距离。另外，可以进一步增强EM(Electrical Migration，电迁移)能力。另外，降低了半导体封装组件的厚度。因此，显著地改善了半导体封装组件的设备性能。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (24)

1.一种半导体封装组件，其特征在于，包括第一封装和第二封装，该第二封装接合至该第一封装；
其中，该第一封装包括：第一组件和第一重分布层结构，该第一重分布层结构耦接至该第一组件，并且该第一重分布层结构包括：第一导电线路；
其中，该第二封装包括：第二组件和第二重分布层结构，该第二重分布层结构耦接至该第二组件，并且该第二重分布层结构包括：第二导电线路，直接接触该第一导电线路。
2.如权利要求1所述的半导体封装组件，其特征在于，该第一封装为第一半导体封装，该第一组件为第一半导体晶粒，该第二封装为第二半导体封装，该第二组件为第二半导体晶粒；其中，该第二半导体晶粒的主动面朝向该第一半导体晶粒的主动面。
3.如权利要求1所述的半导体封装组件，其特征在于，该第一封装为第一半导体封装，该第一组件为第一半导体晶粒，并且该第二组件为无源设备。
4.如权利要求1所述的半导体封装组件，其中该第一封装包括：多于一个的该第一组件，及/或者，该第二封装包括：多于一个的该第二组件。
5.如权利要求1所述的半导体封装组件，其特征在于，该第一导电线路和该第二导电线路均包括铜。
6.如权利要求1所述的半导体封装组件，其特征在于，该第一重分布层结构还包括：第一介电层，围绕该第一导电线路；该第二重分布层结构还包括：第二介电层，围绕该第二导电线路并且直接接触该第一介电层。
7.如权利要求1所述的半导体封装组件，其特征在于，该第一封装还包括：第一成型模料，围绕该第一组件的侧壁。
8.如权利要求7所述的半导体封装组件，其特征在于，该第一重分布层结构覆盖该第一成型模料。
9.如权利要求7所述的半导体封装组件，其特征在于，该第一封装还包括：通孔结构，穿过该第一成型模料并耦接至该第一重分布层结构。
10.如权利要求9所述的半导体封装组件，其特征在于，还包括：导电组件，耦接至该通孔结构，其中该第一组件设置在该第一重分布层结构和该导电组件之间。
11.如权利要求7所述的半导体封装组件，其特征在于，该第二封装还包括：第二成型模料，围绕该第二组件的侧壁。
12.如权利要求11所述的半导体封装组件，其特征在于，该第二重分布层结构覆盖该第二成型模料。
13.如权利要求1所述的半导体封装组件，其特征在于，该第一组件和该第二组件之一为有源设备，另一为无源设备。
14.如权利要求1所述的半导体封装组件，其特征在于，该第一封装包括：一个或多于一个的该第一组件，该第二封装包括：一个或多于一个的该第二组件，并且至少一个该第一组件与至少一个该第二组件具有不同的尺寸。
15.一种形成半导体封装组件的方法，其特征在于，包括：
形成第一半导体封装，其中该第一半导体封装包括：第一半导体晶粒和第一重分布层结构，该第一重分布层结构耦接至该第一半导体晶粒并且该第一重分布层结构包括第一导电线路；
形成第二半导体封装，其中该第二半导体封装包括：第二半导体晶粒，其中该第二半导体晶粒的主动面朝向该第一半导体晶粒的主动面，以及第二重分布层结构，耦接至该第二半导体晶粒以及包括：第二导电线路；以及
将该第二半导体封装接合至该第一半导体封装，其中，该第一导电线路直接接触该第二导电线路。
16.如权利要求15所述的形成半导体封装组件的方法，其特征在于，该第二半导体封装使用熔融接合方式接合至该第一半导体封装。
17.如权利要求16所述的形成半导体封装组件的方法，其特征在于，进一步包括：在将该第二半导体封装接合至该第一半导体封装期间，对该第一半导体封装及该第二半导体封装应用超声能量。
18.如权利要求15所述的形成半导体封装组件的方法，其特征在于，形成该第二半导体封装的步骤包括：
在第二载体基底上形成通孔结构；
将该第二半导体晶粒接合至该第二载体基底上；
在该第二载体基底上形成第二成型模料，其中，该第二成型模料围绕该通孔结构和该第二半导体晶粒的侧壁，其中该第二成型模料露出该通孔结构的顶面以及该第二半导体晶粒的顶面；以及
在该第二半导体晶粒和该第二成型模料上形成该第二重分布层结构。
19.如权利要求18所述的形成半导体封装组件的方法，其特征在于，进一步包括：在将该第二半导体封装接合至该第一半导体封装之后，移除该第二载体基底。
20.如权利要求19所述的形成半导体封装组件的方法，其特征在于，进一步包括：在移除该第二载体基底之后，在该第二半导体封装之上形成导电组件。
21.如权利要求15所述的形成半导体封装组件的方法，其特征在于，形成该第一半导体封装的步骤包括：
将该第一半导体晶粒接合至第一载体基底之上；
在该第一载体基底上形成第一成型模料，其中，该第一成型模料围绕该第一半导体晶粒的侧壁并且露出该第一半导体晶粒的顶面；以及
在该第一半导体晶粒和该第一成型模料上形成该第一重分布层结构。
22.如权利要求21所述的形成半导体封装组件的方法，其特征在于，进一步包括：
在将该第二半导体封装接合至该第一半导体封装之后，移除该第一载体基底；以及
对该第一半导体封装和该第二半导体封装执行切割工艺。
23.如权利要求21所述的形成半导体封装组件的方法，其特征在于，该第一半导体封装的形成包括：将多于一颗的该半导体晶粒接合至该第一载体基底；其中该第一成型模料进一步围绕该第一半导体晶粒的侧壁，并且露出该第一半导体晶粒的顶面。
24.一种形成半导体封装组件的方法，其特征在于，包括：
形成第一半导体封装，其中该第一半导体封装包括：第一半导体晶粒和第一重分布层结构，该第一重分布层结构耦接至该第一半导体晶粒并且包括：第一导电线路；
形成第二封装，其中该第二封装包括：无源设备和第二重分布层结构，该第二重分布层结构耦接至该无源设备并且包括：第二导电线路；以及
将该第二封装接合至该第一半导体封装，其中，该第一导电线路直接接触该第二导电线路。
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