CN109979891B - 晶片级芯片尺寸封装结构 - Google Patents

晶片级芯片尺寸封装结构 Download PDF

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CN109979891B
CN109979891B CN201810478854.9A CN201810478854A CN109979891B CN 109979891 B CN109979891 B CN 109979891B CN 201810478854 A CN201810478854 A CN 201810478854A CN 109979891 B CN109979891 B CN 109979891B
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chip
redistribution layer
conductive
layer
wafer level
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CN109979891A (zh
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林育民
张道智
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Industrial Technology Research Institute ITRI
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Abstract

本发明公开一种晶片级芯片尺寸封装结构，包括：影像感测芯片以及芯片。影像感测芯片包括第一重分布层，其中第一重分布层包含导线与导电衬垫，导电衬垫形成于导线上，且导电衬垫露出于第一重分布层的表面。芯片包括第二重分布层，其中第二重分布层包含导线与导电衬垫，导电衬垫形成于导线上，且导电衬垫露出于第二重分布层的表面。芯片的面积小于影像感测芯片的面积，且芯片通过第二重分布层与影像感测芯片的第一重分布层接合。

Description

晶片级芯片尺寸封装结构
技术领域
本发明涉及一种晶片级芯片尺寸封装(WLCSP)结构。
背景技术
传统影像感测模块的封装制作工艺是以打线封装、或是芯片尺寸封装(CSP)为主。对于整体影像感测模块系统来说，尚需借助存储器芯片与控制芯片来进行数据的存取与控制，因此，影像感测器、存储器芯片与控制芯片通常会组装、整合至系统板上，而存储器芯片、控制芯片与影像感测器间的沟通即通过此系统板来进行。
近来，由于影像感测器制作工艺的革新与像素的大幅提升，增加了巨量数据存取与控制的需求。对于传统的系统整合方式，实已不足以应对市场趋势。因此，有业者开发出将影像感测器/存储器芯片/逻辑芯片等不同种类的晶片以晶片对晶片(wafer to wafer)的方式加以整合的组装技术，将三种元件集成于一，可大幅提升电传输与元件反应的速率。然而，此种技术仍有其瓶颈，要做到晶片对晶片接合的组装技术，就目前而言，仅能适用于小型感测器。原因是虽存储器芯片/逻辑芯片的芯片间距可以尽可能配合影像感测器的间距而做调整，然而，当感测器面积持续增大时，存储器芯片/逻辑芯片的芯片间距势必随之扩大，此时，单位晶片面积中的存储器芯片/逻辑芯片的数量就会减少，结果将使得整体晶片的成本大幅上升。
因此，开发一种低成本、高电传输速率、且适用于中、大型感测器制作的芯片尺寸封装(CSP)结构是众所期待的。
发明内容
根据本发明的一实施例，提供一种晶片级芯片尺寸封装结构，包括：影像感测芯片，包括第一重分布层，其中该第一重分布层包含导线与导电衬垫，该导电衬垫形成于该导线上，且该导电衬垫露出于该第一重分布层的表面；以及芯片，包括第二重分布层，其中该第二重分布层包含导线与导电衬垫，该导电衬垫形成于该导线上，且该导电衬垫露出于该第二重分布层的表面，其中该芯片的面积小于该影像感测芯片的面积，且该芯片通过该第二重分布层与该影像感测芯片的该第一重分布层接合。
根据本发明的一实施例，提供一种晶片级芯片尺寸封装结构，包括：第一芯片，包括第一重分布层，其中该第一重分布层包含导线与导电衬垫，该导电衬垫形成于该导线上，且该导电衬垫露出于该第一重分布层的表面；以及第二芯片，包括第二重分布层，其中该第二重分布层包含导线与导电衬垫，该导电衬垫形成于该导线上，且该导电衬垫露出于该第二重分布层的表面，其中该第二芯片的面积小于该第一芯片的面积，且该第二芯片通过该第二重分布层与该第一芯片的该第一重分布层接合。
为让本发明能更明显易懂，下文特举一优选实施例，并配合所附的附图，作详细说明如下。
附图说明
图1为本发明的一实施例，一种晶片级芯片尺寸封装结构的剖面示意图；
图2为本发明的一实施例，一种晶片级芯片尺寸封装结构中晶片与芯片接合状态的剖面放大示意图；
图3为本发明的一实施例，一种晶片级芯片尺寸封装结构中晶片与芯片接合状态的剖面放大示意图；
图4为本发明的一实施例，一种晶片级芯片尺寸封装结构的剖面示意图；
图5为本发明的一实施例，一种晶片级芯片尺寸封装结构的剖面示意图；
图6为本发明的一实施例，一种晶片级芯片尺寸封装结构的剖面示意图；
图7为本发明的一实施例，一种晶片级芯片尺寸封装结构的剖面示意图；
图8为本发明的一实施例，一种晶片级芯片尺寸封装结构结合镜头模块的剖面示意图。
符号说明
10 晶片级芯片尺寸封装(WLCSP)结构；
12 影像感测芯片；
14 芯片；
16 第一重分布层；
18 第二重分布层；
20 第一重分布层的导线；
22 第一重分布层的表面；
24 第二重分布层的导线；
26 第二重分布层的表面；
28 第一重分布层的导电衬垫；
30 第二重分布层的导电衬垫；
38 第一金属层；
39 第二金属层；
40 微透镜；
42 透光盖层；
44 粘着层；
46 绝缘保护层；
48 内连线；
50 金属衬垫；
52 导电球；
54 凸块结构；
56 封闭空间；
58 模封材料层；
60 金属导电柱；
62 保护层；
64 第一铜凸块；
66 第二铜凸块；
68 焊锡球；
70 底胶；
100 镜头模块；
102 基板；
104 有(无)源元件；
106 镜片；
108 致动器；
110 镜头基座；
A1 影像感测芯片的面积；
A2 芯片的面积；
H1 金属导电柱的高度；
T1 芯片的厚度。
具体实施方式
请参阅图1，根据本发明的一实施例，揭示一种晶片级芯片尺寸封装(wafer levelchip scale package，WLCSP)结构10。图1为晶片级芯片尺寸封装(WLCSP)结构10的剖面示意图。
在本实施例中，晶片级芯片尺寸封装(WLCSP)结构10包括影像感测芯片12以及芯片14。影像感测芯片12包括第一重分布层16。芯片14包括第二重分布层18。芯片14的面积A2小于影像感测芯片12的面积A1。有关第一重分布层16与第二重分布层18的内部结构，以及影像感测芯片12与芯片14间的接合状态(如图中的虚线框处)将详述于后。
在部分实施例中，影像感测芯片12也可由其他感测芯片替代，例如声波感测芯片、温度感测芯片、湿度感测芯片、气体感测芯片、压力感测芯片、电感测芯片、磁感测芯片、图像感测芯片、位移感测芯片、或光感测芯片。
在部分实施例中，芯片14可为存储器芯片、逻辑芯片、或其他功能性芯片。
本发明的封装结构10可应用于车用电子领域、手持式电子装置、机器人视觉辨识或高分辨率高速录像机等巨量信号或高速信号传输的应用，但本发明不限于此。
请参阅图2(图2为图1中虚线框处的放大示意图)，根据本发明的一实施例，揭示第一重分布层16与第二重分布层18的内部结构，以及影像感测芯片12与芯片14间的一种接合状态。如图2所示，第一重分布层16包含导线20、导电衬垫28以及覆盖导线20的保护层，导电衬垫28形成于导线20上，且导电衬垫28露出于第一重分布层16的表面22。第二重分布层18包含导线24、导电衬垫30以及覆盖导线24的保护层，导电衬垫30形成于导线24上，且导电衬垫30露出于第二重分布层18的表面26。在部分实施例中，导线(20、24)与导电衬垫(28、30)可包括铜。芯片14通过其露出于第二重分布层18的导电衬垫30与影像感测芯片12露出于第一重分布层16的导电衬垫28接合，形成铜-铜接合(铜与铜直接接合)。
在部分实施例中，第一重分布层16的表面22的粗糙度(Ra)大约小于1纳米(nm)。在部分实施例中，第二重分布层18的表面26的粗糙度(Ra)大约小于1纳米(nm)。
请参阅图3(图3为图1中虚线框处的放大示意图)，根据本发明的一实施例，揭示影像感测芯片12与芯片14间的一种接合状态。如图3所示，在第二重分布层18的导电衬垫30与第一重分布层16的导电衬垫28之间，还包括形成有第一金属层38。在部分实施例中，第一金属层38可包括金、锡、钴、锰、钛、钯、镍或银与其合金。但是，本发明并不局限于此，可以包括第一金属层38和第二金属层39，其中，第一金属层38形成在该第一重分布层16的导电衬垫28上，而第二金属层39形成在第二重分布层18的导电衬垫30上。
仍请参阅图1，在本实施例中，在影像感测芯片12上，还包括形成有多个微透镜40，其相对于第一重分布层16设置。在本实施例中，在微透镜40上，还包括形成有透光盖层42。在部分实施例中，透光盖层42可包括玻璃或其他适当材料，以保护下层元件及有效促进信号的穿透或增益。在本实施例中，在影像感测芯片12与透光盖层42之间，还包括形成有粘着层44，覆盖微透镜40。在部分实施例中，粘着层44可包括任何适当的有机粘着材料。
在部分实施例中，在影像感测芯片12与透光盖层42之间，还包括形成有封闭空间56，容纳微透镜40，如图4所示。
仍请参阅图1，在本实施例中，在影像感测芯片12上，还包括形成有绝缘保护层46，覆盖芯片14。在部分实施例中，绝缘保护层46可包括任何适当的模封绝缘材料。
在本实施例中，在影像感测芯片12中，还包括形成有内连线48，以电连接影像感测芯片12中的各元件(未图示)与第一重分布层16。在本实施例中，在第一重分布层16上，还包括形成有多个金属衬垫50，露出于绝缘保护层46。在部分实施例中，金属衬垫50可包括铝、铜、镍、铝铜合金、或铝硅铜合金。在本实施例中，还包括形成有多个导电球52，连接金属衬垫50。在部分实施例中，本发明封装结构10可进一步通过导电球52与基板(未图示)接合。在部分实施例中，上述与封装结构10接合的基板可包括硅基板、陶瓷基板、玻璃纤维基板、印刷电路板、或其他符合制作工艺需求的系统板。
在本实施例中，在影像感测芯片12上，还包括形成有多个凸块结构54，透过胶材或者金属接点组装于芯片14周围，其中凸块结构54可进一步抑制封装结构10的翘曲现象。在一实施例，凸块结构54可替换为功能性芯片，位于芯片14的周围(例如：单侧或双侧或周围)，以可整合不同功能芯片于封装结构10中并可进一步抑制封装结构10的翘曲现象。在部分实施例中，功能性芯片可为存储器芯片或逻辑芯片，但本发明不限于此。
本发明一实施例通过芯片堆叠于晶片上(chip on wafer)的组装技术，利用铜-铜直接接合的方式(即，无焊锡球接合(solderless interconnection))，将功能性芯片(例如存储器芯片或逻辑芯片)直接接合至感测芯片。此种芯片接合方式可使功能性芯片在搭配及选用上，更具灵活性，有效降低并控制整体的制作成本，相当适用于中、大型感测器的制作。此外，功能性芯片与感测芯片之间的电传输速度也因铜-铜直接接合路径缩短而大幅提升。
请参阅图5，根据本发明的一实施例，揭示一种晶片级芯片尺寸封装(wafer levelchip scale package，WLCSP)结构10。图5为晶片级芯片尺寸封装(WLCSP)结构10的剖面示意图。
在本实施例中，晶片级芯片尺寸封装(WLCSP)结构10包括影像感测芯片12以及芯片14。影像感测芯片12包括第一重分布层16。芯片14包括第二重分布层18。芯片14的面积A2小于影像感测芯片12的面积A1。
在部分实施例中，影像感测芯片12也可由其他感测芯片替代，例如声波感测芯片、温度感测芯片、湿度感测芯片、气体感测芯片、压力感测芯片、电感测芯片、磁感测芯片、图像感测芯片、位移感测芯片、或光感测芯片。
在部分实施例中，芯片14可为存储器芯片、逻辑芯片、或其他功能性芯片。
有关第一重分布层16与第二重分布层18的内部结构，以及影像感测芯片12与芯片14间的接合状态，请参阅图2、图3。
在本实施例中，在影像感测芯片12上，还包括形成有多个微透镜40，相对于第一重分布层16设置。在本实施例中，在微透镜40上，还包括形成有透光盖层42。在部分实施例中，透光盖层42可包括玻璃或其他适当材料，以保护下层元件及有效促进信号的穿透或增益。在本实施例中，在影像感测芯片12与透光盖层42之间，还包括形成有粘着层44，覆盖微透镜40。在部分实施例中，粘着层44可包括任何适当的有机粘着材料。
在部分实施例中，在影像感测芯片12与透光盖层42之间，还包括形成有封闭空间56，容纳微透镜40，如图6所示。
仍请参阅图5，在本实施例中，在影像感测芯片12上，还包括形成有模封材料层58，覆盖芯片14。在部分实施例中，模封材料层58可包括任何适当的绝缘材料。
在本实施例中，在影像感测芯片12中，还包括形成有内连线48，以电连接影像感测芯片12中的各元件(未图示)与第一重分布层16。在本实施例中，在第一重分布层16上，还包括形成有多个金属导电柱60，贯穿并露出于模封材料层58。在部分实施例中，金属导电柱60可包括铜或其他适当金属。在部分实施例中，金属导电柱60的高度H1大于芯片14的厚度T1。在部分实施例中，在模封材料层58上，还包括形成有保护层62，露出金属导电柱60。在部分实施例中，保护层62可包括任何适当的绝缘材料。在本实施例中，还包括形成有多个导电球52，连接金属导电柱60。在部分实施例中，本发明封装结构10可进一步通过导电球52与基板(未图示)接合。在部分实施例中，上述与封装结构10接合的基板可包括硅基板、陶瓷基板、玻璃纤维基板、印刷电路板、或其他符合制作工艺需求的系统板。
请参阅图7，根据本发明的一实施例，揭示一种晶片级芯片尺寸封装(wafer levelchip scale package，WLCSP)结构10。图7为晶片级芯片尺寸封装(WLCSP)结构10的剖面示意图。
在本实施例中，晶片级芯片尺寸封装(WLCSP)结构10包括影像感测芯片12以及芯片14。影像感测芯片12包括第一重分布层16。芯片14包括第二重分布层18。芯片14的面积A2小于影像感测芯片12的面积A1。
在部分实施例中，影像感测芯片12也可由其他感测芯片替代，例如声波感测芯片、温度感测芯片、湿度感测芯片、气体感测芯片、压力感测芯片、电感测芯片、磁感测芯片、图像感测芯片、位移感测芯片、生物信号感测芯片、或光感测芯片。
在部分实施例中，芯片14可为存储器芯片、逻辑芯片、或其他功能性芯片。
以下详述影像感测芯片12与芯片14间的接合状态。
如图7所示，在影像感测芯片12的第一重分布层16上，还包括形成有多个第一铜凸块64。在芯片14的第二重分布层18上，还包括形成有多个第二铜凸块66，而在第一铜凸块64与第二铜凸块66之间，还包括形成有多个焊锡球68。芯片14通过第二铜凸块66、焊锡球68、以及第一铜凸块64与影像感测芯片12接合，形成铜-焊锡球-铜的接合状态。
在本实施例中，在影像感测芯片12上，还包括形成有多个微透镜40，相对于第一重分布层16设置。在本实施例中，在微透镜40上，还包括形成有透光盖层42。在部分实施例中，透光盖层42可包括玻璃或其他适当材料，以保护下层元件及有效促进信号的穿透或增益。在本实施例中，在影像感测芯片12与透光盖层42之间，还包括形成有粘着层44，覆盖微透镜40。在部分实施例中，粘着层44可包括任何适当的有机粘着材料。
在部分实施例中，在影像感测芯片12与透光盖层42之间，还包括形成有封闭空间(未图示)，容纳微透镜40。
在本实施例中，在影像感测芯片12上，还包括形成有绝缘保护层46。在部分实施例中，绝缘保护层46可包括任何适当的介电绝缘材料。在本实施例中，在绝缘保护层46与芯片14之间的部分区域，还包括填入底胶70。
在本实施例中，在影像感测芯片12中，还包括形成有内连线48，以电连接影像感测芯片12中的各元件(未图示)与第一重分布层16。在本实施例中，在第一重分布层16上，还包括形成有多个金属衬垫50，露出于绝缘保护层46。在部分实施例中，金属衬垫50可包括铝、铝铜合金、或铝硅铜合金。在本实施例中，还包括形成有多个导电球52，连接金属衬垫50。在部分实施例中，本发明封装结构10可进一步通过导电球52与基板(未图示)接合。在部分实施例中，上述与封装结构10接合的基板可包括硅基板、陶瓷基板、玻璃纤维基板、印刷电路板、或其他符合制作工艺需求的系统板。
请参阅图8，根据本发明的一实施例，揭示一种晶片级芯片尺寸封装(WLCSP)结构10结合镜头模块100的结构。图8为晶片级芯片尺寸封装(WLCSP)结构10结合镜头模块100的剖面示意图。
如图8所示，将晶片级芯片尺寸封装(WLCSP)结构10接合于基板102上。而镜头模块100也同时接合于基板102上。
在部分实施例中，与基板102接合的晶片级芯片尺寸封装(WLCSP)结构10可包括如图1、图4、图5、图6、图7所示的封装结构。
在部分实施例中，基板102可包括硅基板、陶瓷基板、玻璃纤维基板、印刷电路板、或其他符合制作工艺需求的系统板。在本实施例中，在基板102上，还包括形成有多个有(无)源元件104。镜头模块100包括镜片106、致动器108、以及镜头基座110。
本发明一实施例的晶片级芯片尺寸封装(WLCSP)结构与镜头模块同时嵌于基板上，使得晶片级芯片尺寸封装(WLCSP)结构中的影像感测芯片与镜片形成良好的共平面性，有效解决了影像感测芯片与镜片之间可能产生的歪斜现象。且晶片级芯片尺寸封装(WLCSP)结构中，影像感测芯片与其他功能性芯片(例如存储器芯片或逻辑芯片)之间的信号传输路径，也因两芯片通过铜-铜对接的连接方式而缩短，大幅提升运算速度。
虽然结合以上数个优选实施例公开了本发明，然而其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，可作任意的更动与润饰，因此本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (15)

1.一种晶片级芯片尺寸封装结构，其特征在于，包括：
影像感测芯片，包括第一重分布层，其中该第一重分布层包含导线与导电衬垫，该导电衬垫形成于该导线上，且该导电衬垫露出于该第一重分布层的表面；
芯片，包括第二重分布层，其中该第二重分布层包含导线与导电衬垫，该导电衬垫形成于该导线上，且该导电衬垫露出于该第二重分布层的表面，其中该芯片的面积小于该影像感测芯片的面积，且该芯片通过该第二重分布层与该影像感测芯片的该第一重分布层接合；
模封材料层，形成于该影像感测芯片上，并覆盖该芯片；
多个金属导电柱，形成于该第一重分布层上，贯穿并露出于该模封材料层；以及
多个凸块结构，位于该影像感测芯片上，位于该芯片的周围。
2.如权利要求1所述的晶片级芯片尺寸封装结构，其中该导线与该导电衬垫包括铜。
3.如权利要求1所述的晶片级芯片尺寸封装结构，其中该芯片通过其露出于该第二重分布层的该导电衬垫与该影像感测芯片露出于该第一重分布层的该导电衬垫接合。
4.如权利要求3所述的晶片级芯片尺寸封装结构，还包括第一金属层，形成于该第二重分布层的该导电衬垫与该第一重分布层的该导电衬垫之间。
5.如权利要求3所述的晶片级芯片尺寸封装结构，还包括第一金属层和第二金属层，其中第一金属层形成于该第一重分布层的该导电衬垫上,第二金属层形成于该第二重分布层的该导电衬垫上。
6.如权利要求1所述的晶片级芯片尺寸封装结构，还包括多个微透镜，形成于该影像感测芯片上，相对于该第一重分布层设置。
7.如权利要求6所述的晶片级芯片尺寸封装结构，还包括透光盖层，形成于该多个微透镜上。
8.如权利要求7所述的晶片级芯片尺寸封装结构，还包括粘着层，形成于该影像感测芯片与该透光盖层之间，并覆盖该多个微透镜。
9.如权利要求7所述的晶片级芯片尺寸封装结构，还包括封闭空间，形成于该影像感测芯片与该透光盖层之间，并容纳该多个微透镜。
10.如权利要求1所述的晶片级芯片尺寸封装结构，还包括多个金属衬垫，形成于该第一重分布层上，并露出于绝缘保护层。
11.如权利要求10所述的晶片级芯片尺寸封装结构，还包括多个导电球，连接该多个金属衬垫。
12.如权利要求1所述的晶片级芯片尺寸封装结构，还包括多个导电球，连接该多个金属导电柱。
13.如权利要求1所述的晶片级芯片尺寸封装结构，其中该凸块结构为功能性芯片。
14.一种晶片级芯片尺寸封装结构，其特征在于，包括：
第一芯片，包括第一重分布层，其中该第一重分布层包含导线与导电衬垫，该导电衬垫形成于该导线上，且该导电衬垫露出于该第一重分布层的表面；
第二芯片，包括第二重分布层，其中该第二重分布层包含导线与导电衬垫，该导电衬垫形成于该导线上，且该导电衬垫露出于该第二重分布层的表面，其中该第二芯片的面积小于该第一芯片的面积，且该第二芯片通过该第二重分布层与该第一芯片的该第一重分布层接合；
模封材料层，形成于该第一芯片上，并覆盖该第二芯片；
多个金属导电柱，形成于该第一重分布层上，贯穿并露出于该模封材料层；以及
多个凸块结构，位于该第一芯片上，位于该第二芯片的周围。
15.如权利要求14所述的晶片级芯片尺寸封装结构，其中该凸块结构为功能性芯片。
CN201810478854.9A 2017-12-28 2018-05-18 晶片级芯片尺寸封装结构 Active CN109979891B (zh)

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