CN107533985A - 包括第一级裸片、背对背堆叠的第二级裸片和第三级裸片以及对应的第一再分配层、第二再分配层和第三再分配层的竖直堆叠系统级封装及其制造方法 - Google Patents

包括第一级裸片、背对背堆叠的第二级裸片和第三级裸片以及对应的第一再分配层、第二再分配层和第三再分配层的竖直堆叠系统级封装及其制造方法 Download PDF

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CN107533985A
CN107533985A CN201680023338.6A CN201680023338A CN107533985A CN 107533985 A CN107533985 A CN 107533985A CN 201680023338 A CN201680023338 A CN 201680023338A CN 107533985 A CN107533985 A CN 107533985A
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nude film
rdl
order
encapsulated
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CN107533985B (zh
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翟军
胡坤忠
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Apple Inc
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Apple Computer Inc
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Abstract

本发明描述了一种竖直堆叠的系统级封装结构。一种封装包括第一级(125)模制(122)和扇出结构(130)、第三级(185)模制(182)和扇出结构(190)以及在所述第一级(125)和第三级(185)之间的第二级(155)模制(152)和扇出结构(160)。所述第一级(125)模制(122)和扇出结构(130)包括第一级裸片(110)，所述第二级(155)模制(152)和扇出结构(160)包括背对背面向的裸片(142)，其中每个裸片(142)的正表面粘结到再分配层(130,160)，并且所述第三级(185)模制(182)包括第三级裸片(172)。可使用多个第一级模制裸片(110)。所述第一级裸片(110)可为易失性存储器裸片，所述第二级裸片(142)可为非易失性存储器裸片，并且所述第三级裸片(172)可为活动裸片。在形成所述竖直堆叠系统级封装的方法中，可使用承载衬底，随后除去。

Description

包括第一级裸片、背对背堆叠的第二级裸片和第三级裸片以 及对应的第一再分配层、第二再分配层和第三再分配层的竖 直堆叠系统级封装及其制造方法
相关专利申请
本申请要求于2015年4月23日提交的美国临时专利申请序列号62/151,843的优先权权益，该临时专利申请公开内容全文以引用方式并入本文。
技术领域
本文所述的实施方案涉及半导体封装。更具体地，实施方案涉及竖直堆叠的系统级封装(SiP)结构以及制造方法。
背景技术
对便携式和移动电子设备诸如移动电话、个人数字助理(PDA)、数字相机、便携式播放器、游戏设备、和其他移动设备的当前市场需求要求将更多性能和特征集成到越来越小的空间中。结果，各种多裸片封装解决方案诸如系统级封装(SiP)和堆叠封装(PoP)变得更加普及，以满足对较高裸片/部件密度设备的需求。
存在用于将多个裸片布置在SiP中的许多不同的可能。例如，将裸片竖直集成在SiP结构中已演进到2.5D解决方案和3D解决方案。在2.5D解决方案中，多个裸片可在包括通孔以及扇出布线的内插器上粘结倒装芯片。在3D解决方案中，多个裸片可堆叠在SiP衬底上的彼此的顶部，并且与芯片外引线键合或焊料凸块连接在一起。
在一种实施方式中，存储器裸片或封装(例如，动态随机存取存储器(DRAM))堆叠在逻辑裸片或封装(例如，专用集成电路(ASIC)或片上系统(SoC))的顶部上。随着便携式和移动电子设备市场不断进步，存储器裸片或封装需要具有较大的存储能力。
发明内容
在实施方案中，竖直堆叠SiP包括：包封在第一级模制化合物中的第一级裸片；所包封的第一级裸片上的第一再分配层(RDL)；在第一RDL上包括一对背对背叠堆裸片并包封在第二级模制化合物中的第二级裸片叠堆；位于所包封的第二级裸片叠堆上的第二RDL；在第二RDL上并包封在第三级模制化合物中的第三级裸片，其中第三级裸片背面朝向第二RDL；以及位于所包封的第三级裸片上的第三RDL。
根据实施方案，在SiP内实现了裸片的特定取向，这可能是特定封装方法导致的。在实施方案中，第三RDL直接位于第三级裸片的导电凸块诸如柱形凸块上。在实施方案中，第三RDL直接位于第三级裸片的接触垫上。可利用裸片附接膜将第三级裸片附接到第二RDL。第一级裸片可正面朝向第一RDL，其中第一RDL直接位于第一级裸片的导电凸块上。根据实施方案，该对背对背堆叠裸片可包括：粘结到第一RDL的第一-第二级裸片，以及第二-第二级裸片，其中第二RDL位于第二-第二级裸片上。例如，可利用焊料将第一-第二级裸片粘结到第一RDL，并且第二RDL可直接位于第二-第二级裸片的导电凸块(例如柱形凸块)上。
各级封装可另外包括导电柱。例如，多个第二级导电柱可从第一RDL延伸至第二RDL，并利用第二级模制化合物包封。类似地，多个第三级导电柱可从第二RDL延伸至第三RDL，并利用第三级模制化合物包封。在实施方案中，多个导电凸块形成在第三级裸片上第三RDL的相反侧上。在实施方案中，多个第一级导电柱延伸穿过第一级模制化合物，并且第二封装位于第一级模制化合物上并且与多个第一级导电柱电连接和/或由多个第一级导电柱机械支撑。
在实施方案中，竖直堆叠SiP包括：包封在第一级模制化合物中的第一级易失性存储器裸片；位于所包封的第一级易失性存储器裸片上的第一RDL；在第一RDL上包括一对背对背堆叠的非易失性存储器裸片并包封在第二级模制化合物中的第二级非易失性存储器裸片叠堆；位于所包封的第二级非易失性存储器裸片叠堆上的第二RDL；位于第二RDL上并包封在第三级模制化合物中的第三级活动裸片；以及位于所包封的第三级活动裸片上的第三RDL。竖直堆叠SiP可包括包封在第一级模制化合物中的多个第一级易失性存储器裸片，其中第一RDL位于多个所包封的第一级易失性存储器裸片上。在实施方案中，第一级易失性存储器裸片为DRAM裸片，背对背堆叠的非易失性存储器裸片为NAND裸片，并且第三级活动裸片为SoC裸片。
在实施方案中，形成竖直堆叠SiP的方法包括利用第一级模制化合物将第一级裸片包封在承载衬底上；在第一级模制化合物上形成第一RDL，利用第二级模制化合物将第二级裸片叠堆包封在第一RDL上；在第二级模制化合物上形成第二RDL；利用第三级模制化合物将第三级裸片包封在第二RDL上；以及在第三级模制化合物上形成第三RDL。例如，第一RDL可直接形成在第一级裸片上。利用裸片附接膜将第一-第二级裸片粘结到第一RDL，并将第二-第二级裸片附接到第一-第二级裸片。
这种制造方法可另外包括导电柱的集成。在实施方案中，利用第二级模制化合物包封多个第二级导电柱，并且第二RDL直接形成在第二级裸片叠堆中的第二-第二级裸片和多个第二级导电柱上。在实施方案中，利用第三级模制化合物包封多个第三级导电柱，并且第三RDL直接形成在第三级裸片和多个第三级导电柱上。
附图说明
图1是根据实施方案的安装在承载衬底上的多个裸片的横截面侧视图图示。
图2是根据实施方案的包封在第一级模制化合物中的多个裸片的横截面侧视图图示。
图3是根据实施方案的形成在第一级模制化合物上的第一RDL的横截面侧视图图示。
图4是根据实施方案的形成在第一RDL上的导电柱的横截面侧视图图示。
图5A是根据实施方案的安装在第一RDL上的裸片的横截面侧视图图示。
图5B是根据实施方案的利用聚合物限定梯台垫粘结到第一RDL的裸片的近距离横截面侧视图图示。
图5C是根据实施方案的利用UBM限定梯台垫粘结到第一RDL的裸片的近距离横截面侧视图图示。
图6是根据实施方案的安装在第一RDL上的裸片叠堆的横截面侧视图图示。
图7是第一级模制和扇出结构上第二级模制和扇出结构的横截面侧视图图示。
图8是根据实施方案的安装在第二RDL上的裸片和形成在第二RDL上的导电柱的横截面侧视图图示。
图9A是第二级模制和扇出结构上第三级模制和扇出结构的横截面侧视图图示。
图9B是根据实施方案的在分割单个封装之前三层堆叠结构的横截面侧视图图示。
图10是根据实施方案的竖直堆叠SiP结构的横截面侧视图图示。
图11是根据实施方案的PoP结构的横截面侧视图图示。
图12是示出形成根据实施方案的竖直堆叠SiP结构的方法的处理流程。
具体实施方式
实施方案描述了竖直堆叠SiP结构。在各种实施方案中，参照附图来进行描述。然而，某些实施方案可在不存在这些具体细节中的一个或多个具体细节或者不与其他已知的方法和构型相结合的情况下被实施。在以下的描述中，示出许多具体细节诸如特定构型、尺寸工艺等，以提供对实施方案的透彻理解。在其他情况下，未对熟知的半导体工艺和制造技术进行特别详细地描述，以免不必要地模糊实施方案。整个说明书中所提到的“一个实施方案”是指结合实施方案所描述的特定特征、结构、构型或特性被包括在至少一个实施方案中。因此，整个说明书中多处出现短语“在一个实施方案中”不一定是指相同的实施方案。此外，特定特征、结构、构型或特性可以任何适当的方式组合在一个或多个实施方案中。
本文所使用的术语“正”、“背”、“至”、“在...之间”和“在...上”可指一层相对于其它层的相对位置。一层在另一层“上”或者粘结“至”另一层或者与另一层“接触”可为直接与其它层接触或可具有一个或多个居间层。一层在多层“之间”可为直接与该多层接触或可具有一个或多个居间层。
在一个方面，实施方案描述了竖直堆叠SiP。在实施方案中，竖直堆叠SiP包括：包封在第一级模制化合物中的第一级裸片；位于所包封的第一级裸片上的第一再分配层(RDL)；在第一RDL上包括一对背对背堆叠的裸片并包封在第二级模制化合物中的第二级裸片叠堆；位于所包封的第二级裸片叠堆上的第二RDL；位于第二RDL上并包封在第三级模制化合物中的第三级裸片；以及位于所包封的第三级裸片上的第三RDL。多个第二级导电柱可将第一RDL电连接至第二RDL，并且多个第三级导电柱可将第二RDL与第三RDL电连接。根据实施方案，导电柱(例如第一级、第二级、第三级等中的任一者)可提供机械支撑。例如，除部件之间的电连接之外，或者在不提供电连接的情况下，可提供机械支撑。在一些实施方案中，某一级封装内导电柱的一部分用于提供电连接和机械支撑，而该级封装内导电柱的另一部分在不提供电连接的情况下提供机械支撑。
在一个方面，实施方案描述了集成了多种类型存储器裸片与逻辑裸片(例如ASIC或SoC)的竖直堆叠SiP。在实施方案中，竖直堆叠SiP包括针对易失性存储器(例如DRAM、SRAM、虚拟SRAM、浮体等)、非易失性存储器(例如NAND、NOR、EPROM、EEPROM、MRAM、FRAM、PCM等)和逻辑裸片的独立模制级别。在实施方案中，竖直堆叠SiP包括具有一个或多个易失性存储器裸片(例如DRAM)的第一级模制、包括背对背堆叠的非易失性存储器裸片(例如NAND)的第二级模制以及包括逻辑裸片(例如ASIC或SoC)的第三级模制。
在一个方面，实施方案描述了竖直堆叠SiP，该竖直堆叠SiP可减少电路板上基板面(例如x-y尺寸)的数量。已经观察到，相比于某些易失性存储器裸片(例如DRAM)，某些非易失性存储器裸片(例如NAND)可具有较大的x-y器件封装尺寸。例如，这可能是由于移动设备中的存储容量增大导致的。根据实施方案，相比于易失性存储器裸片(例如用于高速缓存)，用于存储的非易失性存储器裸片可具有较大的x-y尺寸。根据实施方案，竖直堆叠SiP结构可包括并列布置的多个第一级裸片。根据实施方案，竖直堆叠SiP结构可包括在竖直堆叠SiP内背对背堆叠的具有大x-y尺寸(相对于SiP中的其它裸片)的多个第二级裸片。另外，背对背堆叠裸片的扇出可采用背对背堆叠裸片的相反侧上的再分配层(RDL)完成。这样，可通过使用RDL的扇出来减弱对总封装高度(高度z)的影响，其可以显著小于用于传统内插器和引线粘结的厚度来构造。
现参见图1，提供了多个第一级裸片110安装在承载衬底102，诸如玻璃面板、硅晶片、金属面板等上的横截面侧视图图示。承载衬底102可包括用于安装多个第一级裸片110的粘合剂(例如聚合物)层或胶带层104。在实施方案中，利用膜112，诸如裸片附接膜或环氧树脂粘结材料来将第一级裸片110安装到承载衬底上。在实施方案中，第一级裸片110为存储器裸片。在实施方案中，第一级裸片110为易失性存储器裸片，诸如DRAM、SRAM、虚拟SRAM、浮体等。在具体实施方案中，第一级裸片110为DRAM裸片。
在图1例示的实施方案中，第一级裸片110正面朝上被安装到承载衬底102上，使得包括凸块114(例如柱形凸块)的活动侧正面朝上。例如，柱形凸块114可为铜柱形凸块。凸块114可为任选的，并且相反可为用于第一级裸片110的暴露的接触垫。根据实施方案，第一级导电柱120可任选地形成在承载衬底102上。任选的第一级导电柱120的材料可包括但不限于金属材料，诸如铜、钛、镍、金及其组合或合金。第一级导电柱120可使用合适的处理技术来形成，并且可由各种合适的材料(例如，铜)和层形成。在实施方案中，第一级导电柱120通过镀覆技术来形成，诸如使用图案化光刻胶电镀来限定柱结构尺寸，随后移除该图案化光刻胶层。在实施方案中，任选第一级导电柱120在安装第一级裸片110之前形成。
现在参见图2，多个第一级裸片110和任选第一级导电柱120随后被包封在承载衬底102上的第一级模制化合物122中。例如，第一级模制化合物122可包括热固性交联树脂(例如，环氧树脂)，但是其它材料可如已知那样用于电子封装中。包封可使用合适的技术诸如但不限于传递模制、压缩模制和层压来完成。在利用第一级模制化合物122包封之后，该结构可任选地另外用研磨(例如化学机械抛光)操作、蚀刻操作来处理，或经图案化和蚀刻以暴露第一级裸片110、凸块114以及任选第一级导电柱120。在实施方案中，在研磨或蚀刻操作之后，凸块114的顶表面115、123与第一级模制化合物122(以及第一级导电柱120的任选顶表面121)共面。在实施方案中，凸块114可用第一级裸片110的接触垫替代，其可例如通过蚀刻或激光钻孔第一级模制化合物122而暴露。
现在参见图3，第一再分配层(RDL)130形成在第一级模制化合物122和凸块114(或接触垫)的暴露表面115以及第一级导电柱的任选暴露表面121(当存在时)上。第一RDL 130可包括单个再分配线132或多个再分配线132以及电介质层134。第一RDL 130可通过逐层工艺形成，并且可使用此薄膜技术形成。在实施方案中，第一RDL 130具有小于50μm的总厚度，或更具体地小于30μm，诸如大约20μm。在实施方案中，第一RDL 130包括嵌入式再分配线132(嵌入式迹线)。例如，再分配线132可通过首先形成种子层随后形成金属(例如，铜)图案来创建。另选地，再分配线132可通过沉积(例如，溅射)和蚀刻来形成。再分配线132的材料可包括但不限于金属材料，诸如铜、钛、镍、金及其组合或合金。再分配线132的金属图案随后被嵌入任选地图案化的电介质层134中。电介质层134可为任何合适的材料，诸如氧化物或聚合物(例如，聚酰亚胺)。
在例示的实施方案中，再分配线132直接形成在凸块114(或接触垫)的顶表面115上。更具体地讲，第一RDL 130的再分配线132的接触垫135直接形成在第一级裸片110的凸块114上。第一RDL 130和所模制的第一级裸片110可一起形成第一级模制和扇出135。
在形成第一RDL 130之后，多个第二级导电柱140可形成在第一RDL 130上，如图4所例示。第二级导电柱140可类似地由如上文参照任选第一级导电柱120所述的相同材料形成。
现在参见图5A，一个或多个第二级裸片142被安装在第一RDL 130上。在实施方案中，第二级裸片142为非易失性存储器裸片，诸如(例如NAND、NOR、EPROM、EEPROM、MRAM、FRAM、PCM等)。在具体实施方案中，第二级裸片142为NAND裸片。在实施方案中，相比于任意第一级裸片110，第二级裸片142更宽，x-y面积更大。在图5A所例示的实施方案中，第二级裸片142正面朝向第一RDL 130并利用导电凸块，诸如柱形凸块、焊料凸块或具有焊料尖端的柱形凸块来附接到第一RDL 130的梯台垫或凸点下金属化层(UBM)垫。在实施方案中，第二级裸片142的背面不包括任何导电触点(例如柱形凸块、焊料凸块等)。
梯台垫或UBM垫可以多种方式形成在第一RDL 130中。图5B为粘结到第一RDL的第二级裸片142的近距离图示，其中梯台垫开口已经被电介质层134中的开口限定。在所例示的具体实施方案中，第二级裸片142凸块包括具有焊料尖端146的柱形凸块144。图5C为粘结到第一RDL的第二级裸片142的近距离图示，该第二级裸片包括具有焊料尖端146的柱形凸块144，其中梯台垫被UBM垫136限定。现在重新参见图5A，在将第二级裸片142安装至第一RDL 130之后，可将底层填充材料150任选地施加至第二级裸片142与第一RDL 130之间。
现在参见图6，第二-第二级裸片142附接到第一-第二级裸片142。在例示的具体实施方案中，第二-第二级裸片142的背面以背对背布置附接到第一-第二级裸片142的背面。第二级裸片142可使用例如裸片附接膜(DAF)148附接到彼此。DAF 148可为粘合剂材料，并且可任选地是导热的。DAF可在裸片附接之后通过例如化学、热或紫外光而被任选地固化。
在实施方案中，第一-第二级(例如图6中的顶部)和第二-第二级(例如图6中的底部)裸片142是相同的。例如，每个第二级裸片142可为相同的NAND裸片。在实施方案中，堆叠的第二级裸片142是相同的，一个不同之处在于对柱形凸块的修改。例如，顶部第二级裸片142(如图6中所示)可包括没有焊料尖端的柱形凸块144(或者其中不存在柱形凸块的接触垫)，而底部第二级裸片142(如图6中所示)包括具有焊料尖端146的柱形凸块144，如图5B-5C所示。
现在参见图7，第二级裸片142叠堆和第二级导电柱140被包封在承载衬底102上的第二级模制化合物152中。简要参见图9B，第二级模制化合物152可任选地围绕第一级模制化合物122，但是这不是必需的。第二级模制化合物152可以与第一级模制化合物122类似的方式形成，并由与第一级模制化合物相同的材料形成。在利用第二级模制化合物包封之后，该结构可任选地通过研磨操作、蚀刻操作处理，或经图案化和蚀刻以暴露顶部第二级裸片142、凸块144(或接触垫，如果不存在凸块)以及第二级导电柱140。在实施方案中，在研磨或蚀刻操作之后，凸块144的顶表面145、第二级模制化合物152的顶表面153以及第二级导电柱140的顶表面141共面。
然后第二再分配层(RDL)160形成在第二级模制化合物152、凸块144(或接触垫)的暴露表面145以及第二级导电柱140的暴露表面141上。第二RDL 160可包括单个再分配线162或多个再分配线162以及电介质层164。第二RDL 160可通过逐层工艺形成，并且可使用薄膜技术来形成。在实施方案中，第二RDL 160具有小于50μm的总厚度，或更具体地小于30μm，诸如大约20μm。在实施方案中，第二RDL 160包括嵌入式再分配线162(嵌入式迹线)。例如，再分配线162可通过首先形成种子层随后形成金属(例如，铜)图案来创建。另选地，再分配线162可通过沉积(例如，溅射)和蚀刻来形成。再分配线162的材料可包括但不限于金属材料，诸如铜、钛、镍、金及其组合或合金。再分配线162的金属图案随后被嵌入任选地图案化的电介质层164中。电介质层164可为任何合适的材料，诸如氧化物或聚合物(例如，聚酰亚胺)。
在例示的实施方案中，再分配线162直接形成在凸块144(或不存在凸块的接触垫)的顶表面145上。更具体地讲，第二RDL 160的再分配线162的接触垫165直接形成在顶部第二级裸片142的凸块144上。第二RDL 160和经模制的第二级堆叠裸片142可一起形成第二级模制和扇出155。再分配线162也可直接形成在多个第二级导电柱140的表面141上。
在形成第二RDL 160之后，多个第三级导电柱170可形成在第二RDL 160上，如图8所例示。第三级导电柱可类似地由相同材料形成，如上文参照任选第一级导电柱120所述。
仍参见图8，一个或多个第三级裸片172安装在第二RDL 160上。例如，一个或多个第三级裸片172可在形成第三级导电柱170之后安装。在实施方案中，第三级裸片172为逻辑裸片，诸如ASIC或SoC。在具体实施方案中，第三级裸片172为SoC裸片。如图8所示，第三级裸片172可背向第二RDL 160。在这样的布置中，第三级裸片172可利用与上述DAF 148类似的DAF 178附接到第二RDL 160。第三级裸片172可包括凸块174，诸如柱形凸块(例如铜柱形凸块)。或者，第三级裸片172可包括暴露的接触垫以替代凸块174。
现在参见图9A，第三级裸片172和第三级导电柱170被包封在承载衬底102上的第三级模制化合物182中。简要参见图9B，第三级模制化合物182可任选地围绕第一级模制化合物122和第二级模制化合物152，但是这不是必需的。第三级模制化合物182可以与第一级模制化合物122和第二级模制化合物152类似的方式形成，并由与第一级模制化合物和第二级模制化合物相同的材料形成。在利用第三级模制化合物包封之后，所述结构可任选地通过研磨操作、蚀刻操作处理，或经图案化和蚀刻以暴露第三级裸片172、凸块174(或接触垫)以及第三级导电柱170。在实施方案中，在研磨或蚀刻操作之后，凸块174的顶表面175、第三级模制化合物182的顶表面183以及第三级导电柱170的顶表面171共面。
然后第三再分配层(RDL)190形成在第三级模制化合物182、凸块174(或接触垫)的暴露表面175以及第三级导电柱170的暴露表面171上。第三RDL 190可包括单个再分配线192或多个再分配线192以及电介质层194。第三RDL 190可通过逐层工艺形成，并且可使用薄膜技术来形成。在实施方案中，第三RDL 190具有小于50μm的总厚度，或更具体地小于30μm，诸如大约20μm。在实施方案中，第三RDL 190包括嵌入式再分配线192(嵌入式迹线)。例如，再分配线192可通过首先形成种子层随后形成金属(例如，铜)图案来创建。另选地，再分配线192可通过沉积(例如，溅射)和蚀刻来形成。再分配线192的材料可包括但不限于金属材料，诸如铜、钛、镍、金及其组合或合金。再分配线192的金属图案随后被嵌入任选地图案化的电介质层194中。电介质层194可为任何合适的材料，诸如氧化物或聚合物(例如，聚酰亚胺)。
在例示的实施方案中，再分配线192直接形成在凸块174的顶表面175上。更具体地讲，第三RDL 190的再分配线192的接触垫195直接形成在裸片172的凸块174(或接触垫)上。第三RDL 190和经模制的第三级裸片172可一起形成第三级模制和扇出185。在形成第三RDL190之后，多个导电凸块198(例如焊料凸块或柱形凸块)可形成在第三RDL 190上。
现在参见图9B，提供了根据实施方案的在分割单个封装之前的三层(或三级)堆叠结构的横截面侧视图图示，其中虚线示出了单个封装的分割线。在实施方案中，模制化合物122、152的边缘可带凹口以容纳在包封过程中使用的模制腔。在分割过程中可顺序地修剪带凹口区域。图9B所例示的具体实施方案是示例性的，并且多种模制构造是可能的。不同模制级可使用相同或不同的模制腔。另外，模制腔可具有相同或不同的深度(高度)和面积。在实施方案中，所有模制级别可使用相同的模制腔。
图10是在除去承载衬底和封装分割之后竖直堆叠SiP结构的横截面侧视图图示。在实施方案中，竖直堆叠SiP包括：包封在第一级模制化合物122中的第一级裸片110；位于所包封的第一级裸片110上的第一再分配层(RDL)130；位于第一RDL 130上包括一对背对背堆叠的裸片142并包封在第二级模制化合物152中的第二级裸片叠堆；位于所包封的第二级裸片叠堆上的第二RDL 160；位于第二RDL 160上并包封在第三级模制化合物182中的第三级裸片172；以及位于所包封的第三级裸片172上的第三RDL 190。多个第二级导电柱140可将第一RDL 130电连接至第二RDL 160，并且多个第三级导电柱170可将第二RDL 160与第三RDL 190电连接。如图所示，第三级裸片172背面朝向第二RDL 160(例如在面向第二RDL 160的第三级裸片172的背面上不存在导电触点)。在这样的构造中，在第三级裸片172和第二RDL 160之间不存在直接电连接。例如，可利用裸片附接膜178将第三级裸片172附接到第二RDL。第三RDL 190可直接位于第三级裸片172的导电凸块174(例如柱形凸块)上。在实施方案中，第三级裸片172和第二RDL 160之间的电路径贯穿第三RDL 190和第三级导电柱170至第二RDL 160。
如图所示，第一级裸片110正面朝向第一RDL。第一RDL 130可直接位于第一级裸片110的导电凸块114(例如柱形凸块)上。可存在多个并列的第一级裸片110。与垂直堆叠第一级裸片110截然相反，这样可降低封装的总高度z。在实施方案中，一个或多个第一级裸片110为DRAM裸片。
该对背对背堆叠裸片142可包括：粘结到第一RDL 130的第一-第二级裸片142，以及第二-第二级裸片142，其中第二RDL 160位于第二-第二级裸片142上。如图所示，第一-第二级裸片142可利用焊料粘结到第一RDL 130。第二RDL 160可直接位于第二-第二级裸片142的导电凸块144(例如柱形凸块)上。可利用裸片附接膜148将第二-第二级裸片142附接到第一-第二级裸片142。在实施方案中，该对背对背堆叠裸片142为非易失性存储器裸片，诸如NAND裸片。根据实施方案，由于其相当大的尺寸，NAND裸片背对背堆叠，与并列堆叠相反。因此，可在封装中间内使用背对背堆叠构造来降低总封装尺寸(x-y和高度z两者)。
多个第二级导电柱140可从第一RDL 130延伸至第二RDL 160，并包封在第二级模制化合物152内。多个第三级导电柱170可从第二RDL 160延伸至第三RDL 190，并包封在第三级模制化合物182内。多个导电凸块198可形成在第三级裸片172上第三RDL 190的相反侧上。在实施方案中，利用裸片附接膜178将第三级裸片172附接到第二RDL 160。在实施方案中，一个或多个第一级裸片110为易失性存储器裸片(例如DRAM)，该对背对背堆叠裸片142为非易失性存储器裸片(例如NAND)，并且第三级裸片为逻辑裸片(例如SoC)。
仍参见图10，在实施方案中，钝化层200在第一级模制化合物122和第一级裸片110上任选地形成。例如，钝化层200可通过层压形成。在一个实施方案中，在除去承载衬底102之后并在分割SiP结构之前形成了钝化层200。在另一个实施方案中，在形成任选第一级导电柱120和/或附接第一级裸片110之前，钝化层200可形成在图1所例示的承载衬底102上。例如，钝化层200可在粘合剂(例如聚合物)或胶带层104上形成。
图11是根据实施方案的PoP结构的横截面侧视图图示。如参照图1至图2所述，第一级导电柱120任选地形成在承载衬底102上，并利用第一级模制化合物122包封。在除去承载衬底102之后，可暴露第一级导电柱120。也可进行另外的处理诸如研磨或蚀刻以暴露第一级导电柱。如图11所示，在实施方案中，第二封装210可与延伸穿过竖直堆叠SiP结构的第一级模制化合物122的第一级导电柱120电连接(例如粘结到导电凸块198)以形成PoP结构。
图12是示出根据实施方案的形成竖直堆叠系统级封装的方法的处理流程。在框1210处，以例如参见图2所述的类似方式利用第一级模制化合物将第一级裸片包封在承载衬底上。在框1220处，第一RDL以例如参见图3所述的类似方式形成在第一级模制化合物上。在实施方案中，第一RDL直接形成在第一级裸片上。在框1230处，以例如参见图4至图6所述的类似方式利用第二级模制化合物将第二级裸片叠堆包封在第一RDL上。在实施方案中，第二级裸片叠堆通过利用裸片附接膜将第一-第二级裸片粘结至第一RDL，并将第二-第二级裸片附接至第一-第二级裸片而形成。在实施方案中，形成在第一RDL上的多个第二级导电柱利用第二级模制化合物包封。在框1240处，第二RDL以例如参见图6所述的类似方式形成在第二级模制化合物上。在实施方案中，第二RDL直接形成在第二级裸片叠堆中的第二-第二级裸片和多个第二级导电柱上。在框1250处，以例如参见图9A所述的类似方式利用第三级模制化合物将第三级裸片包封在第二RDL上。在实施方案中，形成在第二RDL上的多个第三级导电柱利用第三级模制化合物包封。在框1260处，第三RDL形成在第三级模制化合物中。第三RDL可直接在第三级裸片和多个第三级导电柱上形成。多个导电凸块(例如焊料球)可形成在(例如落在)第三RDL上，然后可释放承载衬底。例如，这可得到类似于参照图10所述的竖直堆叠SiP结构。在存在第一级导电柱的情况下，可将第二封装堆叠在竖直堆叠SiP结构上以形成类似于参照图11所述的PoP结构。
在利用实施方案的各个方面中，对本领域技术人员显而易见的是，对于形成堆叠的系统级封装结构，以上实施方案的组合或变型是可能的。尽管以特定于结构特征和/或方法行为的语言对实施方案进行了描述，但应当理解，所附权利要求并不一定限于所描述的特定特征或行为。所公开的特定特征和行为相反应当被理解为用于进行例示的权利要求的实施方案。

Claims (20)

1.一种竖直堆叠系统级封装(SiP)，包括：
第一级裸片，所述第一级裸片包封在第一级模制化合物中；
第一再分配层(RDL)，所述第一再分配层位于所包封的第一级裸片上；
第二级裸片叠堆，所述第二级裸片叠堆在所述第一RDL上包括一对背对背堆叠的裸片并包封在第二级模制化合物中；
第二RDL，所述第二RDL位于所包封的第二级裸片叠堆上；
第三级裸片，所述第三级裸片位于所述第二RDL上并包封在第三级模制化合物中，其中所述第三级裸片背面朝向所述第二RDL；
以及
第三RDL，所述第三RDL位于所包封的第三级裸片上。
2.根据权利要求1所述的竖直堆叠SiP，其中所述第三RDL直接位于所述第三级裸片的柱形凸块上。
3.根据权利要求1所述的竖直堆叠SiP，其中所述第三RDL直接位于所述第三级裸片的接触垫上。
4.根据权利要求1所述的竖直堆叠SiP，其中利用裸片附接膜将所述第三级裸片附接到所述第二RDL。
5.根据权利要求1所述的竖直堆叠SiP，其中所述第一级裸片正面朝向所述第一RDL，并且所述第一RDL直接位于所述第一级裸片的导电凸块上。
6.根据权利要求1所述的竖直堆叠SiP，其中所述一对背对背堆叠的裸片包括粘结到所述第一RDL的第一-第二级裸片，以及第二-第二级裸片，其中所述第二RDL位于所述第二-第二级裸片上。
7.根据权利要求6所述的竖直堆叠SiP，其中利用焊料将所述第一-第二级裸片粘结到所述第一RDL。
8.根据权利要求7所述的竖直堆叠SiP，其中所述第二RDL直接位于所述第二-第二级裸片的柱形凸块上。
9.根据权利要求6所述的竖直堆叠SiP，还包括从所述第一RDL延伸至所述第二RDL的多个第二级导电柱，其中利用所述第二级模制化合物包封所述多个第二级导电柱。
10.根据权利要求9所述的竖直堆叠SiP，还包括从所述第二RDL延伸至所述第三RDL的多个第三级导电柱，其中利用所述第三级模制化合物包封所述多个第三级导电柱。
11.根据权利要求10所述的竖直堆叠SiP，还包括所述第三级裸片上的位于所述第三RDL的相反侧上的多个导电凸块。
12.根据权利要求10所述的竖直堆叠SiP，还包括：
多个第一级导电柱，所述多个第一级导电柱延伸穿过所述第一级模制化合物；以及
第二封装，所述第二封装位于所述第一级模制化合物上并与所述多个第一级导电柱电连接。
13.一种竖直堆叠系统级封装(SiP)，包括：
第一级易失性存储器裸片，所述第一级易失性存储器裸片包封在第一级模制化合物中；
第一再分配层(RDL)，所述第一再分配层位于所包封的第一级易失性存储器裸片上；
第二级非易失性存储器裸片叠堆，所述第二级非易失性存储器裸片叠堆在所述第一RDL上包括一对背对背堆叠的非易失性存储器裸片并包封在第二级模制化合物中；
第二RDL，所述第二RDL位于所包封的第二级非易失性存储器裸片叠堆上；
第三级活动裸片，所述第三级活动裸片位于所述第二RDL上并包封在第三级模制化合物中；以及
第三RDL，所述第三RDL位于所包封的第三级活动裸片上。
14.根据权利要求13所述的竖直堆叠SiP，还包括包封在所述第一级模制化合物中的多个所述第一级易失性存储器裸片，其中所述第一RDL位于所包封的多个第一级易失性存储器裸片上。
15.根据权利要求13所述的竖直堆叠SiP，其中：
所述第一级易失性存储器裸片为DRAM裸片；
所述背对背堆叠的非易失性存储器裸片为NAND裸片；并且
所述第三级活动裸片为SoC裸片。
16.一种形成竖直堆叠系统级封装的方法，所述方法包括：
利用第一级模制化合物将第一级裸片包封在承载衬底上；
在所述第一级模制化合物上形成第一再分配层(RDL)；
利用第二级模制化合物将第二级裸片叠堆包封在所述第一RDL上；
在所述第二级模制化合物上形成第二RDL；
利用第三级模制化合物将第三级裸片包封在所述第二RDL上；
以及
在所述第三级模制化合物上形成第三RDL。
17.根据权利要求16所述的方法，还包括在所述第一级裸片上直接形成所述第一RDL。
18.根据权利要求17所述的方法，还包括利用裸片附接膜将第一-第二级裸片粘结至所述第一RDL，并将第二-第二级裸片附接至所述第一-第二级裸片。
19.根据权利要求18所述的方法，还包括：
利用所述第二级模制化合物包封多个第二级导电柱；以及
在所述第二级裸片叠堆中的所述第二-第二级裸片和所述多个第二级导电柱上直接形成所述第二RDL。
20.根据权利要求19所述的方法，还包括：
利用所述第三级模制化合物包封多个第三级导电柱；以及
在所述第三级裸片和所述多个第三级导电柱上直接形成所述第三RDL。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108831861A (zh) * 2018-08-09 2018-11-16 苏州晶方半导体科技股份有限公司 堆叠式芯片封装方法及封装结构
CN111312690A (zh) * 2020-02-14 2020-06-19 华为技术有限公司 系统级封装及其制备方法
CN112908868A (zh) * 2021-01-18 2021-06-04 上海先方半导体有限公司 存储器三维封装方法及结构
JP2021526309A (ja) * 2018-06-14 2021-09-30 インテル コーポレイション 小型電子アセンブリ
WO2024108906A1 (zh) * 2022-11-21 2024-05-30 长鑫存储技术有限公司 半导体结构的制造方法和半导体结构

Families Citing this family (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2417980A1 (en) 2004-02-11 2012-02-15 Amylin Pharmaceuticals Inc. Hybrid polypeptides with selectable properties
BRPI0614649A2 (pt) 2005-08-11 2011-04-12 Amylin Pharmaceuticals Inc polipeptìdeos hìbridos com propriedades selecionáveis
EP1922336B1 (en) 2005-08-11 2012-11-21 Amylin Pharmaceuticals, LLC Hybrid polypeptides with selectable properties
CA2748314C (en) 2009-02-03 2018-10-02 Amunix Operating Inc. Extended recombinant polypeptides and compositions comprising same
EP3406347A3 (en) 2012-02-27 2019-02-13 Amunix Operating Inc. Xten conjugate compositions and methods of making same
EP2900230B1 (en) 2012-09-27 2018-08-15 The Children's Medical Center Corporation Compounds for the treatment of obesity and methods of use thereof
US20150282367A1 (en) * 2014-03-27 2015-10-01 Hans-Joachim Barth Electronic assembly that includes stacked electronic components
US9601471B2 (en) * 2015-04-23 2017-03-21 Apple Inc. Three layer stack structure
WO2017049585A1 (en) 2015-09-25 2017-03-30 Intel Corporation Method, apparatus and system to interconnect packaged integrated circuit dies
US20170098629A1 (en) * 2015-10-05 2017-04-06 Mediatek Inc. Stacked fan-out package structure
US9984998B2 (en) * 2016-01-06 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Devices employing thermal and mechanical enhanced layers and methods of forming same
CN105514071B (zh) * 2016-01-22 2019-01-25 中芯长电半导体（江阴）有限公司 一种扇出型芯片的封装方法及封装结构
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US9818729B1 (en) * 2016-06-16 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure and method
US9859253B1 (en) * 2016-06-29 2018-01-02 Intel Corporation Integrated circuit package stack
US11469215B2 (en) * 2016-07-13 2022-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US9825007B1 (en) * 2016-07-13 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US10276548B2 (en) * 2016-09-14 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages having dummy connectors and methods of forming same
US9859245B1 (en) * 2016-09-19 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with bump and method for forming the same
US10319698B2 (en) * 2016-11-17 2019-06-11 Intel Corporation Microelectronic device package having alternately stacked die
US10622340B2 (en) * 2016-11-21 2020-04-14 Samsung Electronics Co., Ltd. Semiconductor package
US10373931B2 (en) * 2016-11-29 2019-08-06 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and method of manufacturing the same
WO2018111249A1 (en) * 2016-12-14 2018-06-21 Intel Corporation Integrated circuit packages with plates
CN106653709A (zh) * 2016-12-30 2017-05-10 三星半导体(中国)研究开发有限公司 封装件及其制造方法
US10181455B2 (en) 2017-01-17 2019-01-15 Apple Inc. 3D thin profile pre-stacking architecture using reconstitution method
US10319683B2 (en) * 2017-02-08 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stacked package-on-package structures
US10529698B2 (en) * 2017-03-15 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming same
TWI638439B (zh) * 2017-04-17 2018-10-11 力成科技股份有限公司 半導體封裝結構及其製造方法
KR102275684B1 (ko) 2017-04-18 2021-07-13 삼성전자주식회사 반도체 패키지
KR102351676B1 (ko) 2017-06-07 2022-01-17 삼성전자주식회사 반도체 패키지 및 그 제조 방법
WO2018225589A1 (ja) * 2017-06-09 2018-12-13 株式会社村田製作所 電子部品モジュール
US10943869B2 (en) * 2017-06-09 2021-03-09 Apple Inc. High density interconnection using fanout interposer chiplet
CN109103167B (zh) * 2017-06-20 2020-11-03 晟碟半导体（上海）有限公司 用于存储器装置的异构性扇出结构
US10283474B2 (en) * 2017-06-30 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
TWI633635B (zh) * 2017-07-10 2018-08-21 台星科股份有限公司 可提升空間使用率的堆疊式晶片封裝結構及其封裝方法
TWI622143B (zh) * 2017-07-27 2018-04-21 矽品精密工業股份有限公司 電子封裝件及其製法
US10510721B2 (en) * 2017-08-11 2019-12-17 Advanced Micro Devices, Inc. Molded chip combination
US10475747B2 (en) * 2017-08-14 2019-11-12 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method for fabricating the same
US20190067145A1 (en) * 2017-08-22 2019-02-28 Micron Technology, Inc. Semiconductor device
JP6892360B2 (ja) * 2017-09-19 2021-06-23 キオクシア株式会社 半導体装置
WO2019066986A1 (en) * 2017-09-30 2019-04-04 Intel Corporation STACK OF NON-TSV CHIPS USING PLATED PILLARS / CROSSING MOLD INTERCONNECTION
US10763239B2 (en) * 2017-10-27 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-chip wafer level packages and methods of forming the same
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US10651126B2 (en) * 2017-12-08 2020-05-12 Applied Materials, Inc. Methods and apparatus for wafer-level die bridge
KR102455427B1 (ko) * 2017-12-20 2022-10-17 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
WO2019132966A1 (en) 2017-12-29 2019-07-04 Intel Corporation Microelectronic assemblies with communication networks
WO2019132970A1 (en) 2017-12-29 2019-07-04 Intel Corporation Microelectronic assemblies
DE112017008327T5 (de) 2017-12-29 2020-10-08 Intel Corporation Mikroelektronische anordnungen
US11494682B2 (en) 2017-12-29 2022-11-08 Intel Corporation Quantum computing assemblies
WO2019132971A1 (en) 2017-12-29 2019-07-04 Intel Corporation Microelectronic assemblies
US10475767B2 (en) * 2018-01-04 2019-11-12 Kabushiki Kaisha Toshiba Electronic device
US11315891B2 (en) 2018-03-23 2022-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming semiconductor packages having a die with an encapsulant
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
US10742217B2 (en) 2018-04-12 2020-08-11 Apple Inc. Systems and methods for implementing a scalable system
US11276676B2 (en) * 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
KR102448248B1 (ko) * 2018-05-24 2022-09-27 삼성전자주식회사 Pop형 반도체 패키지 및 그 제조 방법
US10658287B2 (en) * 2018-05-30 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a tapered protruding pillar portion
US10601965B2 (en) * 2018-06-03 2020-03-24 World Richman Manufacturing Corporation Cradle assembly and formation for a mobile communications device
US10854552B2 (en) * 2018-06-29 2020-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10930633B2 (en) 2018-06-29 2021-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Buffer design for package integration
WO2020010265A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US10950554B2 (en) * 2018-07-16 2021-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages with electromagnetic interference shielding layer and methods of forming the same
KR102536269B1 (ko) * 2018-09-14 2023-05-25 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US10770433B1 (en) * 2019-02-27 2020-09-08 Apple Inc. High bandwidth die to die interconnect with package area reduction
US20200294914A1 (en) * 2019-03-13 2020-09-17 Rahul Agarwal Fan-out packages with warpage resistance
CN110731012B (zh) 2019-04-15 2021-01-29 长江存储科技有限责任公司 具有处理器和异构存储器的一体化半导体器件及其形成方法
EP3891806A4 (en) * 2019-04-15 2022-10-12 Yangtze Memory Technologies Co., Ltd. UNITED SEMICONDUCTOR DEVICES HAVING HETEROGENEOUS PROCESSOR AND MEMORIES AND METHODS FOR FORMING THEM
KR20240045345A (ko) 2019-04-15 2024-04-05 양쯔 메모리 테크놀로지스 씨오., 엘티디. 프로세서 및 동적 랜덤 액세스 메모리를 갖는 본디드 반도체 장치 및 이를 형성하는 방법
CN110192269A (zh) * 2019-04-15 2019-08-30 长江存储科技有限责任公司 三维nand存储器件与多个功能芯片的集成
KR20210114016A (ko) 2019-04-30 2021-09-17 양쯔 메모리 테크놀로지스 씨오., 엘티디. 프로세서 및 낸드 플래시 메모리를 갖는 접합된 반도체 소자 및 이를 형성하는 방법
KR102653213B1 (ko) 2019-05-13 2024-04-01 삼성전기주식회사 반도체 패키지
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11195816B2 (en) * 2019-07-23 2021-12-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages comprising a plurality of redistribution structures and methods of forming the same
US11658148B2 (en) 2019-07-25 2023-05-23 Samsung Electronics Co., Ltd. Semiconductor package and a method for manufacturing the same
US11094635B2 (en) * 2019-08-22 2021-08-17 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
DE102020106459B4 (de) * 2019-08-30 2023-04-27 Taiwan Semiconductor Manufacturing Co., Ltd. Chip-package-struktur mit formungsschicht und verfahren zu deren bildung
US11856800B2 (en) * 2019-09-20 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices with system on chip devices
DE102020106799A1 (de) * 2019-09-20 2021-03-25 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiterbauelemente und verfahren zur herstellung
US11158608B2 (en) 2019-09-25 2021-10-26 Powertech Technology Inc. Semiconductor package including offset stack of semiconductor dies between first and second redistribution structures, and manufacturing method therefor
US11094672B2 (en) 2019-09-27 2021-08-17 Intel Corporation Composite IC chips including a chiplet embedded within metallization layers of a host IC chip
WO2021097186A1 (en) 2019-11-13 2021-05-20 Amunix Pharmaceuticals, Inc. Barcoded xten polypeptides and compositions thereof, and methods for making and using the same
US11610911B2 (en) * 2020-01-07 2023-03-21 Micron Technology, Inc. Semiconductor assemblies including combination memory and methods of manufacturing the same
KR20210108075A (ko) 2020-02-25 2021-09-02 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
KR20210110008A (ko) 2020-02-28 2021-09-07 삼성전자주식회사 반도체 패키지
US11264362B2 (en) * 2020-05-28 2022-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of fabricating the same
US11552053B2 (en) 2020-06-25 2023-01-10 Apple Inc. Miniaturization of optical sensor modules through wirebonded ball stacks
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11515261B2 (en) * 2020-09-21 2022-11-29 Apple Inc. Multiple component integration in fanout package with different back side metallization and thicknesses
KR20220058683A (ko) 2020-10-29 2022-05-10 삼성전자주식회사 반도체 패키지
US12125775B2 (en) 2020-11-11 2024-10-22 Nepes Co., Ltd. Semiconductor package and method for manufacturing the same
KR102610246B1 (ko) * 2020-11-11 2023-12-06 주식회사 네패스 반도체 패키지 및 이의 제조 방법
US12125820B2 (en) 2021-02-12 2024-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Through-dielectric vias for direct connection and method forming same
KR20220117032A (ko) 2021-02-16 2022-08-23 삼성전자주식회사 반도체 패키지
TWI760227B (zh) * 2021-05-19 2022-04-01 矽品精密工業股份有限公司 電子封裝件及其製法
US11728248B2 (en) * 2021-07-01 2023-08-15 Deca Technologies Usa, Inc. Fully molded semiconductor structure with through silicon via (TSV) vertical interconnects
US11616003B2 (en) 2021-07-01 2023-03-28 Deca Technologies Usa, Inc. Stackable fully molded semiconductor structure with through silicon via (TSV) vertical interconnects
WO2023008111A1 (ja) * 2021-07-26 2023-02-02 株式会社村田製作所 インターポーザ
US20230260872A1 (en) * 2022-02-16 2023-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and manufacturing method of the same
US20240072029A1 (en) * 2022-08-23 2024-02-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090160053A1 (en) * 2007-12-19 2009-06-25 Infineon Technologies Ag Method of manufacturing a semiconducotor device
CN102931173A (zh) * 2011-08-10 2013-02-13 台湾积体电路制造股份有限公司 多芯片晶圆级封装
CN103077933A (zh) * 2011-10-26 2013-05-01 马克西姆综合产品公司 三维的芯片到晶圆级集成

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2866258B1 (en) 2002-05-31 2019-04-17 Socionext Inc. Semiconductor device and manufacturing method thereof
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
KR20100107540A (ko) 2009-03-26 2010-10-06 대덕전자 주식회사 다기능 인쇄회로기판의 접속 구조 형성 방법
US8895440B2 (en) 2010-08-06 2014-11-25 Stats Chippac, Ltd. Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
US8288209B1 (en) 2011-06-03 2012-10-16 Stats Chippac, Ltd. Semiconductor device and method of using leadframe bodies to form openings through encapsulant for vertical interconnect of semiconductor die
US20130260510A1 (en) 2012-04-02 2013-10-03 Infineon Technologies Ag 3-D Integrated Circuits and Methods of Forming Thereof
US8878360B2 (en) * 2012-07-13 2014-11-04 Intel Mobile Communications GmbH Stacked fan-out semiconductor chip
US20160013156A1 (en) * 2014-07-14 2016-01-14 Apple Inc. Package-on-package options with multiple layer 3-d stacking
US9601471B2 (en) * 2015-04-23 2017-03-21 Apple Inc. Three layer stack structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090160053A1 (en) * 2007-12-19 2009-06-25 Infineon Technologies Ag Method of manufacturing a semiconducotor device
CN102931173A (zh) * 2011-08-10 2013-02-13 台湾积体电路制造股份有限公司 多芯片晶圆级封装
CN103077933A (zh) * 2011-10-26 2013-05-01 马克西姆综合产品公司 三维的芯片到晶圆级集成

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021526309A (ja) * 2018-06-14 2021-09-30 インテル コーポレイション 小型電子アセンブリ
JP7282794B2 (ja) 2018-06-14 2023-05-29 インテル コーポレイション 小型電子アセンブリ
CN108831861A (zh) * 2018-08-09 2018-11-16 苏州晶方半导体科技股份有限公司 堆叠式芯片封装方法及封装结构
CN111312690A (zh) * 2020-02-14 2020-06-19 华为技术有限公司 系统级封装及其制备方法
WO2021159961A1 (zh) * 2020-02-14 2021-08-19 华为技术有限公司 系统级封装及其制备方法
CN112908868A (zh) * 2021-01-18 2021-06-04 上海先方半导体有限公司 存储器三维封装方法及结构
WO2024108906A1 (zh) * 2022-11-21 2024-05-30 长鑫存储技术有限公司 半导体结构的制造方法和半导体结构

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