TWI594396B - 垂直堆疊系統級封裝及形成一垂直堆疊系統級封裝之方法 - Google Patents

垂直堆疊系統級封裝及形成一垂直堆疊系統級封裝之方法 Download PDF

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TWI594396B
TWI594396B TW105108870A TW105108870A TWI594396B TW I594396 B TWI594396 B TW I594396B TW 105108870 A TW105108870 A TW 105108870A TW 105108870 A TW105108870 A TW 105108870A TW I594396 B TWI594396 B TW I594396B
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die
rdl
molding compound
pair
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TW201709473A (zh
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軍 翟
胡坤忠
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蘋果公司
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垂直堆疊系統級封裝及形成一垂直堆疊系統級封裝之方法 相關申請案
本申請案主張2015年4月23日申請之美國臨時專利申請案第62/151,843號之優先權益，該臨時專利申請案之全部揭示內容以引用的方式併入本文中。
本文中所描述之實施例係關於半導體封裝。更特定言之，實施例係關於垂直堆疊式系統級封裝(SiP)結構及製造方法。
對於諸如行動電話、個人數位助理(PDA)、數位攝影機、攜帶型播放機、遊戲以及其他行動裝置之攜帶型及行動電子裝置的當前市場需求要求將更多效能及特徵整合至愈來愈小之空間中。因此，諸如系統級封裝(SiP)及堆疊式封裝(PoP)之各種多晶粒封裝解決方案已變得愈加風行，以滿足對於較高晶粒/組件密度裝置之需求。
將多個晶粒配置於SiP中存在許多不同可能性。舉例而言，晶粒在SiP結構中之垂直整合已演進成2.5D解決方案及3D解決方案。在2.5D解決方案中，多個晶粒可覆晶接合於包括貫穿介層孔以及扇出佈線之仲介層上。在3D解決方案中，多個晶粒可以上下方式堆疊於SiP基板上，且用晶片外引線接合或焊料凸塊進行連接。
在一個實施方案中，記憶體晶粒或封裝(例如，動態隨機存取記憶體(DRAM))堆疊於邏輯晶粒或封裝(例如，特殊應用積體電路 (ASIC))或系統單晶片(SoC)之頂部上。隨著攜帶型及行動電子裝置之市場的發展，要求記憶體晶粒或封裝具有更大記憶能力。
在一實施例中，一種垂直堆疊SiP包括：一第一層級晶粒，其囊封於一第一層級模製化合物中；一第一重佈層(RDL)，其在該經囊封第一層級晶粒上；一第二層級晶粒堆疊，其包括在該第一RDL上之一對背對背堆疊式晶粒且囊封於一第二層級模製化合物中；一第二RDL，其在該經囊封第二層級晶粒堆疊上；一第三層級晶粒，其在該第二RDL上且囊封於一第三層級模製化合物中，其中該第三層級晶粒背面朝向該第二RDL；及一第三RDL，其在該經囊封第三層級晶粒上。
根據實施例，在SiP內達成晶粒之特定定向，其可係特定封裝方法之結果。在一實施例中，第三RDL直接在第三層級晶粒之導電凸塊(諸如柱形凸塊)上。在一實施例中，第三RDL直接在第三層級晶粒之接觸襯墊上。第三層級晶粒可用晶粒附接膜附接至第二RDL。第一層級晶粒可正面朝向第一RDL，其中第一RDL直接在第一層級晶粒之導電凸塊上。根據實施例，該對背對背堆疊式晶粒可包括接合至第一RDL的第一個第二層級晶粒，以及第二個第二層級晶粒，其中第二RDL係在第二個第二層級晶粒上。舉例而言，可用焊料將第一個第二層級晶粒接合至第一RDL，且第二RDL可直接在第二個第二層級晶粒之導電凸塊(例如柱形凸塊)上。
該等封裝層級可另外包括導電柱。舉例而言，複數個第二層級導電柱可自第一RDL延伸至第二RDL，且用第二層級模製化合物經囊封。類似地，複數個第三層級導電柱可自第二RDL延伸至第三RDL，且用第三層級模製化合物經囊封。在一實施例中，複數個導電凸塊形成於第三RDL之與第三層級晶粒對置之側上。在一實施例中，複數個 第一層級導電柱延伸穿過第一層級模製化合物，且第二封裝位於第一層級模製化合物上且與複數個第一層級導電柱電連接及/或由該複數個第一層級導電柱機械支撐。
在一實施例中，一種垂直堆疊SiP包括：一第一層級揮發性記憶體晶粒，其囊封於一第一層級模製化合物中；一第一RDL，其在該經囊封第一層級揮發性記憶體晶粒上；一第二層級非揮發性記憶體晶粒堆疊，其包括在該第一RDL上之一對背對背堆疊式非揮發性記憶體晶粒且囊封於一第二層級模製化合物中；一第二RDL，其在該經囊封第二層級非揮發性記憶體晶粒堆疊上；一第三層級作用晶粒，其在該第二RDL上且囊封於一第三層級模製化合物中；及一第三RDL，其在該經囊封第三層級作用晶粒上。該垂直堆疊SiP可包括囊封於該第一層級模製化合物中之複數個第一層級揮發性記憶體晶粒，其中該第一RDL係在該複數個經囊封第一層級揮發性記憶體晶粒上。在一實施例中，該第一層級揮發性記憶體晶粒係一DRAM晶粒，該背對背堆疊式非揮發性記憶體晶粒係NAND晶粒，且該第三層級作用晶粒係一SoC晶粒。
在一實施例中，一種形成一垂直堆疊SiP之方法包括：用一第一層級模製化合物將一第一層級晶粒囊封於一載體基板上；形成一第一RDL該第一層級模製化合物上；用一第二層級模製化合物將一第二層級晶粒堆疊囊封於該第一RDL上；形成一第二RDL該第二層級模製化合物上；用一第三層級模製化合物將一第三層級晶粒囊封於該第二RDL上；及形成一第三RDL該第三層級模製化合物上。舉例而言，可直接形成該第一RDL於該第一層級晶粒上。將一第一個第二層級晶粒接合至該第一RDL，且用一晶粒附接膜將一第二個第二層級晶粒附接至該第一個第二層級晶粒。
該等製造方法可另外包括導電柱之整合。在一實施例中，用該 第二層級模製化合物囊封複數個第二層級導電柱，且直接形成該第二RDL於該第二層級晶粒堆疊中的該第二個第二層級晶粒及該複數個第二層級導電柱上。在一實施例中，用該第三層級模製化合物囊封複數個第三層級導電柱，且直接形成該第三RDL該第三層級晶粒及該複數個第三層級導電柱上。
102‧‧‧載體基板
104‧‧‧黏接劑(例如聚合物)或膠帶層
110‧‧‧第一層級晶粒
112‧‧‧膜
114‧‧‧凸塊/柱形凸塊
115‧‧‧頂表面/經暴露表面
120‧‧‧第一層級導電柱
121‧‧‧頂表面/經暴露表面
122‧‧‧第一層級模製化合物
123‧‧‧頂表面
130‧‧‧第一重佈層
132‧‧‧重佈線/嵌入式重佈線
134‧‧‧介電層
135‧‧‧接觸襯墊/第一層級模製及扇出部
136‧‧‧凸塊下金屬層襯墊
140‧‧‧第二層級導電柱
141‧‧‧頂表面/經暴露表面
142‧‧‧第二層級晶粒/頂部第二層級晶粒/底部第二層級晶粒/第二層級堆疊式晶粒/背對背堆疊式晶粒/第一個第二層級晶粒/第二個第二層級晶粒
144‧‧‧柱形凸塊/凸塊/導電凸塊
145‧‧‧頂表面/經暴露表面
146‧‧‧焊料尖端
148‧‧‧晶粒附接膜
150‧‧‧底部填充材料
152‧‧‧第二層級模製化合物
153‧‧‧頂表面
155‧‧‧第二層級模製及扇出部
160‧‧‧第二重佈層
162‧‧‧重佈線/嵌入式重佈線
164‧‧‧介電層
165‧‧‧接觸襯墊
170‧‧‧第三層級導電柱
171‧‧‧頂表面/經暴露表面
172‧‧‧第三層級晶粒
174‧‧‧凸塊/導電凸塊
175‧‧‧頂表面/經暴露表面
178‧‧‧晶粒附接膜
182‧‧‧第三層級模製化合物
183‧‧‧頂表面
185‧‧‧第三層級模製及扇出部
190‧‧‧第三重佈層
192‧‧‧重佈線/嵌入式重佈線
194‧‧‧介電層
195‧‧‧接觸襯墊
198‧‧‧導電凸塊
200‧‧‧鈍化層
210‧‧‧第二封裝
圖1為根據一實施例之安裝於載體基板上之複數個晶粒的橫截面側視圖說明。
圖2為根據一實施例之囊封於第一層級模製化合物中之複數個晶粒的橫截面側視圖說明。
圖3為根據一實施例之形成於第一層級模製化合物上之第一RDL的橫截面側視圖說明。
圖4為根據一實施例之形成於第一RDL上之導電柱之橫截面側視圖說明。
圖5A為根據一實施例之安裝於第一RDL上之晶粒的橫截面側視圖說明。
圖5B為根據一實施例之接合至具有聚合物界定之焊墊之第一RDL之晶粒的近距橫截面側視圖說明。
圖5C為根據一實施例之接合至具有UBM界定之焊墊之第一RDL之晶粒的近距橫截面側視圖說明。
圖6為根據一實施例之黏著於第一RDL上之晶粒堆疊的橫截面側視圖說明。
圖7為在第一層級模製及扇出結構上之第二層級模製及扇出結構的橫截面側視圖說明。
圖8為根據一實施例之黏著於第二RDL上之晶粒及形成於第二RDL上之導電柱的橫截面側視圖說明。
圖9A為在第二層級模製及扇出結構上之第三層級模製及扇出結構的橫截面側視圖說明。
圖9B為根據一實施例之在個別封裝的單粒化之前的三層堆疊結構之橫截面側視圖說明。
圖10為根據一實施例之垂直堆疊式SiP結構的橫截面側視圖說明。
圖11為根據一實施例之PoP結構的橫截面側視圖說明。
圖12為說明根據一實施例之形成垂直堆疊式SiP結構之方法的程序流程。
實施例描述垂直堆疊式SiP結構。在各種實施例中，參看圖式進行描述。然而，某些實施例可在無此等特定細節中之一或多者的情況下或與其他已知方法及組態組合而加以實踐。在以下描述中，闡述諸如特定組態、尺寸及處理序等眾多特定細節以便提供對實施例的透徹理解。在其他情況下，未特別詳細描述熟知半導體製程及製造技術，以便不不必要地混淆實施例。貫穿本說明書參考「一項實施例」意謂接合實施例描述之特定特徵、結構、組態或特性包括於至少一項實施例中。因此，貫穿本說明書之各種地方出現的片語「在一項實施例中」未必係指同一實施例。此外，可在一或多項實施例中以任何適合之方式組合特定特徵、結構、組態或特性。
如本文中所使用之術語「正面」、「背面」、「至」、「在之間」及「在上」可指一個層相對於其他層之相對位置。在另一層「上」或接合「至」另一層或與另一層「接觸」之一個層可直接與該另一層接觸或可具有一或多個介入層。在若干層「之間」之一個層可直接與該等層接觸或可具有一或多個介入層。
在一項態樣中，實施例描述垂直堆疊SiP。在一實施例中，一種 垂直堆疊SiP包括：一第一層級晶粒，其囊封於一第一層級模製化合物中；一第一重佈層(RDL)，其在該經囊封第一層級晶粒上；一第二層級晶粒堆疊，其包括在該第一RDL上之一對背對背堆疊式晶粒且囊封於一第二層級模製化合物中；一第二RDL，其在該經囊封第二層級晶粒堆疊上；一第三層級晶粒，其在該第二RDL上且囊封於一第三層級模製化合物中；及一第三RDL，其在該經囊封第三層級晶粒上。複數個第二層級導電柱可將第一RDL電連接至第二RDL，且複數個第三層級導電柱可電連接第二RDL與第三RDL。根據實施例，導電柱(例如第一層級、第二層級、第三層級等中之任一者)可提供機械支撐。舉例而言，可除組件之間的電連接以外亦提供機械支撐，或在不提供電連接之情況下提供機械支撐。在一些實施例中，封裝層級內之導電柱之一部分將提供電連接及機械支撐，而該封裝層級內之導電柱之另一部分將提供機械支撐但不提供電連接。
在一項態樣中，實施例描述整合多種類型之記憶體晶粒與邏輯晶粒(例如ASIC或SoC)之垂直堆疊SiP。在一實施例中，垂直堆疊SiP包括用於揮發性記憶體(例如DRAM、靜態隨機存取記憶體(SRAM)、偽SRAM、浮體，等)、非揮發性記憶體(例如NAND、NOR、可抹除可程式化唯讀記憶體(EPROM)、電子可抹除可程式化唯讀記憶體(EEPROM)、磁阻隨機存取記憶體(MRAM)、鐵電隨機存取記憶體(FRAM)、相變記憶體(PCM)，等)及邏輯晶粒之獨立模製層級。在一實施例中，垂直堆疊SiP包含包括一或多個揮發性記憶體晶粒(例如DRAM)之第一層級模製、包括背對背堆疊式非揮發性記憶體晶粒(例如NAND)之第二層級模製，以及包括邏輯晶粒(例如ASIC或SoC)之第三層級模製。
在一項態樣中，實施例描述可減少電路板上之面積(例如x-y維度)之量的垂直堆疊SiP。已觀察到，某些非揮發性記憶體晶粒(例如 NAND)可具有比某些揮發性記憶體晶粒(例如DRAM)大之x-y尺寸佔據面積。舉例而言，此可歸因於行動裝置中之經增加記憶容量。根據實施例，記憶體之非揮發性記憶體晶粒可具有比揮發性記憶體晶粒(例如用於快取記憶體)大之x-y尺寸。根據實施例，垂直堆疊SiP結構可包括多個並排配置之第一層級晶粒。根據實施例，垂直堆疊SiP結構可包括具有大x-y尺寸(相對於SiP中之另一晶粒)之多個第二層級晶粒，其在垂直堆疊SiP內以背對背方式堆疊。另外，可藉由在背對背堆疊式晶粒之對置側上使用重佈層(RDL)而實現背對背堆疊式晶粒之扇出。以此方式，可藉由使用RDL之扇出緩和對總體封裝高度(z高度)之影響，該RDL可製造成具有比用於傳統仲介層及引線接合之情況小得多之厚度。
現參看圖1，提供黏著於諸如玻璃面板、矽晶圓、金屬面板等之載體基板102上之複數個第一層級晶粒110之橫截面側視圖說明。載體基板102可包括用於黏著複數個第一層級晶粒110之黏著劑(例如聚合物)或膠帶層104。在一實施例中，第一層級晶粒110以諸如晶粒附接膜或環氧接合材料之膜112黏著至載體基板上。在一實施例中，第一層級晶粒110係記憶體晶粒。在一實施例中，第一層級晶粒110係揮發性記憶體晶粒，諸如DRAM、SRAM、偽SRAM、浮體，等。在一具體實施例中，第一層級晶粒110係DRAM晶粒。
在於圖1中說明之實施例中，第一層級晶粒110面向上黏著至載體基板102上，使得包括凸塊114(例如柱形凸塊)之作用側面向上。舉例而言，柱形凸塊114可係銅柱形凸塊。凸塊114可係選用的，且替代地可為用於第一層級晶粒110之暴露接觸襯墊。根據實施例，第一層級導電柱120可視情況形成於載體基板102上。選用之第一層級導電柱120之材料可包括(但不限於)金屬材料，諸如銅、鈦、鎳、金及其組合或合金。第一層級導電柱120可使用適合之處理技術形成，且可由 多種適合之材料(例如銅)及層形成。在一實施例中，第一層級導電柱120係藉由鍍敷技術形成，諸如使用經圖案化光阻以界定柱結構尺寸接著移除經圖案化光阻層之電鍍。在一實施例中，選用之第一層級導電柱120係在黏著第一層級晶粒110之前形成。
現參看圖2，然後，複數個第一層級晶粒110及選用之第一層級導電柱120囊封於載體基板102上之第一層級模製化合物122中。舉例而言，第一層級模製化合物122可包括熱固型交聯樹脂(例如環氧樹脂)，不過如電子封裝中已知，可使用其他材料。可使用諸如(但不限於)轉注模製、壓縮模製及層壓之合適技術來實現囊封。在用第一層級模製化合物122進行囊封之後，該結構可視情況另外以研磨(例如化學機械拋光)操作、蝕刻操作進行處理，或經圖案化且經蝕刻以暴露第一層級晶粒110、凸塊114，以及視情況地第一層級導電柱120。在一實施例中，凸塊114及第一層級模製化合物122之頂表面115、123(以及視情況地第一層級導電柱120之頂表面121)在研磨或蝕刻操作之後係共面的。在一實施例中，凸塊114可置換為第一層級晶粒110之接觸襯墊，其可(例如)藉由對第一層級模製化合物122進行蝕刻或雷射鑽孔而暴露。
現參看圖3，第一重佈層(RDL)130形成於第一層級模製化合物122及凸塊114(或接觸襯墊)之經暴露表面115，以及第一層級導電柱之視情況經暴露表面121(若存在)上。第一RDL 130可包括單個重佈線132或多個重佈線132及介電層134。第一RDL 130可藉由逐層製程形成，且可使用薄膜技術形成。在一實施例中，第一RDL 130之總厚度小於50μm，或更具體言之，小於30μm，諸如大約20μm。在一實施例中，第一RDL 130包括嵌入式重佈線132(嵌入式跡線)。舉例而言，可藉由首先形成晶種層，接著形成金屬(例如銅)圖案而產生重佈線132。替代地，可藉由沈積(例如濺鍍)及蝕刻形成重佈線132。重佈 線132之材料可包括(但不限於)金屬材料，諸如銅、鈦、鎳、金及其組合或合金。然後，重佈線132之金屬圖案嵌入於視情況經圖案化之介電層134中。該(等)介電層134可係任何合適之材料，諸如氧化物或聚合物(例如聚醯亞胺)。
在所說明之實施例中，重佈線132直接形成於凸塊114(或接觸襯墊)之頂表面115上。更具體言之，第一RDL 130之重佈線132之接觸襯墊135直接形成於第一層級晶粒110之凸塊114上。共同地，第一RDL 130及經模製第一層級晶粒110可形成第一層級模製及扇出部135。
在形成第一RDL 130之後，複數個第二層級導電柱140可形成於第一RDL 130上，如在圖4中所說明。第二層級導電柱140可與如上文關於選用之第一層級導電柱120所描述類似地形成且由與如上文關於選用之第一層級導電柱120所描述的材料相同材料形成。
現參看圖5A，一或多個第二層級晶粒142黏著於第一RDL 130上。在一實施例中，第二層級晶粒142係非揮發性記憶體晶粒，諸如(例如NAND、NOR、EPROM、EEPROM、MRAM、FRAM、PCM，等)。在一具體實施例中，第二層級晶粒142係NAND晶粒。在一實施例中，第二層級晶粒142比第一層級晶粒110中之任一者更寬，具有較大之x-y區域。在於圖5A中說明之實施例中，第二層級晶粒142正面朝向第一RDL 130且藉由導電凸塊(諸如柱形凸塊、焊料凸塊或具有焊料尖端之柱形凸塊)附接至第一RDL 130之焊墊或凸塊下金屬層(UBM)襯墊。在一實施例中，第二層級晶粒142之背側不包括任何導電接觸件(例如柱形凸塊、焊料凸塊，等)。
焊墊或UBM襯墊可以多種方式形成於第一RDL 130中。圖5B為接合至第一RDL之第二層級晶粒142的近距說明，在該第一RDL中，焊墊開口已由介電層134中之開口界定。在所說明之特定實施例中，第二層級晶粒142凸塊包括具有焊料尖端146之柱形凸塊144。圖5C為 包括具有接合至第一RDL之焊料尖端146之柱形凸塊144的第二層級晶粒142之近距說明，在該第一RDL中，焊墊係由UBM襯墊136界定。現返回參看圖5A，在將第二層級晶粒142黏著至第一RDL 130之後，底部填充材料150可視情況應用至第二層級晶粒142與第一RDL 130之間。
現參看圖6，第二個第二層級晶粒142附接至第一個第二層級晶粒142。在所說明之特定實施例中，第二個第二層級晶粒142之背側以背對背配置附接至第一個第二層級晶粒142之背側。舉例而言，第二層級晶粒142可使用晶粒附接膜(DAF)148附接至彼此。DAF 148可係黏性材料，且可視情況為導熱性的。舉例而言，DAF可視情況在晶粒附接之後經由化學、熱或紫外光加以固化。
在一實施例中，第一個(例如在圖6中為頂部)及第二個(例如在圖6中為底部)第二層級晶粒142係相同的。舉例而言，各第二層級晶粒142可係相同NAND晶粒。在一實施例中，堆疊式第二層級晶粒142係相同的，唯一例外係對柱形凸塊之修改。舉例而言，頂部第二層級晶粒142(如在圖6中所示)可包括不具有焊料尖端之柱形凸塊144(或替代地在不存在柱形凸塊之情況下，係接觸襯墊)，而底部第二層級晶粒142(如在圖6中所示)包括具有焊料尖端146之柱形凸塊144，如在圖5B至圖5C中所說明。
現參看圖7，第二層級晶粒142堆疊及第二層級導電柱140囊封於載體基板102上之第二層級模製化合物152中。簡要地參看圖9B，第二層級模製化合物152可視情況包圍第一層級模製化合物122，不過此並非必需的。第二層級模製化合物152可與第一層級模製化合物122類似地形成且由與第一層級模製化合物122相同的材料形成。在用第二層級模製化合物進行囊封之後，該結構可視情況以研磨操作、蝕刻操作進行處理，或經圖案化且經蝕刻以暴露頂部第二層級晶粒142、凸 塊144(或在不存在凸塊之情況下係接觸襯墊)，以及第二層級導電柱140。在一實施例中，凸塊144之頂表面145、第二層級模製化合物152之頂表面153以及第二層級導電柱140之頂表面141在研磨或蝕刻操作之後係共面的。
然後，第二重佈層(RDL)160形成於第二層級模製化合物152、凸塊144(或接觸襯墊)之經暴露表面145以及第二層級導電柱140之經暴露表面141上。第二RDL 160可包括單個重佈線162或多個重佈線162及介電層164。第二RDL 160可藉由逐層製程形成，且可使用薄膜技術形成。在一實施例中，第二RDL 160之總厚度小於50μm，或更具體言之，小於30μm，諸如大約20μm。在一實施例中，第二RDL 160包括嵌入式重佈線162(嵌入式跡線)。舉例而言，可藉由首先形成晶種層，接著形成金屬(例如銅)圖案而產生重佈線162。替代地，可藉由沈積(例如濺鍍)及蝕刻形成重佈線162。重佈線162之材料可包括(但不限於)金屬材料，諸如銅、鈦、鎳、金及其組合或合金。然後，重佈線162之金屬圖案嵌入於視需要經圖案化之介電層164中。該(等)介電層164可係任何合適之材料，諸如氧化物或聚合物(例如聚醯亞胺)。
在所說明之實施例中，重佈線162直接形成於凸塊144(或在不存在凸塊之情況下係接觸襯墊)之頂表面145上。更具體言之，第二RDL160之重佈線162之接觸襯墊165直接形成於頂部第二層級晶粒142之凸塊144上。共同地，第二RDL 160及經模製第二層級堆疊式晶粒142可形成第二層級模製及扇出部155。重佈線162亦可直接形成於複數個第二層級導電柱140之表面141上。
在形成第二RDL 160之後，複數個第三層級導電柱170可形成於第二RDL 160上，如在圖8中所說明。第三層級導電柱可與如上文關於選用之第一層級導電柱120所描述類似地形成且由與如上文關於選 用之第一層級導電柱120所描述的材料相同的材料形成。
仍參看圖8，一或多個第三層級晶粒172黏著於第二RDL 160上。舉例而言，一或多個第三層級晶粒172可在形成第三層級導電柱170之後經黏著。在一實施例中，第三層級晶粒172係邏輯晶粒，諸如ASIC或SoC。在一具體實施例中，第三層級晶粒172係SoC晶粒。如在圖8中所示，第三層級晶粒172可背面朝向第二RDL 160。在此配置中，第三層級晶粒172可藉由DAF 178(類似於上文所述之DAF 148)附接至第二RDL 160。第三層級晶粒172可包括凸塊174，諸如柱形凸塊(例如銅柱形凸塊)。替代地，第三層級晶粒172可包括代替凸塊174之經暴露接觸襯墊。
現參看圖9A，第三層級晶粒172及第三層級導電柱170囊封於載體基板102上之第三層級模製化合物182中。簡要地參看圖9B，第三層級模製化合物182可視情況包圍第一層級模製化合物122及第二層級模製化合物152，不過此並非必需的。第三層級模製化合物182可與第一層級模製化合物122及第二層級模製化合物152類似地形成且由與第一層級模製化合物122及第二層級模製化合物152相同的材料形成。在用第三層級模製化合物進行囊封之後，該結構可視情況以研磨操作、蝕刻操作進行處理，或經圖案化且經蝕刻以暴露第三層級晶粒172、凸塊174(或接觸襯墊)以及第三層級導電柱170。在一實施例中，凸塊174之頂表面175、第三層級模製化合物182之頂表面183以及第三層級導電柱170之頂表面171在研磨或蝕刻操作之後係共面的。
然後，第三重佈層(RDL)190形成於第三層級模製化合物182、凸塊174(或接觸襯墊)之經暴露表面175及第三層級導電柱170之經暴露表面171上。第三RDL 190可包括單個重佈線192或多個重佈線192及介電層194。第三RDL 190可藉由逐層製程形成，且可使用薄膜技術形成。在一實施例中，第三RDL 190之總厚度小於50μm，或更具體 言之，小於30μm，諸如大約20μm。在一實施例中，第三RDL 190包括嵌入式重佈線192(嵌入式跡線)。舉例而言，可藉由首先形成晶種層，接著形成金屬(例如銅)圖案而產生重佈線192。替代地，可藉由沈積(例如濺鍍)及蝕刻形成重佈線192。重佈線192之材料可包括(但不限於)金屬材料，諸如銅、鈦、鎳、金及其組合或合金。然後，重佈線192之金屬圖案嵌入於視情況經圖案化之介電層194中。該(等)介電層194可係任何合適之材料，諸如氧化物或聚合物(例如聚醯亞胺)。
在所說明之實施例中，重佈線192直接形成於凸塊174之頂表面175上。更具體言之，第三RDL 190之重佈線192之接觸襯墊195直接形成於晶粒172之凸塊174(或接觸襯墊)上。共同地，第三RDL 190及經模製第三層級晶粒172可形成第三層級模製及扇出部185。在形成第三RDL 190之後，複數個導電凸塊198(例如焊料凸塊，或柱形凸塊)可形成於第三RDL 190上。
現參看圖9B，提供在個別封裝的單粒化之前的根據一實施例之三層(或三個層級)堆疊結構之橫截面側視圖說明，其中虛線說明個別封裝之單粒化線。在一實施例中，模製化合物122、152之邊緣可係有凹口的以容納在囊封期間使用之模穴。有凹口的區域隨後可在單粒化期間經修整。圖9B中說明之特定實施例係示例性的，且多種模製組態係可能的。相同或不同模穴可用於不同模製層級。另外，模穴可具有相同或不同深度(高度)及面積。在一實施例中，同一模穴可用於所有模製層級。
圖10係在移除載體基板及封裝單粒化之後之垂直堆疊式SiP結構的橫截面側視圖說明。在一實施例中，垂直堆疊式SiP包括：第一層級晶粒110，其囊封於第一層級模製化合物122中；第一重佈層(RDL)130，其在經囊封第一層級晶粒110上；第二層級晶粒堆疊，其包括在第一RDL 130上之一對背對背堆疊式晶粒142且囊封於第二層 級模製化合物152中；第二RDL 160，其在經囊封第二層級晶粒堆疊上；第三層級晶粒172，其在第二RDL 160上且囊封於第三層級模製化合物182中；及第三RDL 190，其在經囊封第三層級晶粒172上。複數個第二層級導電柱140可將第一RDL 130電連接至第二RDL 160，且複數個第三層級導電柱170可電連接第二RDL 160與第三RDL 190。如圖所示，第三層級晶粒172背面朝向第二RDL 160(例如在面向第二RDL 160的第三層級晶粒172之背側上不存在導電接觸件)。在此組態中，在第三層級晶粒172與第二RDL 160之間不存在直接電連接。舉例而言，第三層級晶粒172可用晶粒附接膜178附接至第二RDL。第三RDL 190可直接在第三層級晶粒172之導電凸塊174(例如柱形凸塊)上。在一實施例中，第三層級晶粒172與第二RDL 160之間的電路徑延伸通過第三RDL 190及第三層級導電柱170至第二RDL 160。
如圖所示，第一層級晶粒110正面朝向第一RDL。第一RDL 130可直接在第一層級晶粒110之導電凸塊114(例如柱形凸塊)上。可存在複數個並排的第一層級110。與垂直堆疊第一層級晶粒110對比，此可減小封裝的總z高度。在一實施例中，一或多個第一層級晶粒110係DRAM晶粒。
該對背對背堆疊式晶粒142可包括接合至第一RDL 130的第一個第二層級晶粒142，以及第二個第二層級晶粒142，其中第二RDL 160在第二個第二層級晶粒142上。如圖所示，可用焊料將第一個第二層級晶粒142接合至第一RDL 130。第二RDL 160可直接在第二個第二層級晶粒142之導電凸塊144(例如柱形凸塊)上。第二個第二層級晶粒142可用晶粒附接膜148附接至第一個第二層級晶粒142。在一實施例中，該對背對背堆疊式晶粒142係非揮發性記憶體晶粒，諸如NAND晶粒。根據實施例，歸因於相對較大的大小，NAND晶粒係背對背堆疊的，而非並排堆疊的。因此，藉由在封裝之中部內使用背對背堆疊 組態，可減小總體封裝大小(x-y及z高度二者)。
複數個第二層級導電柱140可自第一RDL 130延伸至第二RDL 160，且囊封於第二層級模製化合物152內。複數個第三層級導電柱170可自第二RDL 160延伸至第三RDL 190且囊封於第三層級模製化合物182內。複數個導電凸塊198可形成於第三RDL 190之與第三層級晶粒172對置之側上。在一實施例中，第三層級晶粒172用晶粒附接膜178附接至第二RDL 160。在一實施例中，一或多個第一層級晶粒110係揮發性記憶體晶粒(例如DRAM)，該對背對背堆疊式晶粒142係非揮發性記憶體晶粒(例如NAND)，且第三層級晶粒係邏輯晶粒(例如SoC)。
仍參看圖10，在一實施例中，鈍化層200視情況形成於第一層級模製化合物122及第一層級晶粒110上方。舉例而言，鈍化層200可藉由層壓形成。在一項實施例中，鈍化層200係在移除載體基板102之後且在SiP結構單粒化之前形成。在另一實施例中，鈍化層200可在形成選用之第一層級導電柱120及/或附接第一層級晶粒110之前形成於圖1中說明之載體基板102上。舉例而言，鈍化層200可形成於黏著劑(例如聚合物)或膠帶層104上方。
圖11為根據一實施例之PoP結構的橫截面側視圖說明。如關於圖1至圖2所描述，第一層級導電柱120視情況形成於載體基板102上，且用第一層級模製化合物122進行囊封。在移除載體基板102後，即可暴露第一層級導電柱120。亦可執行諸如研磨或蝕刻之額外處理以暴露第一層級導電柱。如圖11中所示，在一實施例中，第二封裝210可與延伸穿過垂直堆疊式SiP結構之第一層級模製化合物122之第一層級導電柱120電連接(例如藉由導電凸塊198接合至第一層級導電柱120)，從而形成PoP結構。
圖12為說明根據一實施例之形成垂直堆疊式系統級封裝之方法 的程序流程。在方塊1210處，例如與關於圖2所描述的類似，用第一層級模製化合物將第一層級晶粒囊封於載體基板上。在方塊1220處，例如與關於圖3所描述的類似，形成第一RDL於第一層級模製化合物上。在一實施例中，第一RDL直接形成於第一層級晶粒上。在方塊1230處，例如與關於圖4至圖6所描述的類似，用第二層級模製化合物將第二層級晶粒堆疊囊封於第一RDL上。在一實施例中，藉由將第一個第二層級晶粒接合至第一RDL且用晶粒附接膜將第二個第二層級晶粒附接至第一個第二層級晶粒，形成第二層級晶粒堆疊。在一實施例中，用第二層級模製化合物囊封形成於第一RDL上之複數個第二層級導電柱。在方塊1240處，例如與關於圖6所描述的類似，形成第二RDL於第二層級模製化合物上。在一實施例中，第二RDL直接形成於第二層級晶粒堆疊中的第二個第二層級晶粒及複數個第二層級導電柱上。在方塊1250處，例如與關於圖9A所描述的類似地，用第三層級模製化合物將第三層級晶粒囊封於第二RDL上。在一實施例中，用第三層級模製化合物囊封形成於第二RDL上之複數個第三層級導電柱。在方塊1260處，形成第三RDL於第三層級模製化合物上。第三RDL可直接形成於第三層級晶粒及複數個第三層級導電柱上。複數個導電凸塊(例如焊球)可形成(例如滴落)於第三RDL上，且接著可釋放載體基板。舉例而言，此可產生類似於關於圖10描述之彼結構的垂直堆疊式SiP結構。在存在第一層級導電柱之情況下，第二封裝可堆疊於垂直堆疊式SiP結構上以形成PoP結構，其類似於關於圖11描述之彼結構。
在利用實施例之各種態樣時，對於熟習此項技術者將變得顯而易見：以上實施例之組合或變化有可能用於形成堆疊式系統級封裝結構。儘管已經用對於結構特徵及/或方法動作而言特定之語言描述實施例，但應理解，所附申請專利範圍不一定限於所描述之特定特徵或動作。所揭示之特定特徵及動作應替代地理解為申請專利範圍之用於 說明之實施例。
110‧‧‧第一層級晶粒
112‧‧‧膜
114‧‧‧凸塊/柱形凸塊
122‧‧‧第一層級模製化合物
123‧‧‧頂表面
130‧‧‧第一重佈層
140‧‧‧第二層級導電柱
142‧‧‧第二層級晶粒/頂部第二層級晶粒/底部第二層級晶粒/第二層級堆疊式晶粒/背對背堆疊式晶粒/第一個第二層級晶粒/第二個第二層級晶粒
144‧‧‧柱形凸塊/凸塊/導電凸塊
148‧‧‧晶粒附接膜
152‧‧‧第二層級模製化合物
155‧‧‧第二層級模製及扇出部
160‧‧‧第二重佈層
170‧‧‧第三層級導電柱
172‧‧‧第三層級晶粒
174‧‧‧凸塊/導電凸塊
178‧‧‧晶粒附接膜
182‧‧‧第三層級模製化合物
185‧‧‧第三層級模製及扇出部
190‧‧‧第三重佈層
198‧‧‧導電凸塊
200‧‧‧鈍化層

Claims (20)

  1. 一種垂直堆疊系統級封裝(SiP)，其包含：一對第一層級晶粒，其囊封於一第一層級模製化合物中；一第一重佈層(RDL)，其在該經囊封之該對第一層級晶粒上；一第二層級晶粒堆疊，其包括在該第一RDL上之一對背對背堆疊式晶粒且囊封於一第二層級模製化合物中；一第二RDL，其在該經囊封第二層級晶粒堆疊上；一第三層級晶粒，其在該第二RDL上且囊封於一第三層級模製化合物中，其中該第三層級晶粒背面朝向該第二RDL；及一第三RDL，其在該經囊封第三層級晶粒上；其中該對第一層級晶粒的每一個是一第一型的晶粒，而且該對背對背堆疊式晶粒的每一個是一第二型的晶粒，該第二型的晶粒不同於第一型的晶粒，該對背對背堆疊式晶粒的每一個比該對第一層級晶粒的每一個的x-y尺寸還大，而且第三層級晶粒是一第三型的晶粒，該第三型的晶粒不同於該第一型的晶粒及該第二型的晶粒。
  2. 如請求項1之垂直堆疊SiP，其中該第三RDL直接在該第三層級晶粒之一柱形凸塊上。
  3. 如請求項1之垂直堆疊SiP，其中該第三RDL直接在該第三層級晶粒之一接觸襯墊上。
  4. 如請求項1之垂直堆疊SiP，其中該第三層級晶粒用一晶粒附接膜附接至該第二RDL。
  5. 如請求項1之垂直堆疊SiP，其中該對第一層級晶粒的每一個正面朝向該第一RDL且該第一RDL直接在該對第一層級晶粒的每一個之一導電凸塊上。
  6. 如請求項1之垂直堆疊SiP，其中該對背對背堆疊式晶粒包括接合至該第一RDL的一第一個第二層級晶粒，以及一第二個第二層級晶粒，其中該第二RDL係在該第二個第二層級晶粒上。
  7. 如請求項6之垂直堆疊SiP，其中用焊料將該第一個第二層級晶粒接合至該第一RDL。
  8. 如請求項7之垂直堆疊SiP，其中該第二RDL直接在該第二個第二層級晶粒之一柱形凸塊上。
  9. 如請求項6之垂直堆疊SiP，其進一步包含自該第一RDL延伸至該第二RDL之複數個第二層級導電柱，其中用該第二層級模製化合物囊封該複數個第二層級導電柱。
  10. 如請求項9之垂直堆疊SiP，其進一步包含自該第二RDL延伸至該第三RDL之複數個第三層級導電柱，其中用該第三層級模製化合物囊封該複數個第三層級導電柱。
  11. 如請求項10之垂直堆疊SiP，其進一步包含在該第三RDL之與該第三層級晶粒對置之一側上之複數個導電凸塊。
  12. 如請求項10之垂直堆疊SiP，其進一步包含：複數個第一層級導電柱，其延伸穿過該第一層級模製化合物；及一第二封裝，其在該第一層級模製化合物上，且與該複數個第一層級導電柱電連接。
  13. 如請求項1之垂直堆疊SiP，其中該第一型晶粒是一揮發性記憶體晶粒，而且該第二型晶粒是一非揮發性記憶體晶粒。
  14. 如請求項13之垂直堆疊SiP，其中該第三型晶粒是一邏輯晶粒。
  15. 如請求項14之垂直堆疊SiP，其中：該對第一層級晶粒的每一個係一動態隨機存取記憶體(DRAM)晶粒； 該對背對背堆疊式晶粒係NAND晶粒；且該第三層級作用晶粒係一系統單晶片(SoC)晶粒。
  16. 一種形成一垂直堆疊系統級封裝之方法，其包含：用一第一層級模製化合物將一對第一層級晶粒囊封於一載體基板上；形成一第一重佈層(RDL)於該第一層級模製化合物上；用一第二層級模製化合物將一第二層級晶粒堆疊囊封於該第一RDL上，該第二層級晶粒堆疊包括在該第一RDL上之一對背對背堆疊式晶粒；形成一第二RDL於該第二層級模製化合物上；用一第三層級模製化合物將一第三層級晶粒囊封於該第二RDL上；及形成一第三RDL於該第三層級模製化合物上；其中該對第一層級晶粒的每一個是一第一型的晶粒，而且該對背對背堆疊式晶粒的每一個是一第二型的晶粒，該第二型的晶粒不同於第一型的晶粒，該對背對背堆疊式晶粒的每一個比該對第一層級晶粒的每一個的x-y尺寸還大，而且第三層級晶粒是一第三型的晶粒，該第三型的晶粒不同於該第一型的晶粒及該第二型的晶粒。
  17. 如請求項16之方法，其進一步包含直接形成該第一RDL於該對第一層級晶粒上。
  18. 如請求項17之方法，其進一步包含將一第一個第二層級晶粒接合至該第一RDL，且用一晶粒附接膜將一第二個第二層級晶粒附接至該第一個第二層級晶粒，其中該對背對背堆疊式晶粒包含第一個第二層級晶粒以及第二個第二層級晶粒。
  19. 如請求項18之方法，其進一步包含： 用該第二層級模製化合物囊封複數個第二層級導電柱；及直接形成該第二RDL於該第二層級晶粒堆疊中的該第二個第二層級晶粒及該複數個第二層級導電柱上。
  20. 如請求項19之方法，其進一步包含：用該第三層級模製化合物囊封複數個第三層級導電柱；及直接形成該第三RDL於該第三層級晶粒及該複數個第三層級導電柱上。
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