WO2021159961A1 - 系统级封装及其制备方法 - Google Patents

系统级封装及其制备方法 Download PDF

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Publication number
WO2021159961A1
WO2021159961A1 PCT/CN2021/074090 CN2021074090W WO2021159961A1 WO 2021159961 A1 WO2021159961 A1 WO 2021159961A1 CN 2021074090 W CN2021074090 W CN 2021074090W WO 2021159961 A1 WO2021159961 A1 WO 2021159961A1
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Prior art keywords
rdl
electronic component
package
compound
electrically connected
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PCT/CN2021/074090
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English (en)
French (fr)
Inventor
叶润清
郭学平
佘勇
马富强
王惠娟
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华为技术有限公司
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Publication of WO2021159961A1 publication Critical patent/WO2021159961A1/zh

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Definitions

  • This application relates to semiconductor packaging, and more particularly to a system-in-package and a manufacturing method thereof.
  • the embodiments of the application provide a system-level packaging structure and a preparation method, which adopts wafer-level packaging or board-level packaging processes to realize system-level interconnection of active or passive devices in the system by using advanced semiconductor processes, that is, RDL semiconductor processes method. Therefore, it replaces the package substrate in the traditional package, reduces the thickness of the metal interconnection layer and the inter-metal dielectric layer between active or passive devices, and realizes the thinning of the package.
  • a system-in-package including: a first redistribution layer RDL; a first electronic component disposed on the front surface of the first RDL, and the first electronic component is electrically connected to the first RDL; The first compound arranged on the front surface of the first RDL, the first electronic component is encapsulated in the first compound; the second electronic component arranged on the back surface of the first RDL, the second electronic component is combined with The first RDL is electrically connected; a second compound disposed on the back of the first RDL, and the second electronic component is encapsulated in the second compound; wherein, the first electronic component is a bare chip or a passive device At least one of the second electronic components is a secondary packaged device. .
  • RDL is used as the system interconnection redistribution layer, and bare chips, secondary packaged devices or passive devices are integrated on the external interconnection side of RDL, thereby breaking through the restriction requirements on system devices, and through semiconductor Process RDL to replace the thicker package substrate to realize the internal interconnection of the system, which meets the product's device thickness requirements in the case of two-layer and above device distribution, and improves the 3D spatial integration in the system package.
  • the system-in-package further includes: a second RDL; and a first interconnection copper pillar disposed between the first RDL and the second RDL The first interconnecting copper pillar is used to electrically connect the first RDL and the second RDL.
  • more layers of packaging can be integrated to form a packaging structure of stacked packaging technology.
  • Another fan-out system in package structure can be integrated above the system in package of the first RDL structure.
  • it can also be a single electronic component packaging structure.
  • the integration level of the system-in-package can be better improved within the same footprint.
  • the system-in-package further includes: a third electronic component disposed on a surface of the second RDL away from the first RDL, and the third The electronic component is electrically connected to the second RDL; a third compound disposed on the surface of the second RDL away from the first RDL, and the third electronic component is encapsulated in the third compound.
  • electronic devices may be provided on the surface of the second RDL, and a fan-out method may be used, or a formal mounting, flip-chip or other process method may be used.
  • the system-in-package further includes: a packaging substrate; a second interconnecting copper pillar disposed between the first RDL and the packaging substrate, so The second interconnecting copper pillar is used to electrically connect the first RDL and the package substrate.
  • more layers of packaging can be integrated to form a packaging structure of stacked packaging technology.
  • the package substrate in the conventional technology can be provided above the system-in-package of the first RDL structure, and it can also be a package structure of a single electronic component.
  • the integration level of the system-in-package can be better improved within the same footprint.
  • the system-in-package further includes: a fourth electronic component disposed on a surface of the packaging substrate away from the first RDL, and the fourth electronic component The component is electrically connected to the packaging substrate; a fourth compound disposed on the surface of the packaging substrate away from the first RDL, and the fourth electronic component is encapsulated in the fourth compound.
  • electronic devices can be disposed on the basic surface of the package, and can adopt front mounting, flip mounting, or other process methods.
  • the system-in-package further includes: at least one copper core solder ball, one end of the copper core solder ball is electrically connected to the first RDL, and the other end is located at The outside of the system-in-package is used for electrical connection with an external circuit.
  • the copper core tin ball can be a tin ball with a copper core, and the copper core tin ball can maintain a certain height in the post-assembly process to prevent the BGA solder ball from collapsing during multiple reflow processes.
  • the second electronic component is disposed on the back of the first RDL by at least one of front-mounted, flip-chip, or SMT.
  • the first electronic component is disposed on the front side of the first RDL through a fan-out process.
  • the system-in-package further includes: a fifth electronic component electrically connected to the first RDL, and the fifth electronic component is a bare chip or a passive At least one of the devices.
  • passive devices or bare chips may also be provided on the back of the first RDL, which can effectively improve the integration of system-in-package.
  • a method for preparing a system-in-package including: preparing a carrier board, which is used to implement temporary mounting and position fixation of electronic components; The disk surface is mounted and fixed on the carrier board in a manner of facing down; the first electronic component is embedded in the first compound through a plastic packaging process; the carrier board is removed; The first RDL fanned out in the first compound device, and the first electronic component is electrically connected to the first RDL; on the surface of the first RDL where the second electronic component or the fifth electronic component will be mounted Processing; mount the second electronic component or the fifth electronic component on the surface of the first RDL, and the second electronic component or the fifth electronic component is electrically connected to the first RDL; The plastic encapsulation process embeds the second electronic component or the fifth electronic component in the second compound; interconnects the input and output I/O outside the fan-out surface through the molded through-hole TMV or solder ball processing for The external circuit is electrically connected.
  • the method further includes: Copper pillars are planted on the surface of the first RDL.
  • the method further includes: The surface of the first RDL is electroplated with conductive pillars.
  • the method further includes: The copper pillars or the conductive pillars embedded in the second compound are exposed through a thinning process.
  • Fig. 1 is a schematic diagram of an electronic device provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a system-in-package provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another system-in-package provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another system-in-package provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of yet another system-in-package provided by an embodiment of the present application.
  • Fig. 6 is a schematic diagram of the system-in-package provided by an embodiment of the present application integrated in an electronic device.
  • FIG. 7 to FIG. 17 are schematic diagrams of a method for preparing a system-in-package according to an embodiment of the present application.
  • the electronic device in the embodiment of the present application may be a mobile phone, a tablet computer, a notebook computer, a smart bracelet, a smart watch, a smart helmet, a smart glasses, and the like.
  • the electronic device can also be a cellular phone, a cordless phone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA), with wireless communication Functional handheld devices, computing devices, or other processing devices connected to wireless modems, in-vehicle devices, electronic devices in 5G networks, or electronic devices in the public land mobile network (PLMN) that will evolve in the future.
  • SIP session initiation protocol
  • WLL wireless local loop
  • PDA personal digital assistant
  • the application embodiment does not limit this.
  • FIG. 1 is a schematic diagram of an electronic device provided by an embodiment of the present application.
  • the electronic device is a mobile phone for description.
  • the electronic device has a cube-like shape, which can include a frame 10 and a display screen 20. Both the frame 10 and the display screen 20 can be installed on the middle frame (not shown in the figure), and the frame 10 can be divided into upper frames.
  • the frame, the bottom frame, the left frame, and the right frame are connected to each other, and a certain arc or chamfer can be formed at the joint.
  • Electronic equipment also includes a printed circuit board (PCB) installed inside.
  • PCB printed circuit board
  • Electronic components can be installed on the PCB.
  • the electronic components can include capacitors, inductors, resistors, processors, cameras, flashes, microphones, batteries, etc., but not Limited to this.
  • the frame 10 may be a metal frame, such as metals such as copper, magnesium alloy, stainless steel, etc., or a plastic frame, a glass frame, a ceramic frame, etc., or a frame that combines metal and plastic.
  • the traditional fan-out package is integrated on the external interconnection side of the redistribution layer (RDL). More devices in the integrated system receive a limited angle.
  • the packaging form and thickness of the integrated device are more limited in the placement of integrated devices.
  • the double-sided The packaging structure is also unable to integrate multi-layer packaging to achieve three-dimensional integration due to the limitations of the substrate technology based on the line width and line spacing of the packaging substrate technology, the thickness of the dielectric layer, and the number of interconnection lines.
  • This application provides a system-in-package (system-in-package, SIP) structure and preparation method, which adopts wafer-level packaging or board-level packaging processes to realize system-level systems for active or passive devices in the system using advanced semiconductor processes.
  • Interconnect the semiconductor process method of RDL. Therefore, it replaces the package substrate in the traditional package, reduces the thickness of the metal interconnection layer and the inter-metal dielectric layer between active or passive devices, and realizes the thinning of the package.
  • this application integrates the traditional surface mounted technology (SMT), wire bonding and flip chip packaging processes, and directly integrates active or passive devices into the RDL of the package fan-out
  • SMT surface mounted technology
  • wire bonding and flip chip packaging processes directly integrates active or passive devices into the RDL of the package fan-out
  • the fan-out RDL double-sided packaging is realized, which improves the integration of the entire SIP package and meets the requirements for high integration and thinness of devices in electronic equipment such as earphones or mobile phones.
  • FIG. 2 is a schematic structural diagram of a system-in-package provided by an embodiment of the present application.
  • the system-in-package 100 may include: a first RDL 110, a first electronic component 120 and a second electronic component 130.
  • the first electronic component 120 may be at least one of a bare chip or a passive device
  • the second electronic component 130 is a secondary packaged device. It can solve the scenario where the device cannot be opened based on the bare electronic component package in the system package.
  • the first electronic component 120 may be arranged on the front surface of the first RDL 110 and electrically connected to the first RDL 110.
  • the first electronic component 120 may be encapsulated on the front surface of the first RDL 110 by the first compound 140.
  • the second electronic component 130 may be disposed on the back of the first RDL 110 and electrically connected to the first RDL 110.
  • the second electronic component 130 may be encapsulated on the back surface of the first RDL 110 by the second compound 150.
  • front and back of the first RDL 110 are merely relative concepts, and the present application does not limit the specific positions of the front and back of the first RDL 110.
  • the system-in-package 100 may further include a fifth electronic component 160.
  • the fifth electronic component 160 may be at least one of a bare chip or a passive device. connect.
  • the fifth electronic component 160 is disposed on the back of the first RDL 110 and can be encapsulated on the back of the first RDL 110 by the second compound 150.
  • the first RDL 110 includes an insulating layer 111, a circuit layer 112 and an interconnection hole 113.
  • the first electronic component 120, the second electronic component 130, and the fifth electronic component 160 may be electrically connected to the circuit layer 112, and the interconnection hole 113 may be electrically connected to each circuit layer 112.
  • the first electronic component 120 may include a plurality of dies and passive devices, the lateral sides of which are encapsulated in the first compound 140, and the first compound 140 is also formed at the highest Above the upper surface of an electronic component 120, the first compound 140 may not be required to cover the upper surface of the highest first electronic component 120.
  • the first compound 140 may include a thermosetting cross-linked resin, for example, an epoxy molding compound (EMC).
  • EMC epoxy molding compound
  • the second compound 150 may be a thermosetting crosslinked resin similar to the first compound 140, for example, EMC.
  • the first electronic component 120 may be a die, for example, it may be a logic component, a memory, or other die.
  • the first electronic component 120 may also be a passive device, such as a capacitive device, an inductance device, a resistance device or other passive devices.
  • the second electronic component 130 may be a packaged logic component, a memory, or other secondary packaged devices.
  • the fifth electronic component 160 may be a die, for example, it may be a logic component, a memory, or other die.
  • the fifth electronic component 160 may also be a passive device, such as a capacitive device, an inductance device, a resistance device or other passive devices.
  • the fifth electronic component 160 when the fifth electronic component 160 is a bare chip, the bare chip located on the back of the system-in-package 100 may be fixed on the first RDL 110 by a patch adhesive 161.
  • the fifth electronic component 160 may be electrically connected to the first RDL 110 through the interconnect bonding wire 162.
  • One end of the interconnect bonding wire 162 is electrically connected to the die pad 163 of the fifth electronic component 160, and the other end is electrically connected to the first RDL 110.
  • the passive device located on the back of the system-in-package 100 may be fixed on the first RDL 110 by solder 164 and be electrically connected to the first RDL 110.
  • the second electronic component 130 located on the back of the system-in-package 100 may be fixed on the first RDL 110 through solder balls 131 to achieve electrical connection with the first RDL 110.
  • both the front and back sides of the fan-out first RDL integrate active and passive devices.
  • the electronic components arranged on the front side can fan out their pins through advanced wafer or board-level packaging processes, and fan out the pins of the electronic components and devices through the interconnect holes and lines of the first RDL.
  • the first RDL of the fan-out package is used to fabricate the interconnection copper pillar 170 or realize the interconnection copper pillar embedded in the EMC by welding the copper pillar.
  • interconnection copper pillar 170 directly embedded in the EMC
  • the other is after the plastic molding compound above the external interconnection pad is removed by laser.
  • a solder ball 180 of a ball grid array (BGA) package is planted on the pad.
  • BGA ball grid array
  • one end of the interconnecting copper pillar 170 or the solder ball 180 is electrically connected to the first RDL, and the other end is used to electrically connect to an external circuit.
  • the solder ball 180 may be an ordinary tin ball, and the material component may be a lead-free tin-silver-copper (SnAgCu) alloy tin material, such as SAC305.
  • the solder ball 180 may also be a solder ball with a copper core, and the copper core solder ball can maintain a certain height in the post-assembly process to avoid the collapse of the BGA solder ball during multiple reflow processes.
  • the interconnection copper pillar 170 or the solder ball 180 may be arranged on the front or back of the first RDL 110. If the system-in-package 100 includes a multilayer RDL structure, the interconnection copper pillar 170 or the solder ball 180 may also be arranged near the outside. This application does not restrict the front or back of the RDL.
  • the electronic components that are packaged through the fan-out process involved in this application may be application processors (application processors, AP), power management chips (power management units, PMU), and matching passive components. Bare chips and passive devices such as resistors, capacitors and inductors, as well as radio frequency chips, passive devices, audio codecs and other devices that are mounted or flipped, as well as other active chips and passive devices in the upper fan-out package.
  • the PMU is the power chip that supplies power to the AP and surrounding devices.
  • the AP is the processor of the entire system. It will integrate processors such as baseband and audio.
  • This application uses RDL as the system interconnection redistribution layer, and integrates bare chips, secondary packaged devices or passive devices on the external interconnection side of RDL, thus breaking through the restriction requirements on system devices, and processing RDL through semiconductor technology It replaces the thicker package substrate to realize the internal interconnection of the system, satisfies the product thickness requirements of the device in the case of two-layer and above device distribution, and improves the 3D spatial integration in the system package.
  • the embodiments of the present application may also be applied to the case where the front and back sides of the first RDL only include dies.
  • the dies and passive devices can be fan-out on the front side of the first RDL, and the dies and passive devices provided on the back side of the first RDL can be fixed by processes such as front mounting, flip mounting, and SMT.
  • FIG. 4 is a schematic structural diagram of another system-in-package provided by an embodiment of the present application.
  • more layers of packaging can be integrated to form a package on package (PoP) packaging structure.
  • PoP package on package
  • another fan-out SIP package structure can be integrated above the system-in-package shown in FIG. 2.
  • it can also be a single electronic component packaging structure.
  • the system-in-package 100 may include a second RDL 210.
  • the second RDL 210 may be electrically connected through the first interconnecting copper pillar 220 disposed between the first RDL 110 and the second RDL 210.
  • the system-level package 100 may further include a third electronic component 230 disposed on a surface of the second RDL away from the first RDL and a third compound 240 disposed on a surface of the second RDL away from the first RDL.
  • the third electronic component 230 is electrically connected to the second RDL 210, and the third electronic component 230 may be encapsulated in the third compound 240.
  • the third electronic component 230 may be a die, which is fan-out on the surface of the second RDL away from the first RDL.
  • the third electronic component 230 may also be a secondary packaged device, and it may be disposed on the surface of the second RDL away from the first RDL through processes such as front mounting, flip-chip mounting, and SMT.
  • the third electronic component 230 may also be a passive device, and may be disposed on the surface of the second RDL away from the first RDL through a process such as welding.
  • the third compound 240 may be a thermosetting crosslinked resin similar to the first compound 140, for example, EMC.
  • FIG. 5 is a schematic structural diagram of yet another system-in-package provided by an embodiment of the present application.
  • more layers of packaging can be integrated to form a PoP packaging structure.
  • the package substrate in the conventional technology can be provided above the system-in-package shown in FIG.
  • the system in package 100 may include a package substrate 310.
  • the packaging substrate 310 may be electrically connected to the first RDL 110 through a second interconnecting copper pillar 320 disposed between the first RDL 110 and the packaging substrate.
  • the system in package 100 may further include a fourth electronic component 330 disposed on a surface of the packaging substrate 310 away from the first RDL and a fourth compound 340 disposed on a surface of the packaging substrate 310 away from the first RDL.
  • the fourth electronic element 330 is electrically connected to the packaging substrate 310, and the fourth electronic element 330 may be encapsulated in the fourth compound 340.
  • the fourth electronic component 330 may be a bare chip or a secondary packaged device, and may be disposed on the surface of the package substrate 310 away from the first RDL through processes such as front mounting, flip-chip mounting, and SMT.
  • the fourth electronic component 330 may also be a passive device, and it may be arranged on the surface of the second RDL away from the first RDL through a process such as welding.
  • the fourth compound 340 may be a thermosetting crosslinked resin similar to the first compound 140, for example, EMC.
  • Fig. 6 is a schematic diagram of the system-in-package provided by an embodiment of the present application integrated in an electronic device.
  • the system-in-package can be integrated as an independent system on the motherboard of electronic equipment, such as mobile phones, headsets, wearables, etc., and interconnect and interact with peripheral devices on the motherboard to achieve specific functions.
  • the system-in-package 100 can be disposed on the PCB 410 of the electronic device through the solder balls 180, so that it can be electrically connected with other devices on the PCB 410.
  • RDL system interconnection redistribution layer
  • RDL is processed by semiconductor technology to replace thicker packaging substrates to achieve internal interconnection of the system, which meets the requirements of product thickness for devices in the case of more than 2 layers of device distribution, and improves the 3D spatial integration in system packaging.
  • FIG. 7 to FIG. 17 are schematic diagrams of a method for preparing a system-in-package according to an embodiment of the present application.
  • the first electronic component is a bare chip and the second electronic component is a secondary packaged device as an example for description.
  • the preparation process is a two-layer system-in-package. According to this method, the number of integrated layers and complexity can be increased, which is not limited in this application.
  • a carrier board which can be metal, silicon wafer, or organic plate.
  • a layer of adhesive temporary bonding glue or glue film is combined on the carrier board, which can realize the temporary mounting and position fixation of electronic components or devices, and avoid position deviation during the subsequent plastic packaging process.
  • the pads (pads) drawn out of the fan-out first electronic component are mounted on the carrier board with the face down by the mounting device.
  • the first electronic component mounted on the carrier board is embedded in the first compound through the plastic packaging process equipment, thereby forming a whole with a certain rigidity and a fixed position of the device.
  • the whole embedded in the first compound is separated from the carrier plate through the process of unbonding, and the residual glue temporarily bonded through the process of dry method (plasma) or chemical wet method Clean up.
  • the production of the circuit that is embedded in the first compound device and fan-out is realized by a semiconductor or liquid crystal display (LCD) process method.
  • LCD liquid crystal display
  • S508 Mount the positive-mounted electronic components on the first RDL layer and realize interconnection.
  • the first RDL is to dispense glue at the position where the electronic components are mounted on the first RDL, the electronic components are mounted on the first RDL through the placement machine, and the electrical connection between the electronic components and the first RDL is realized through a wire bonding process.
  • the upper device is plastic-encapsulated.
  • the device above the first RDL is plastic-encapsulated inside the second compound in the plastic packaging equipment, and all the copper pillars and devices are wrapped.
  • the upper layer is plastic-encapsulated and thinned to expose the interconnection copper pillars.
  • the copper pillars embedded in the second compound are exposed through the thinning process, and the interconnection with the upper package body can be realized by interconnecting the copper pillars.
  • the fan-out surface externally interconnects the input/output (I/O) through a through molding via (TMV) and performs solder ball processing.
  • I/O input/output
  • TMV through molding via
  • the side of the electronic component can be fanned out by laser processing to clean the compound on the reserved pad, and then the exposed pad Mount the solder ball that meets a certain thickness requirement, and the height of the solder ball needs to meet the needs of welding the entire system package to a single board.
  • a certain thickness of dry film can be mounted and a copper pillar with a certain height can be processed through the process flow of exposure, development, electroplating, leg film, etc., to realize the mutual interaction between the lower fan-out electronic components and the package on the device. even.
  • the disclosed system, device, and method can be implemented in other ways.
  • the device embodiments described above are merely illustrative, for example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical or other forms.

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Abstract

本申请实施例提供了一种系统级封装及制备方法。其中，所述系统级封装包括：第一重布线层RDL；设置在所述第一RDL正面的第一电子元件，所述第一电子元件与所述第一RDL电连接；设置在所述第一RDL正面的第一化合物，所述第一电子元件包封在所述第一化合物中；设置在所述第一RDL背面的第二电子元件，所述第二电子元件与所述第一RDL电连接；设置在所述第一RDL背面的第二化合物，所述第二电子元件包封在第二化合物中；其中，所述第一电子元件为裸片或无源器件中的至少一种，所述第二电子元件为二次封装的器件。

Description

系统级封装及其制备方法
本申请要求于2020年2月14日提交中国专利局、申请号为202010091890.7、申请名称为“系统级封装及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体封装，尤其涉及一种系统级封装及其制备方法。
背景技术
随着电子设备的发展，在架构和功能上一直在走加法，集成功能越来越多，但是作为面向用户的产品，外形尺寸导致内部空间受限，对电子元件尺寸和厚度要求越来越高。系统级封装技术使电子元件的集成度越来越高，将电子元件在架构上由2D空间往3D空间的堆叠架构延伸。但是在实现了平面上更高的集成度的同时，电子元件在厚度上也受到限制，所以要求解决在三维空间的体积上集成度是未来先进封装技术的发展方向。
发明内容
本申请实施例提供一种系统级封装结构及制备方法，采用晶圆级封装或板级封装工艺将系统中有源或无源器件采用先进的半导体工艺实现系统级互连，即RDL的半导体工艺方法。从而替代传统封装中的封装基板，使有源或无源器件之间金属互连层以及金属层间介质层厚度降低，实现封装薄型化。
第一方面，提供了一种系统级封装，包括：第一重布线层RDL；设置在所述第一RDL正面的第一电子元件，所述第一电子元件与所述第一RDL电连接；设置在所述第一RDL正面的第一化合物，所述第一电子元件包封在所述第一化合物中；设置在所述第一RDL背面的第二电子元件，所述第二电子元件与所述第一RDL电连接；设置在所述第一RDL背面的第二化合物，所述第二电子元件包封在第二化合物中；其中，所述第一电子元件为裸片或无源器件中的至少一种，所述第二电子元件为二次封装的器件。。
根据本申请实施例，采用RDL作为系统互连再分布层，并在RDL的外界互连侧集成裸片，二次封装的器件或无源器件，从而突破了对系统器件限制要求，且通过半导体工艺加工RDL来替代较厚的封装基板实现系统内部互连，满足了2层及以上器件分布情况下产品对器件厚度要求，提高了系统封装中3D空间集成度。
结合第一方面，在第一方面的某些实现方式中，所述系统级封装还包括：第二RDL；设置在所述第一RDL与所述第二RDL之间的第一互连铜柱，所述第一互连铜柱用于使所述第一RDL与所述第二RDL之间电连接。
根据本申请实施例，可以集成更多层封装从而形成叠层封装技术的封装结构。可以在第一RDL结构的系统级封装上方集成另外一个扇出型系统级封装结构。同样的，也可以为单电子元件的封装结构。可以在相同的占地面积内，更好的提升所述系统级封装的集成 度。
结合第一方面，在第一方面的某些实现方式中，所述系统级封装还包括：设置在所述第二RDL的远离所述第一RDL的面的第三电子元件，所述第三电子元件与所述第二RDL电连接；设置在所述第二RDL的远离所述第一RDL的面的第三化合物，所述第三电子元件包封在所述第三化合物中。
根据本申请实施例，可以在第二RDL表面设置电子器件，可以采用扇出的方式，也可以采用正装，倒装或其他工艺方式。
结合第一方面，在第一方面的某些实现方式中，所述系统级封装还包括：封装基板；设置在所述第一RDL与所述封装基板之间的第二互连铜柱，所述第二互连铜柱用于使所述第一RDL与所述封装基板之间电连接。
根据本申请实施例，可以集成更多层封装从而形成叠层封装技术的封装结构。可以在第一RDL结构的系统级封装上方设置传统技术中的封装基板同样的，也可以为单电子元件的封装结构。可以在相同的占地面积内，更好的提升所述系统级封装的集成度。
结合第一方面，在第一方面的某些实现方式中，所述系统级封装还包括：设置在所述封装基板的远离所述第一RDL的面的第四电子元件，所述第四电子元件与所述封装基板电连接；设置在所述封装基板的远离所述第一RDL的面的第四化合物，所述第四电子元件包封在所述第四化合物中。
根据本申请实施例，可以在封装基本表面设置电子器件，可以采用正装，倒装或其他工艺方式。
结合第一方面，在第一方面的某些实现方式中，所述系统级封装还包括：至少一个铜核锡球，所述铜核锡球一端与所述第一RDL电连接，另一端位于所述系统级封装外侧，用于与外部电路电连接。
根据本申请实施例，铜核锡球可以为具有铜核的锡球，铜核锡球可以在后组装工艺中保持一定高度，避免多次回流过程中BGA焊球塌陷。
结合第一方面，在第一方面的某些实现方式中，所述第二电子元件通过正装、倒装或SMT中的至少一种方式设置在第一RDL背面。
结合第一方面，在第一方面的某些实现方式中，所述第一电子元件通过扇出工艺设置在第一RDL正面。
结合第一方面，在第一方面的某些实现方式中，所述系统级封装还包括：第五电子元件，与所述第一RDL电连接，所述第五电子元件为裸片或无源器件中的至少一种。
根据本申请实施例，第一RDL背面也可以设置无源器件或裸片，可以有效提升系统级封装的集成度。
第二方面，提供了一种制备系统级封装的方法，包括：准备承载板，所述承载板用于实现电子元件的临时贴装及位置固定；将扇出的第一电子元件以外引出的焊盘面朝下的方式贴装固定在所述承载板上；通过塑封工艺将所述第一电子元件埋置在第一化合物中；拆除所述承载板；通过半导体或液晶LCD的工艺方法制作嵌入到第一化合物器件中向外扇出的第一RDL，所述第一电子元件与所述第一RDL电连接；在将要贴装第二电子元件或第五电子元件的所述第一RDL的表面进行处理；在所述第一RDL的表面贴装所述第二电子元件或所述第五电子元件，所述第二电子元件或所述第五电子元件与所述第一RDL电连接；通过塑封工艺将所述第二电子元件或所述第五电子元件埋置在第二化合物中；在扇 出面外部互连输入输出I/O穿透模塑通孔TMV或焊球加工，用于与外部电路电连接。
结合第二方面，在第二方面的某些实现方式中，所述在将要贴装第二电子元件或第五电子元件的所述第一RDL的表面进行处理之后，所述方法还包括：在所述第一RDL的表面植铜柱。
结合第二方面，在第二方面的某些实现方式中，所述在将要贴装第二电子元件或第五电子元件的所述第一RDL的表面进行处理之后，所述方法还包括：在所述第一RDL的表面电镀导电柱。
结合第二方面，在第二方面的某些实现方式中，所述通过塑封工艺将所述第二电子元件或所述第五电子元件埋置在第二化合物中之后，所述方法还包括：通过减薄工艺将嵌埋在第二化合物内的所述铜柱或所述导电柱露出来。
附图说明
图1是本申请实施例提供的电子设备的示意图。
图2是本申请实施例提供的一种系统级封装的结构示意图。
图3是本申请实施例提供的另一种系统级封装的结构示意图。
图4是本申请实施例提供的另一种系统级封装的结构示意图。
图5是本申请实施例提供的又一种系统级封装的结构示意图。
图6是本申请实施例提供的系统级封装集成在电子设备中的示意图。
图7至图17是本申请实施例提供系统级封装的制备方法的示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
本申请实施例中的电子设备可以是手机、平板电脑、笔记本电脑、智能手环、智能手表、智能头盔、智能眼镜等。电子设备还可以是蜂窝电话、无绳电话、会话启动协议(session initiation protocol，SIP)电话、无线本地环路(wireless local loop，WLL)站、个人数字助手(personal digital assistant，PDA)、具有无线通信功能的手持设备、计算设备或连接到无线调制解调器的其它处理设备、车载设备，5G网络中的电子设备或者未来演进的公用陆地移动通信网络(public land mobile network，PLMN)中的电子设备等，本申请实施例对此并不限定。
图1是本申请实施例提供的电子设备的示意图，在此，以电子设备为手机进行说明。
如图1所示，电子设备具有类似立方体的形状，可以包括边框10和显示屏20，边框10和显示屏20均可以安装在中框上(图中未示出)，边框10可以分为上边框、下边框、左边框、右边框，这些边框相互连接，在连接处可以形成一定的弧度或倒角。
电子设备还包括设置于内部的印刷电路板(printed circuit board，PCB)，PCB上可以设置电子元件，电子元件可以包括电容、电感、电阻、处理器、摄像头、闪光灯、麦克风、电池等，但不限于此。
边框10可以是为金属边框，比如铜、镁合金、不锈钢等金属，也可以是塑胶边框、玻璃边框、陶瓷边框等，也可以是金属与塑料结合的边框。
传统的扇出型封装在重布线层(redistribution layer，RDL)的外界互连侧集成系统更多的器件收到限制角度，在贴装集成器件的封装形式以及厚度受限较大，另外双面封装结 构形式由于基于基板技术受制于封装基板技术的线宽线距、介质层厚度、互连线层数等限制同样无法集成多层封装实现三维空间上集成。
本申请提供了一种系统级封装(system-in-package，SIP)结构及制备方法，采用晶圆级封装或板级封装工艺将系统中有源或无源器件采用先进的半导体工艺实现系统级互连，即RDL的半导体工艺方法。从而替代传统封装中的封装基板，使有源或无源器件之间金属互连层以及金属层间介质层厚度降低，实现封装薄型化。同时本申请融合了传统的表面组装技术(surface mounted technology，SMT)、压焊(wire bonding)及倒装芯片(flip chip)的封装工艺，将有源或无源器件直接集成封装扇出的RDL层上，实现扇出RDL的双面封装，提高了整个SIP封装集成度，满足耳机或手机等电子设备中对器件集成度高且较薄的需求。
图2是本申请实施例提供的一种系统级封装的结构示意图。
如图2所示，系统级封装100可以包括：第一RDL110，第一电子元件120和第二电子元件130。第一电子元件120可以为裸片或无源器件中的至少一种，第二电子元件130为二次封装的器件。可以解决在系统封装中器件无法打开基于裸电子元件封装的场景。
其中，第一电子元件120可以设置在第一RDL110的正面并与第一RDL110电连接。第一电子元件120可以被第一化合物140包封在第一RDL110的正面。第二电子元件130可以设置在第一RDL110的背面并与第一RDL110电连接。第二电子元件130可以被第二化合物150包封在第一RDL110的背面。
应理解，第一RDL110的正面和背面仅作为相对的概念，本申请并不限制第一RDL110的正面和背面的具体位置。
可选地，系统级封装100还可以包括第五电子元件160，第五电子元件160可以为裸片或无源器件中的至少一种，可以设置在第一RDL110的背面，与第一RDL110电连接。第五电子元件160设置在第一RDL110的背面，则可以被第二化合物150包封在第一RDL110的背面。
可选地，第一RDL110包括绝缘层111，线路层112和互连孔113。其中，第一电子元件120，第二电子元件130和第五电子元件160可以与线路层112电连接，互连孔113可以与各个线路层112电连接。
应理解，包封可使用合适的技术诸如但不限于传递模制、压缩模制和层压来完成。如本申请所使用的，"包封的"不要求所有表面被包封在模制化合物内。在图2所示的实施方案中，第一电子元件120可以包括多个裸片和无源器件，其横向侧被包封在第一化合物140中，并且第一化合物140也被形成在最高第一电子元件120的上表面的上方，也可以不需要第一化合物140覆盖最高的第一电子元件120的上表面。
可选地，第一化合物140可包括热固性交联树脂，例如，环氧树脂注塑化合物(epoxy molding compound，EMC)。
可选地，第二化合物150可以是与第一化合物140类似的热固性交联树脂，例如，EMC。
可选地，第一电子元件120可以是裸片，例如，可以是逻辑部件、存储器、或其他裸片。第一电子元件120也可以是无源器件，如电容器件，电感器件，电阻器件或其他无源器件。
可选地，第二电子元件130可以是封装过的逻辑部件、存储器或其他二次封装的器件。
可选地，第五电子元件160可以是裸片，例如，可以是逻辑部件、存储器、或其他裸片。第五电子元件160也可以是无源器件，如电容器件，电感器件，电阻器件或其他无源器件。
可选地，当第五电子元件160为裸片时，位于系统级封装100背面的裸片可以通过贴片胶161固定在第一RDL110上。第五电子元件160可以通过互连焊线162实现与第一RDL110的电连接。互连焊线162一端与第五电子元件160的芯片焊盘163电连接，另一端与第一RDL110电连接。
可选地，当第五电子元件160为无源器件时，位于系统级封装100背面的无源器件可以通过焊料164固定在第一RDL110上并实现与第一RDL110的电连接。
可选地，位于系统级封装100背面的第二电子元件130可以通过焊球131固定在第一RDL110上并实现与第一RDL110的电连接。
在本申请实施例中扇出型的第一RDL的正面和背面均集成有源及无源器件。正面设置的电子元件可以通过晶圆或板级封装先进工艺实现其管脚扇出，通过第一RDL的互连孔及线路实现电子元件及器件管脚的扇出。然后在此扇出型封装的第一RDL进行互连铜柱170的制作或通过焊接植铜柱的方式实现内嵌到EMC内互连铜柱。同时，在第一RDL背面通过正装、倒装及SMT等工艺方式集成更多与扇出器件互连的电子元件，并且表贴到第一RDL上的器件通过塑封(molding)工艺嵌入到EMC内，在形成结构的两面均可以和外界实现互连。
在本实施例中列举了其中两种典型的互连方式，一种是直接嵌入到EMC内的互连铜柱170，另外一种是通过激光方式将外界互连焊盘上方的塑封料清除后在焊盘上面植球栅阵列封装(ball grid array，BGA)的焊球180。
可选地，互连铜柱170或焊球180的一端与第一RDL电连接，另一端用于与外部电路电连接。
可选地，焊球180可以为普通的锡球，材料组份可以为无铅的锡银铜(SnAgCu)合金锡料，如SAC305等。焊球180也可以为具有铜核的锡球，铜核锡球可以在后组装工艺中保持一定高度，避免多次回流过程中BGA焊球塌陷。
应理解，互连铜柱170或焊球180可以设置在第一RDL110的正面或背面，若系统级封装100包括多层RDL结构，则互连铜柱170或焊球180也可以设置在靠近外侧的RDL的正面或背面，本申请对此并不做限制。
应理解，以耳机的场景为例，在本申请中涉及到通过扇出工艺封装的电子元件可以是应用处理器(application processor，AP)、电源管理芯片(power management unit，PMU)、匹配无源电阻电容电感等裸芯片及无源器件，以及正装或倒装的射频芯片、无源器件、音频编译码器(codec)等器件，还有上层扇出型封装其他有源芯片及无源器件。其中PMU为AP以及周围器件进行供电的电源芯片，AP是整个系统的处理器，将集成有基带及音频等处理器，另外还有已经完成封装或基于裸芯片存储芯片等，同样还有和芯片信号处理或匹配电路上的无源电阻、电容及电感器件。在整个系统中还包含射频相关蓝牙、WIFI及通信相关的射频器件。同样也可能包含晶振、功率放大器、滤波器等器件。
本申请采用RDL作为系统互连再分布层，并在RDL的外界互连侧集成裸片，二次封装的器件或无源器件，从而突破了对系统器件限制要求，且通过半导体工艺加工RDL来替代较厚的封装基板实现系统内部互连，满足了2层及以上器件分布情况下产品对器件厚 度要求，提高了系统封装中3D空间集成度。
应理解，本申请实施例还可以应用于第一RDL的正反两面仅包括裸片的情况。如图3所示，裸片和无源器件可以扇出在第一RDL的正面，设置在第一RDL的背面的裸片和无源器件可以通过正装、倒装及SMT等工艺方式固定。
图4是本申请实施例提供的另一种系统级封装的结构示意图。
本申请实施例中可以集成更多层封装从而形成叠层封装技术(package on package，PoP)的封装结构。如图4所示，可以在图2所示的系统级封装上方集成另外一个扇出型SIP封装结构。同样的，也可以为单电子元件的封装结构。
可选地，系统级封装100可以包括第二RDL210。其中，第二RDL210可以通过设置在第一RDL110与第二RDL210之间的第一互连铜柱220实现电连接。
可选地，统级封装100还可以包括设置在第二RDL的远离第一RDL的面的第三电子元件230和设置在第二RDL的远离第一RDL的面的第三化合物240。其中，第三电子元件230与第二RDL210电连接，第三电子元件230可以包封在第三化合物240中。
可选地，第三电子元件230可以是裸片，扇出在第二RDL的远离第一RDL的面上。第三电子元件230也可以是二次封装的器件，可以通过正装、倒装及SMT等工艺方式设置在第二RDL的远离第一RDL的面上。第三电子元件230也可以是无源器件，可以通过焊接等工艺方式设置在第二RDL的远离第一RDL的面上。
可选地，第三化合物240可以是与第一化合物140类似的热固性交联树脂，例如，EMC。
图5是本申请实施例提供的又一种系统级封装的结构示意图。
本申请实施例中可以集成更多层封装从而形成PoP的封装结构。如图5所示，可以在图2所示的系统级封装上方设置传统技术中的封装基板同样的，也可以为单电子元件的封装结构。
可选地，系统级封装100可以包括封装基板310。其中，封装基板310可以通过设置在第一RDL110与封装基板之间的第二互连铜柱320与第一RDL110实现电连接。
可选地，系统级封装100还可以包括设置在封装基板310的远离第一RDL的面的第四电子元件330和设置在封装基板310不与的远离第一RDL的面的第四化合物340。其中，第四电子元件330与封装基板310电连接，第四电子元件330可以包封在第四化合物340中。
可选地，第四电子元件330可以是裸片，也可以是二次封装的器件，可以通过正装、倒装及SMT等工艺方式设置在封装基板310的远离第一RDL的面上。第四电子元件330也可以是无源器件，可以通过焊接等工艺方式设置在第二RDL的远离第一RDL的面上。
可选地，第四化合物340可以是与第一化合物140类似的热固性交联树脂，例如，EMC。
图6是本申请实施例提供的系统级封装集成在电子设备中的示意图。
系统级封装可以作为独立系统集成在电子设备，如手机、耳机、可穿戴等产品主板上，和主板上外围器件形成互连和互动实现其特定功能。如图6所示，系统级封装100可以通过焊球180设置在电子设备的PCB410上，从而可以与PCB410上的其它器件电连接。
应理解，本申请采用RDL作为系统互连再分布层，并在RDL的外界互连侧集成任何类型器件，从而突破了对系统器件限制要求。且通过半导体工艺加工RDL来替代较厚的 封装基板实现系统内部互连，满足了2层以上器件分布情况下产品对器件厚度要求，提高了系统封装中3D空间集成度。
图7至图17是本申请实施例提供系统级封装的制备方法的示意图。
应理解，为简要说明，以第一电子元件为裸片，第二电子元件为二次封装的器件为例进行说明。制备流程为两层结构的系统级封装，可以根据此方法，增加集成的层数及复杂度，本申请对此并不做限制。
S501，承载板准备。
如图7所示，为了能够更好实现电子元件或器件的扇出，借助于一个承载板，该承载板可以为金属、硅晶圆同样也可以为有机板材。在此承载板上结合一层具有粘性的临时结合(bonding)胶或胶膜，能够实现电子元件或器件临时贴装及位置固定，避免在后面塑封工艺过程中发生位置偏移。
S502，贴装扇出性电子元件及器件。
如图8所示，通过贴片设备将扇出的第一电子元件以外引出的焊盘(pad)面朝下的方式贴装固定在承载板上。
S503，封装扇出电子元件。
如图9所示，通过塑封工艺设备将贴装到承载板上的第一电子元件埋置在第一化合物中，从而形成具有一定刚性且器件位置固定的整体。
S504，拆键合承载板。
如图10所示，将内嵌在第一化合物内的整体通过拆键合的工艺实现和承载板进行拆分，并且通过干法(plasma)或化学湿法的工艺将临时键合的残胶清理干净。
S505，加工扇出第一RDL。
如图11所示，通过半导体或液晶(liquid crystal display，LCD)的工艺方法实现嵌入到第一化合物器件中向外扇出的线路的制作。
S506，第一RDL表面处理。
如图12所示，在实现第一RDL线路最终成形后，在贴装第二电子元件或第五电子元件的位置进行表面处理，一方面为了增加第一RDL焊盘与焊锡之间的可焊性的同时也可以实现对第一RDL的表面防氧化。
S507，第一RDL植铜柱和倒装及SMT器件。
如图13所示，在同层上如存在倒装器件、无源器件以及正装的电子元件时，可以先进行倒装及SMT器件的贴装和植铜柱，并对整个圆片或方片进行助焊剂的清洗。
S508，第一RDL层上贴装正贴电子元件并实现互连。
如图14所示，然后进行正装电子元件贴装及互连。首先在第一RDL贴装电子元件的位置进行点胶，通过贴片机将电子元件贴装到第一RDL上，并通过wire bonding的工艺方式实现电子元件和第一RDL之间电连接。
S509，上层器件塑封。
如图15所示，在塑封设备中将第一RDL上方器件塑封在第二化合物内部，并且实现铜柱、器件的全部包裹。
S510，上层塑封的减薄露出互连铜柱。
如图16所示，通过减薄工艺将嵌埋在第二化合物内的铜柱露出来，可以通过互连铜柱实现与上方封装体之间的互连。
S511，扇出面外部互连输入输出(input/output，I/O)穿透模塑通孔(through molding via，TMV)并进行焊球加工。
如图17所示，在完成上面的器件工艺及包裹器件的化合物减薄工艺后再扇出电子元件的一面可以通过激光加工方式在预留的焊盘上将化合物清理，并在露出的焊盘上植满足一定厚度要求焊球，该焊球高度需满足能够满足整个系统封装焊接到单板上的需求。
应理解，如果第一RDL面没有无源器件的集成，只有倒装或wire bonding的电子元件的情况下可以采用另外一种互连铜柱制作方法。
在完成第一RDL的加工后，在第一RDL上直接电镀导电柱，如铜柱，代替上面的植铜柱，具体操作为：
在第一RDL加工完成后可以通过贴装一定厚度干膜并通过曝光、显影、电镀、腿膜等工艺流程加工具有一定高度铜柱，实现下层扇出电子元件及器件上面封装体之间的互连。
本领域技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性或其它的形式。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种系统级封装，其特征在于，包括：
    第一重布线层RDL；
    设置在所述第一RDL正面的第一电子元件，所述第一电子元件与所述第一RDL电连接；
    设置在所述第一RDL正面的第一化合物，所述第一电子元件包封在所述第一化合物中；
    设置在所述第一RDL背面的第二电子元件，所述第二电子元件与所述第一RDL电连接；
    设置在所述第一RDL背面的第二化合物，所述第二电子元件包封在第二化合物中；
    其中，所述第一电子元件为裸片或无源器件中的至少一种，所述第二电子元件为二次封装的器件。
  2. 根据权利要求1所述的系统级封装，其特征在于，所述系统级封装还包括：
    第二RDL；
    设置在所述第一RDL与所述第二RDL之间的第一互连铜柱，所述第一互连铜柱用于使所述第一RDL与所述第二RDL之间电连接。
  3. 根据权利要求2所述的系统级封装，其特征在于，所述系统级封装还包括：
    设置在所述第二RDL的远离所述第一RDL的面的第三电子元件，所述第三电子元件与所述第二RDL电连接；
    设置在所述第二RDL的远离所述第一RDL的面的第三化合物，所述第三电子元件包封在所述第三化合物中。
  4. 根据权利要求1所述的系统级封装，其特征在于，所述系统级封装还包括：
    封装基板；
    设置在所述第一RDL与所述封装基板之间的第二互连铜柱，所述第二互连铜柱用于使所述第一RDL与所述封装基板之间电连接。
  5. 根据权利要求4所述的系统级封装，其特征在于，所述系统级封装还包括：
    设置在所述封装基板的远离所述第一RDL的面的第四电子元件，所述第四电子元件与所述封装基板电连接；
    设置在所述封装基板的远离所述第一RDL的面的第四化合物，所述第四电子元件包封在所述第四化合物中。
  6. 根据权利要求1至5中任一项所述的系统级封装，其特征在于，所述系统级封装还包括：
    至少一个铜核锡球，所述铜核锡球一端与所述第一RDL电连接，另一端位于所述系统级封装外侧，用于与外部电路电连接。
  7. 根据权利要求1至5中任一项所述的系统级封装，其特征在于，所述第二电子元件通过正装、倒装或SMT中的至少一种方式设置在第一RDL背面。
  8. 根据权利要求1至5中任一项所述的系统级封装，其特征在于，所述第一电子元件通过扇出工艺设置在第一RDL正面。
  9. 根据权利要求1至5中任一项所述的系统级封装，其特征在于，所述系统级封装还包括：
    第五电子元件，与所述第一RDL电连接，所述第五电子元件为裸片或无源器件中的至少一种。
  10. 一种制备系统级封装的方法，其特征在于，包括：
    准备承载板，所述承载板用于实现电子元件的临时贴装及位置固定；
    将扇出的第一电子元件以外引出的焊盘面朝下的方式贴装固定在所述承载板上；
    通过塑封工艺将所述第一电子元件埋置在第一化合物中；
    拆除所述承载板；
    通过半导体或液晶LCD的工艺方法制作嵌入到第一化合物器件中向外扇出的第一RDL，所述第一电子元件与所述第一RDL电连接；
    在将要贴装第二电子元件或第五电子元件的所述第一RDL的表面进行处理；
    在所述第一RDL的表面贴装所述第二电子元件或所述第五电子元件，所述第二电子元件或所述第五电子元件与所述第一RDL电连接；
    通过塑封工艺将所述第二电子元件或所述第五电子元件埋置在第二化合物中；
    在扇出面外部互连输入输出I/O穿透模塑通孔TMV并进行焊球加工，用于与外部电路电连接。
  11. 根据权利要求10所述的方法，其特征在于，所述在将要贴装第二电子元件或第五电子元件的所述第一RDL的表面进行处理之后，所述方法还包括：
    在所述第一RDL的表面植铜柱。
  12. 根据权利要求10所述的方法，其特征在于，所述在将要贴装第二电子元件或第五电子元件的所述第一RDL的表面进行处理之后，所述方法还包括：
    在所述第一RDL的表面电镀导电柱。
  13. 根据权利要求11或12所述的方法，其特征在于，所述通过塑封工艺将所述第二电子元件或所述第五电子元件埋置在第二化合物中之后，所述方法还包括：
    通过减薄工艺将嵌埋在第二化合物内的所述铜柱或所述导电柱露出来。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023134013A1 (zh) * 2022-01-13 2023-07-20 长鑫存储技术有限公司 一种芯片封装结构及存储系统
CN117153811A (zh) * 2023-08-29 2023-12-01 之江实验室 一种针对晶上系统的供电装置

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111312690A (zh) * 2020-02-14 2020-06-19 华为技术有限公司 系统级封装及其制备方法
CN112382626B (zh) * 2020-11-11 2022-11-22 歌尔微电子有限公司 系统级封装结构及其制作工艺和电子设备
CN113035812B (zh) * 2020-12-22 2022-09-27 复旦大学 三维集成结构及其制造方法
CN116960075A (zh) * 2022-04-15 2023-10-27 华为技术有限公司 芯片封装结构及其制作方法、电子设备
CN117894788A (zh) * 2022-10-12 2024-04-16 华为技术有限公司 器件的封装方法、器件封装模组和电子设备
CN115332224A (zh) * 2022-10-14 2022-11-11 北京华封集芯电子有限公司 3d封装结构及其制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202394963U (zh) * 2011-12-28 2012-08-22 日月光半导体制造股份有限公司 多芯片晶圆级半导体封装构造
CN105765711A (zh) * 2013-12-23 2016-07-13 英特尔公司 封装体叠层架构以及制造方法
US20170053898A1 (en) * 2015-08-21 2017-02-23 Powertech Technology Inc. Semiconductor package with pillar-top-interconnection (pti) configuration and its mis fabricating method
CN107533985A (zh) * 2015-04-23 2018-01-02 苹果公司 包括第一级裸片、背对背堆叠的第二级裸片和第三级裸片以及对应的第一再分配层、第二再分配层和第三再分配层的竖直堆叠系统级封装及其制造方法
CN111312690A (zh) * 2020-02-14 2020-06-19 华为技术有限公司 系统级封装及其制备方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9478474B2 (en) * 2012-12-28 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for forming package-on-packages
CN106876363A (zh) * 2017-03-13 2017-06-20 江苏长电科技股份有限公司 3d连接的扇出型封装结构及其工艺方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202394963U (zh) * 2011-12-28 2012-08-22 日月光半导体制造股份有限公司 多芯片晶圆级半导体封装构造
CN105765711A (zh) * 2013-12-23 2016-07-13 英特尔公司 封装体叠层架构以及制造方法
CN107533985A (zh) * 2015-04-23 2018-01-02 苹果公司 包括第一级裸片、背对背堆叠的第二级裸片和第三级裸片以及对应的第一再分配层、第二再分配层和第三再分配层的竖直堆叠系统级封装及其制造方法
US20170053898A1 (en) * 2015-08-21 2017-02-23 Powertech Technology Inc. Semiconductor package with pillar-top-interconnection (pti) configuration and its mis fabricating method
CN111312690A (zh) * 2020-02-14 2020-06-19 华为技术有限公司 系统级封装及其制备方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023134013A1 (zh) * 2022-01-13 2023-07-20 长鑫存储技术有限公司 一种芯片封装结构及存储系统
CN117153811A (zh) * 2023-08-29 2023-12-01 之江实验室 一种针对晶上系统的供电装置
CN117153811B (zh) * 2023-08-29 2024-03-05 之江实验室 一种针对晶上系统的供电装置

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