WO2022247294A1 - 芯片封装结构以及制作方法、电子设备 - Google Patents

芯片封装结构以及制作方法、电子设备 Download PDF

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Publication number
WO2022247294A1
WO2022247294A1 PCT/CN2022/070373 CN2022070373W WO2022247294A1 WO 2022247294 A1 WO2022247294 A1 WO 2022247294A1 CN 2022070373 W CN2022070373 W CN 2022070373W WO 2022247294 A1 WO2022247294 A1 WO 2022247294A1
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chip
layer
substrate
plastic
conductor
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PCT/CN2022/070373
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English (en)
French (fr)
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郭学平
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荣耀终端有限公司
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Definitions

  • the present application relates to the technical field of chip packaging, and in particular to a chip packaging structure, manufacturing method, and electronic equipment.
  • double-sided packaging technology is generally used.
  • the requirements for the integration level of the double-sided packaging module increase, the demand for the number of input/output (I/O) pins of the double-sided packaging module will also increase.
  • the number of lead-out I/O pins of the double-sided packaging module is also limited, thereby affecting the application range of the double-sided packaging module.
  • Embodiments of the present application provide a chip packaging structure, manufacturing method, and electronic device, which can increase the number of lead I/O pins of the packaged packaging module, improve the integration of the packaging module and the application range of the packaging module.
  • the present application provides a chip packaging structure.
  • the chip packaging structure includes: a substrate, a first chip, a device module, a first plastic sealing layer and a second plastic sealing layer.
  • the device module is coupled to the first surface of the substrate, and is covered and molded by the first plastic encapsulation layer.
  • the first chip is coupled to the second surface of the substrate and is covered and molded by the second plastic encapsulation layer.
  • a side of the second plastic packaging layer away from the substrate is provided with an RDL wiring layer, and the RDL wiring layer is used to lead out external soldering pins.
  • a first conductor column is disposed in the second plastic encapsulation layer, and the first end of the first conductor column is coupled to the substrate, and the second end of the first conductor column is coupled to the RDL wiring layer.
  • the chip packaging structure adopts a double-sided packaging structure.
  • the first conductor column is arranged in the second plastic packaging layer that encapsulates the first chip, and a side of the second plastic packaging layer that is far away from the substrate Set the RDL wiring layer on the side.
  • the RDL wiring layer is used to lead out external soldering pins as leading out I/O pins.
  • the first conductive pillars are respectively coupled to the substrate and the RDL wiring layer, so that the lead-out I/O pins on the RDL wiring layer can be connected to the substrate for signal connection, thereby improving the integration of the chip packaging structure.
  • the packaging structure can be applied to more application scenarios, thereby improving the miniaturization competitiveness of electronic devices that have higher requirements on the number of I/O pins.
  • the above-mentioned device module may include one or more of passive devices, WB chips, and soldered chips.
  • various chip packaging scenarios can be applied.
  • the above-mentioned chip packaging structure may further include a second chip.
  • the second chip is stacked on the side of the first chip away from the substrate, and is covered and molded by the second plastic encapsulation layer.
  • the side of the second chip away from the first chip has soldering bumps; the soldering bumps are coupled with the RDL wiring layer.
  • the second plastic sealing layer may include a second inner plastic sealing layer and a second outer plastic sealing layer.
  • the second inner plastic encapsulation layer is used for encapsulating and encapsulating the first chip.
  • the second outer plastic sealing layer is used for covering the second chip with plastic packaging.
  • the first conductor post includes a first inner conductor post and a first outer conductor post.
  • the first inner conductor column is located in the second inner plastic encapsulation layer.
  • the first outer conductor post is located in the second outer plastic encapsulation layer.
  • the first inner conductor post is coupled to the first outer conductor post.
  • the first chip and the first inner conductor post can be plastic-sealed by the second inner plastic sealing layer; the second chip and the first outer conductive post can also be plastic-sealed by the second outer plastic sealing layer.
  • the plastic sealing of the second internal plastic sealing layer is completed, not only the second internal plastic sealing layer can be thinned, but also the substrate of the first chip can be thinned to reduce the thickness of the first chip, thereby reducing the thickness of the entire chip.
  • the thickness of the package structure provides the integration level of the chip package.
  • the first chip and the second chip can be mounted with adhesive.
  • a ground layer may be disposed in the substrate.
  • a shielding layer is provided on the outer surface of the first plastic sealing layer, and the shielding layer is coupled to the grounding layer.
  • a Faraday cage structure can be formed between the grounding layer and the shielding layer in the substrate to perform electromagnetic shielding on the device modules on the substrate and improve the performance of the chip packaging structure.
  • a third plastic sealing layer may also be provided on the outside of the shielding layer; the side of the third plastic sealing layer away from the shielding layer is mounted with an antenna structure.
  • a second conductor column is arranged in the first plastic sealing layer; a third conductive column is arranged in the third plastic sealing layer. The first end of the second conductor column is coupled to the substrate, the second end of the second conductor column is coupled to the first end of the third conductor column, and the second end of the third conductor column is coupled to the antenna structure.
  • the antenna structure can be packaged using the antenna in package (AIP) technology to improve the integration of the chip and meet the requirements of miniaturization of the chip module.
  • AIP antenna in package
  • a first dielectric layer is disposed between the antenna structure and the third plastic encapsulation layer.
  • the first dielectric layer can be made on the side of the third plastic sealing layer away from the substrate, and it is easier to realize the fabrication of the antenna structure by sputtering seed layer, pattern transfer, electroplating and etching on the first dielectric layer, thereby improving The stability and reliability of the chip packaging structure.
  • a second dielectric layer is provided between the second plastic encapsulation layer and the RDL wiring layer; the second dielectric layer is provided with a first via structure at a position close to the first conductor column, The first conductor column is connected to the RDL wiring layer through the first via structure.
  • the second dielectric layer can be fabricated on the side of the second plastic encapsulation layer away from the substrate, on the second dielectric layer it is easier to realize the production of the RDL wiring layer by processes such as sputtering seed layer, pattern transfer, electroplating and etching, thereby Improve the stability and reliability of the chip packaging structure.
  • the present application provides an electronic device.
  • the electronic device includes an external component and at least one possible chip package structure according to any one of the above first aspects coupled with the external component.
  • the external components include at least one of a package substrate, an interposer, or at least one fan-out redistribution layer.
  • the present application provides a method for manufacturing a chip packaging structure.
  • the manufacturing method includes: setting a device module on the first surface of the substrate, and coupling the device module with the substrate.
  • a first plastic sealing layer is arranged on the first surface of the substrate, so that the device module is covered and sealed by the first plastic sealing layer.
  • the first chip and the first conductor column are arranged on the second surface of the substrate, so that both the first chip and the first conductor column are coupled with the substrate.
  • a second plastic encapsulation layer is provided on the second surface of the substrate, so that the first chip and the first conductor column are covered and molded by the second plastic encapsulation layer.
  • An RDL wiring layer is made on the side of the second plastic packaging layer away from the substrate, and external soldering pins are drawn out on the RDL wiring layer.
  • the above method may further include: setting a second chip on the side of the first chip away from the substrate, the second chip has a welding bump on the side away from the first chip; The point is coupled to the RDL wiring layer.
  • arranging the first chip and the first conductor column on the second surface of the substrate includes: arranging the first chip and the first inner conductor column on the second surface of the substrate, Both the first chip and the first conductor column are coupled to the substrate.
  • the first outer conductor post is welded on the first inner conductor post.
  • Setting the second plastic sealing layer on the second surface of the substrate includes: setting a second inner plastic sealing layer on the second surface of the substrate, so that the first chip and the first inner conductor column are covered and sealed by the second inner plastic sealing layer.
  • a second outer plastic sealing layer is provided on a side of the second inner plastic sealing layer away from the substrate, so that the second chip and the first outer conductor column are covered and sealed by the second outer plastic sealing layer.
  • the method may further include: forming a shielding layer on a side of the first plastic encapsulation layer away from the substrate.
  • the method may further include: welding the second conductor post on the first surface of the substrate.
  • the above method may further include: welding a third conductor post at an end of the second conductor post away from the substrate.
  • a third plastic sealing layer is arranged on the side of the shielding layer away from the substrate, so that the shielding layer and the third conductor column are covered and sealed by the third plastic sealing layer.
  • An antenna structure is mounted on a side of the third plastic packaging layer away from the shielding layer, so that the antenna structure is coupled to the third conductor post.
  • any chip packaging structure provided above can be realized by the corresponding chip packaging structure provided above, or related to the corresponding chip packaging structure provided above Therefore, the beneficial effects that it can achieve can refer to the beneficial effects in the chip packaging structure provided above, and will not be repeated here.
  • FIG. 1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application.
  • FIG. 2 is a structural schematic diagram 1 of the chip packaging structure provided by the embodiment of the present application.
  • FIG. 3 is a flow chart 1 of a manufacturing method of a chip packaging structure provided by an embodiment of the present application
  • FIG. 4 is a schematic structural diagram of performing S301 in FIG. 3;
  • FIG. 5 is a schematic structural diagram of performing S302 in FIG. 3;
  • FIG. 6 is a schematic structural diagram of performing S303 in FIG. 3;
  • FIG. 7 is a schematic structural diagram of performing S304 in FIG. 3;
  • FIG. 8 is a schematic structural diagram of performing S305 in FIG. 3;
  • FIG. 9 is a second structural schematic diagram of the chip packaging structure provided by the embodiment of the present application.
  • Fig. 10 is another structural schematic diagram formed by executing S303 in Fig. 3;
  • Fig. 11 is another structural schematic diagram formed by executing S304 in Fig. 3;
  • Fig. 12 is another structural schematic diagram formed by executing S305 in Fig. 3;
  • FIG. 13 is a structural schematic diagram III of the chip packaging structure provided by the embodiment of the present application.
  • Fig. 14 is another structural schematic diagram formed by executing S303 and S304 in Fig. 3;
  • FIG. 15 is a structural schematic diagram 4 of the chip packaging structure provided by the embodiment of the present application.
  • FIG. 16 is a structural schematic diagram five of the chip packaging structure provided by the embodiment of the present application.
  • FIG. 17 is the second flow chart of the manufacturing method of the chip packaging structure provided by the embodiment of the present application.
  • FIG. 18 is a schematic diagram of a structure formed by executing S1701 in FIG. 17;
  • FIG. 19 is a schematic diagram of a structure formed by executing S1702 in FIG. 17;
  • FIG. 20 is a schematic diagram of a structure formed by executing S1703 and S1704 in FIG. 17;
  • FIG. 21 is a schematic diagram of an intermediate structure formed by executing S1705 in FIG. 17;
  • FIG. 22 is a schematic diagram of a structure formed by executing S1705 in FIG. 17;
  • Fig. 23 is a schematic diagram of the structure formed by executing S1706, S1707 and S1708 in Fig. 18;
  • FIG. 24 is a schematic structural diagram of another electronic device provided by an embodiment of the present application.
  • first”, second, etc. are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features.
  • a feature defined as “first”, “second”, etc. may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • connection should be understood in a broad sense, for example, “connection” can be a fixed connection, a detachable connection, or an integral body; it can be a direct connection, or It can be connected indirectly through an intermediary.
  • connection can be a fixed connection, a detachable connection, or an integral body; it can be a direct connection, or It can be connected indirectly through an intermediary.
  • coupled may be an electrical connection for signal transmission.
  • Coupling can be a direct electrical connection, or an indirect electrical connection through an intermediary.
  • An embodiment of the present application provides an electronic device.
  • the electronic device includes a mobile phone (mobile phone), a tablet computer (pad), a computer, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (virtual reality, VR) terminal device, an augmented reality (augmented reality, AR ) Terminal equipment and other electronic products.
  • the embodiment of the present application does not specifically limit the specific form of the foregoing electronic device.
  • the electronic device 01 includes an external component 10 and at least one chip packaging structure 20 coupled to the external component 10 .
  • the external component 10 may include at least one of a packaging substrate, a silicon-based interposer, and at least one redistribution layer (RDL) of fan-out (integrated fan-out, InFO).
  • RDL redistribution layer
  • the above-mentioned chip package structure 20 may include multiple chips or device modules.
  • the chips in the chip packaging structure 20 may be logic chips or memory chips.
  • the chip package structure 20 may be provided with a ball grid array (BGA) as shown in FIG. 1 , or a plurality of copper pillar bumps arranged in an array, for coupling with the external component 10 .
  • BGA ball grid array
  • the electronic device 01 also includes printed circuit boards (printed circuit boards, PCB).
  • PCB printed circuit boards
  • the above-mentioned external component 10 can also be coupled with the PCB through an electrical connector (such as a BGA solder ball array).
  • the above-mentioned chip package structure 20 can realize signal transmission with other chips or chip package structures on the PCB through the external component 10 .
  • the chip packaging structure 20 may include a substrate 101 , a first chip 103 , a device module 102 , a first plastic packaging layer 104 and a second plastic packaging layer 105 .
  • the substrate 101 is a carrier for chip packaging, and the substrate 101 includes one or more wiring layers, which can provide electrical connections to multiple chips arranged on the substrate 101, so as to realize the functions of the packaged chips.
  • the device module 102 may include one or more of a passive device 1023, a wire bonding (WB) chip 1021 and a soldering chip 1022, and may also include a ball grid array package (ball grid array, BGA) that has been packaged.
  • the device, the land grid array package (land grid array, LGA) device, or the quad flat no-leads package (quad flat no-leads package, QFN) device are not specifically limited in this embodiment of the present application.
  • the above-mentioned device module 102 is coupled to the first surface 1013 of the above-mentioned substrate 101 and is encapsulated by the first plastic sealing layer 104 .
  • the device module 102 may include a passive device 1023 , a WB chip 1021 and a welding chip 1022 .
  • the passive device 1023 can be coupled to the substrate 101 through surface mount technology (surface mounted technology, SMT).
  • the WB chip 1021 may refer to a chip whose circuit structure is coupled to the substrate 101 through wires during chip packaging. That is to say, the WB chip 1021 can be coupled to the substrate 101 through a wire bond.
  • the soldered chip 1022 may refer to a chip that couples the circuit structure of the chip to the substrate 101 by means of soldering (such as pads and solder balls) during chip packaging. That is to say, the soldering chip 1022 can be coupled to the substrate 101 by soldering.
  • the material of the first plastic sealing layer 104 can be a thermosetting material mixed with a resin and a filler, wherein the resin can be a resin material such as epoxy resin, and the filler can be an inorganic material such as silicon oxide (SiO2) or boron nitride (BN). Materials and fillers can adjust the properties of the resin to achieve material properties of high thermal conductivity, high melting point, and low coefficient of thermal expansion (CTE).
  • the material of the first plastic sealing layer 104 may also be other types of materials, such as ceramics or glass, which are not specifically limited in this embodiment of the present application.
  • the first chip 103 is coupled to the second surface 1014 of the substrate 101 and is encapsulated by the second plastic layer 105 .
  • the first chip 103 may be a bonding chip 1022, and is coupled to the above-mentioned substrate 101 by means of soldering (such as pads, solder balls).
  • soldering such as pads, solder balls.
  • the substrate 101 is provided with a plurality of pads 1012 on the side away from the device module 102, and the first chip 103 is soldered to the plurality of pads 1012 on the substrate 101 through a plurality of chip solder balls 1031, thereby The first chip 103 is coupled to the substrate 101 .
  • the chip package structure 20 In order to make the chip package structure 20 have an array of solder balls for coupling with external components, or a plurality of copper stud bumps arranged in an array.
  • An RDL wiring layer 107 is provided on a side of the second plastic encapsulation layer 105 away from the substrate 101 , and the RDL wiring layer 107 can be used to lead out external soldering pins 109 .
  • the external soldering pin 109 may be a BGA solder ball array as shown in FIG. 2 , or an LGA connection contact, or a plurality of copper pillar bumps arranged in an array, which is not specifically limited in this embodiment of the present application.
  • the external welding pins 109 led out from the RDL wiring layer 107 can realize signal connection with the external component 10 shown in FIG. 1 .
  • the external soldering pins 109 drawn from the RDL wiring layer 107 need to be connected to the substrate in the chip package structure 20 101 implements signal connection.
  • the signal connection between the RDL wiring layer 107 and the substrate 101 can be realized through copper pillars.
  • a first conductor column 106 may be disposed in the second plastic encapsulation layer 105, and the first end of the first conductor column 106 is coupled to the substrate 101, and the second end of the first conductor column 106 is connected to the above-mentioned RDL wiring layer 107. coupling.
  • the first conductor post 106 may be a copper post disposed inside the second plastic encapsulation layer 105 . That is, the first end of the copper pillar is coupled to the substrate 101 , and the second end of the copper pillar is connected to the RDL wiring layer 107 , so as to realize the signal connection between the RDL wiring layer 107 and the substrate 101 .
  • the conductor post (such as the first conductor post 106 ) in the embodiment of the present application is a post structure made of conductive metal materials, such as copper, nickel, tungsten and other metal conductive materials.
  • the structure of the conductor column may be any column structure such as a cylinder, a triangular prism, and a conical column structure, which is not particularly limited in this embodiment of the present application.
  • the chip packaging structure 20 adopts a double-sided packaging structure.
  • the first conductor post 106 is arranged in the second plastic packaging layer 105 of the packaging first chip 103, and the second plastic packaging layer 105 is away from the An RDL wiring layer 107 is provided on one side of the substrate 101 .
  • the RDL wiring layer 107 is used to lead out external solder pins 109 as lead out I/O pins.
  • the first conductive pillars 106 are respectively coupled to the substrate 101 and the RDL wiring layer 107, so that the outgoing I/O pins on the RDL wiring layer 107 can be connected to the substrate 101 for signal connection, thereby improving the integration of the chip package structure.
  • the chip packaging structure can be applied to more application scenarios, thereby improving the miniaturization competitiveness of electronic devices that have higher requirements on the number of I/O pins.
  • the RDL wiring layer 107 may include one wiring layer, or may include multiple stacked wiring layers, which is not specifically limited in this embodiment of the present application.
  • adjacent wiring layers may be interconnected through an interconnection structure, so that the substrate 101 is signal-connected to the lead-out soldering pin 109 on the RDL wiring layer 107 .
  • the aforementioned chips may include a substrate and a circuit structure disposed on the substrate.
  • the substrate may be a glass substrate, an amorphous silicon (a-Si) substrate, or a silicon carbide (SiC) substrate, etc., which are not specifically limited in this embodiment of the present application.
  • a dielectric layer 108 (ie, the second dielectric layer) is arranged between them.
  • the material of the dielectric layer 108 may be polyimide (polyimide, PI), benzocyclobutene (benzocyclobutene, BCB) and other insulating materials.
  • the dielectric layer 108 is provided with a first interconnection hole 1081 at a position close to the first conductor pillar 106 .
  • the first interconnection hole 1081 may be filled with metal material (such as copper, nickel, etc.), so that the first conductor column 106 is coupled to the RDL wiring layer 107 through the first interconnection hole 1081 .
  • the manufacturing method of the chip packaging structure includes:
  • solder paste can be printed on the first surface 1013 of the substrate 101, so that the SMT device is mounted on the first surface 1013 of the substrate 101, And coupled with the substrate 101 .
  • the substrate of the chip can be faced to the substrate 101 first, and the WB chip 1021 can be mounted on the first surface 1013 of the substrate 101 by using adhesive or dispensing, and then the WB chip can be placed on the first surface 1013 of the substrate 101 through a wire.
  • the circuit structure of the chip 1021 is connected to the substrate 101 to realize the interconnection and signal transmission between the WB chip 1021 and the substrate 101 .
  • the welding surface of the welding chip 1022 (that is, the side on which the solder balls of the chip are arranged) can be directed towards the substrate 101, and the welding chip 1022 is welded to the substrate 101 by means of reflow welding, laser welding, etc. Interconnection of the substrate 101 and signal transmission.
  • the substrate 101 or the device module 102 may be processed by a plasma process.
  • the device can be packaged by plastic packaging, and the gap between the devices and the gap between the device and the substrate 101 need to be packaged in plastic.
  • the welding surface of the first chip 103 can face the substrate 101, and the second A chip 103 is soldered to the substrate 101 , so as to realize interconnection and signal transmission between the first chip 103 and the substrate 101 .
  • the first conductor column 106 can be a copper column structure, and the copper column structure can also be welded to the substrate 101 on the second surface 1014 of the substrate 101 by means of reflow welding or laser welding, so as to realize the first A first end of the conductor post 106 is coupled to the substrate 101 .
  • the first chip 103 and the first conductive column 106 can be packaged by plastic packaging to form the second plastic packaging layer 105 .
  • the first chip 103 and the first conductor post 106 need to be completely wrapped inside the molding compound. That is to say, the height of the molding compound needs to exceed the height of the first chip 103 and the first conductive pillar 106 .
  • the height of the first conductor post 106 can be slightly higher than the thickness of the first chip 103, or even equal to the thickness of the first chip 103, and this embodiment of the present application does not make special limit.
  • the second plastic packaging layer 105 can be thinned by several steps. Thin processing, thereby exposing the first conductive post 106 .
  • the dielectric layer 108 can be formed by spraying polyimide or other insulating materials on the side of the second plastic sealing layer 105 away from the substrate 101, and then the dielectric layer 108 is facing the first conductor column 106.
  • a first interconnection hole 1081 is formed at the position using a photolithography process (including masking, exposure, development, and etching processes), and a conductive material (such as copper, nickel, etc.) is filled in the first interconnection hole 1081 .
  • the RDL wiring layer 107 can be fabricated on the side of the dielectric layer 108 away from the second plastic encapsulation layer 105 , as shown in FIG. 8 .
  • the RDL wiring layer 107 may be one layer, or may be a multilayer interconnection structure, which is not specifically limited in this embodiment of the present application.
  • the seed layer is a very thin metal layer produced on the surface of the substrate by processes such as electroless plating, sputtering, or evaporation, and is used as the initiation of the electroplating process during the manufacturing process of the RDL wiring layer 107.
  • the metal layer is also called the seed layer.
  • the material of the seed layer may be conductive metals such as copper and nickel.
  • RDL pattern transfer can be realized through processes such as exposure and development of materials such as photoresist or photosensitive film.
  • the lead-out I/O pins of the above-mentioned chip package structure 20 can be fanned out to the entire surface of one side of the chip package structure 20, so that more lead-out external soldering tubes can be realized.
  • the pins 109 (such as solder balls) may be applicable to the scene where the chip/device module 102 in the chip packaging structure 20 has many interconnection links with external devices.
  • the chip package structure 20 may further include a second chip 201 .
  • the second chip 201 is stacked on the side of the first chip 103 away from the substrate 101 , and may also be encapsulated by the second plastic encapsulation layer 105 .
  • the chip package structure 20 may further include a second chip 201 .
  • the second chip 201 is stacked on the side of the first chip 103 away from the substrate 101 , and may also be encapsulated by the second plastic encapsulation layer 105 .
  • at least two chips such as the first chip 103 and the second chip 201
  • they can be packaged in a stacked manner, thereby reducing the lateral size of the chip packaging structure and improving chip packaging.
  • the degree of integration of devices in the structure is not limited to be packaged.
  • the above-mentioned second chip 201 may be a chip with solder bumps (bump) 2011 .
  • the substrate of 201 is mounted by patch glue. That is to say, after the mounting is completed, the side of the second chip 201 away from the first chip 103 has welding bumps 2011 .
  • the solder bumps 2011 of the second chip 201 can be coupled to the RDL wiring layer 107 .
  • the welding bump 2011 of the second chip 201 is coupled with the RDL wiring layer 107, since the RDL wiring layer 107 realizes signal connection with the substrate 101 through the first conductive column 106, the second chip 201 can also be connected with the substrate 101. signal connection.
  • step S303 after the first chip 103 is soldered to the substrate 101, the back surface of the first chip 103 (ie, Glue is dispensed on the side of the first chip 103 away from the substrate 101, and then the substrate of the second chip 201 is directed towards the first chip 103, so that the second chip 201 is attached to the first chip 103, to form as shown in FIG. 10 Structure.
  • the back surface of the first chip 103 ie, Glue is dispensed on the side of the first chip 103 away from the substrate 101, and then the substrate of the second chip 201 is directed towards the first chip 103, so that the second chip 201 is attached to the first chip 103, to form as shown in FIG. 10 Structure.
  • the second chip 201 needs to be packaged in plastic, as shown in FIG. 11 . Since the second chip 201 has welding bumps 2011 , the height of the molding compound in the second molding layer 105 needs to exceed the height of the first conductor post 106 and the sum of the thicknesses of the first chip 103 and the second chip 201 . It should be understood that, in order to reduce the thickness of the entire chip package structure 20, the height of the first conductor column 106 can be slightly higher than the sum of the thicknesses of the first chip 103 and the second chip 201, for example, the height of the first conductor column 106 can be higher than the height of the second chip 201. The sum of the thicknesses of the first chip 103 and the second chip 201 is 0 to 200 micrometers (um), or the height of the first conductive pillar 106 may be equal to the thickness of the first chip 103 and the second chip 201 .
  • the second plastic encapsulation layer 105 needs to be thinned and the soldering bumps of the second chip 201 are exposed. 2011 and the first conductor post 106. As shown in FIG.
  • the first interconnection needs to be formed by photolithography at the position corresponding to the welding bump 2011 of the second chip 201 hole, and fill the interconnection hole with a conductive material so that the second chip 201 is interconnected with the RDL wiring layer 107, so that when the RDL wiring layer 107 is interconnected with the substrate 101 through the first conductor column 106, the second The two chips 201 may also be interconnected with the substrate 101 to realize signal connection.
  • the second plastic encapsulation layer 105 shown in FIG. 9 may include a second inner plastic encapsulation layer 1051 and a second outer plastic encapsulation layer 1052 .
  • the second inner plastic encapsulation layer 1051 can be used for encapsulating the first chip 103 with plastic encapsulation.
  • the second outer plastic layer 1052 can be used to encapsulate the second chip 201 with plastic.
  • the first conductor post 106 shown in FIG. 9 can also be divided into a first inner conductor post 1061 and a first outer conductor post 1062 .
  • the first inner conductor post 1061 is located in the second inner plastic encapsulation layer 1051 .
  • the first outer conductive post 1062 is located inside the second outer plastic encapsulation layer 1052 .
  • the first inner conductive post 1061 is coupled to the first outer conductive post 1062 .
  • the first chip 103, the second chip 201, and the first conductor column 106 are integrally plastic-sealed by the second plastic-seal layer 105, and the height after plastic-seal is at least the first The sum of the thicknesses of the chip and the second chip.
  • the first chip 103 and the first inner conductor post 1061 are covered and encapsulated by the second inner plastic encapsulation layer 1051.
  • the substrate of the first chip 103, the first The inner conductor post 1061 and the second inner plastic encapsulation layer 1051 are overall thinned, thereby reducing the thickness of the first chip 103 .
  • the second chip 201 and the first outer conductor post 1062 are overmolded by the second outer plastic layer 1052 .
  • the height of the second inner molding layer 1051 and the second outer molding layer 1052 is the sum of the thickness of the thinned first chip 103 and the thickness of the second chip 201 , so that the thickness of the chip packaging structure 20 can be reduced.
  • step S304 complete the plastic packaging of the first chip 103 and the first inner conductor column 1061 to form the second inner plastic layer 1051 .
  • the formed second inner molding layer 1051 may be thinned.
  • the substrate of the first chip 103 can be thinned, so as to reduce the thickness of the first chip 103 and expose the first chip 103.
  • An inner conductor post 1061 is not only the second inner plastic encapsulation layer 1051 can be thinned, but also the substrate of the first chip 103 can be thinned, so as to reduce the thickness of the first chip 103 and expose the first chip 103.
  • the second inner plastic encapsulation layer 1051 After completing the thinning process of the second inner plastic encapsulation layer 1051, as shown in (b) in FIG. , and weld a copper post on the first inner conductor post 1061 as the first outer conductor post 1062 .
  • a method similar to that in the above step S304 can be performed, and the second chip 201 and the first outer conductor post 1062 are plastic-wrapped to form the second chip 201.
  • Two outer plastic sealing layers 1052 as shown in (c) of FIG. 14 .
  • the second outer plastic encapsulation layer 1052 can be thinned to expose the soldering bumps of the second chip 201 and the first outer conductor post 1062 .
  • a ground layer 1011 is also provided in the substrate 101 .
  • a shielding layer 202 is disposed on the outer surface of the first plastic sealing layer 104 .
  • the shielding layer 202 is coupled to the grounding layer 1011 in the substrate 101 , so that a Faraday cage structure is formed between the grounding layer 1011 in the substrate 101 and the shielding layer 202 to electromagnetically shield the device module 102 on the substrate 101 .
  • FIG. 2 FIG. 9 and FIG.
  • ground layer 1011 there is a ground network layer (ie, ground layer 1011) extending from the inside of the substrate 101 to the edge of the substrate 101 on the side of the substrate 101, and the first plastic encapsulation layer 104
  • the shielding layer 202 formed on the outer surface of the first plastic encapsulation layer 104 extends to the ground layer 1011 of the substrate 101 along the outer surface of the first plastic encapsulation layer 104 , and is coupled to the ground layer 1011 .
  • the fabrication of the shielding layer 202 can be realized by sputtering, and the structure of the shielding layer 202 can be a three-layer metal film structure, such as a stainless steel layer (steel use stainless, SUS), a copper layer and a stainless steel layer SUS three-layer structure .
  • the shielding layer 202 can also be made by spraying.
  • the shielding layer 202 made by spraying can use shielding materials such as conductive silver paste.
  • the embodiment of the present application does not impose special restrictions on the material and manufacturing method of the shielding layer 202 .
  • the antenna may be packaged using antenna in package (AIP) technology, for example, for a radio frequency integrated circuit (radio frequency integrated circuit, RFIC) radio frequency front end (RFFE) Devices and antenna (antenna, ANT) structures can be packaged into a chip package structure 20 to improve chip integration and meet the requirements for miniaturization of chip modules.
  • AIP antenna in package
  • the packaging of the antenna structure 204 into the chip packaging structure 20 shown in FIG. 2 or FIG. 9 is taken as an example for description.
  • the antenna structure 204 may be mounted on a side of the third plastic packaging layer 203 away from the shielding layer 202 .
  • the shielding layer 202 may also serve as a ground reference plane of the antenna structure 204 .
  • a second conductor post 205 may be provided in the first plastic encapsulation layer 104
  • a third conductor post 206 may be provided in the third plastic encapsulation layer 203 .
  • the first end of the second conductor column 205 is coupled to the substrate 101
  • the second end of the second conductor column 205 is coupled to the first end of the third conductor column 206
  • the second end of the third conductor column 206 is connected to the antenna Structure 204 is coupled.
  • both the second conductor column 205 and the third conductor column 206 may be copper column structures.
  • the method for manufacturing the chip package structure 20 including the antenna structure 204 may include:
  • the second conductor column 205 may be soldered to the first surface 1013 of the substrate 101 , as shown in FIG. 18 .
  • the device module 102 and the second conductor column 205 can be plastic-encapsulated in the first plastic-encapsulation layer 104 after performing the above step S302 , as shown in FIG. 19 .
  • the first plastic encapsulation layer 104 can be thinned by several sets of thinners, so that the second conductive column 205 end bare. Then, an L-shaped area can be formed by cutting from the upper surface of the first plastic sealing layer 104 (that is, the side away from the substrate 101) to the second surface 1014 of the substrate 101 by a board splitter, and the grounding network (that is, the ground layer) on the substrate 101 is exposed. 1011), as shown in (a) in FIG. 21 or (b) in FIG. 21 .
  • the shielding layer 202 can be fabricated on the surface of the thinned first plastic encapsulation layer 104 (that is, the side away from the substrate 101) and the L-shaped region formed by cutting, and finally the shielding layer 200 with an L-shaped structure can be formed, as shown in FIG. (a) in Figure 22 or (b) in Figure 22.
  • the shielding layer 202 can be made by sputtering or spraying.
  • the material of the shielding layer 202 can be a three-layer metal film structure, or a shielding material such as conductive silver paste.
  • the fabrication of the shielding layer 202 needs to expose the second conductor post 205, that is, on the second end of the second conductor post 205 and the second end of the second conductor post 205. There is no need to make a shielding layer 202 around the two ends, so as to achieve signal connection between the antenna structure 204 and the substrate 101 through the second conductor post 205 and the third conductor post 206 .
  • a third conductor post 206 can be welded on the second end of the exposed second conductor post 205 .
  • the third conductor post 206 can be soldered by reflow soldering or laser soldering.
  • the third conductor post 206 As shown in (a) in FIG. 23 or (b) in FIG. 23, after the third conductor post 206 is welded to the second conductor post 205, it can be placed on the shielding layer 202 (that is, the side of the shielding layer 202 away from the substrate 101) ) to form the third plastic layer 203 , and the third plastic layer 203 can cover the entire shielding layer 202 and the entire third conductor column 206 .
  • S1708 mount the antenna structure on the side of the third plastic packaging layer away from the shielding layer, so as to couple the antenna structure with the third conductor column.
  • the antenna structure 204 can be fabricated on the surface of the third plastic encapsulation layer 203 (ie, the side of the third plastic encapsulation layer 203 away from the shielding layer 202 ).
  • the antenna structure 204 can be realized by sputtering seed layer, pattern transfer, electroplating, etching and other processes.
  • a dielectric layer 207 (ie, a first dielectric layer) is disposed between the antenna structure 204 and the third plastic encapsulation layer 203 .
  • the dielectric layer 207 can improve the bonding force between the antenna structure 204 and the third plastic packaging layer 203, and it is easier to pass sputtering seed layer, pattern transfer, electroplating and etching on the dielectric layer 207.
  • the manufacture of the antenna structure 204 is realized, thereby improving the stability and reliability of the chip packaging structure.
  • the fabrication of the RDL wiring layer and the fabrication of the external soldering pins can be completed in the above step S1709, the S1709 For the steps, reference may be made to the above step S305, which will not be repeated here.
  • FIG. 24 is a schematic structural diagram of another electronic device provided by an embodiment of the present application.
  • the electronic device may be a terminal device or a base station.
  • the electronic device may include an application subsystem, a memory (memory), a mass storage (massive storage), a baseband subsystem, a radio frequency integrated circuit (radio frequency integrated circuit, RFIC), a radio frequency front end (radio frequency front end, RFFE) devices, and antennas (antenna, ANT), these devices can be coupled through various interconnection buses or other electrical connections.
  • RFIC radio frequency integrated circuit
  • RFFE radio frequency front end
  • antennas antennas
  • ANT_1 represents the first antenna
  • ANT_N represents the Nth antenna
  • N is a positive integer greater than 1.
  • Tx represents the transmission path
  • Rx represents the reception path
  • different numbers represent different paths.
  • FBRx represents a feedback receiving path
  • PRx represents a main receiving path
  • DRx represents a diversity receiving path.
  • HB means high frequency
  • LB means low frequency, both refer to the relative high and low frequencies.
  • BB means baseband.
  • the application subsystem can be used as the main control system or main computing system of the electronic equipment, used to run the main operating system and application programs, manage the software and hardware resources of the entire electronic equipment, and provide users with a user interface.
  • An application subsystem may include one or more processing cores.
  • the application subsystem may also include driver software related to other subsystems (eg, baseband subsystem).
  • the baseband subsystem may also include one or more processing cores, as well as a hardware accelerator (hardware accelerator, HAC), cache, and the like.
  • the RFFE device, RFIC 1 can together form a radio frequency subsystem.
  • the RF subsystem can be further divided into RF receive path (RF receive path) and RF transmit path (RF transmit path).
  • the radio frequency receiving channel can receive the radio frequency signal through the antenna, process the radio frequency signal (such as amplifying, filtering and down-converting) to obtain the baseband signal, and transmit it to the baseband subsystem.
  • the radio frequency transmission channel can receive the baseband signal from the baseband subsystem, perform radio frequency processing (such as up-conversion, amplification and filtering) on the baseband signal to obtain a radio frequency signal, and finally radiate the radio frequency signal into space through the antenna.
  • the radio frequency subsystem may include an antenna switch, an antenna tuner, a low noise amplifier (low noise amplifier, LNA), a power amplifier (power amplifier, PA), a mixer (mixer), a local oscillator (local oscillator, LO ), filters and other electronic devices, these electronic devices can be integrated into one or more chips as required. Antennas are also sometimes considered part of the RF subsystem.
  • the baseband subsystem can extract useful information or data bits from baseband signals, or convert information or data bits into baseband signals to be transmitted. These information or data bits may be data representing user data such as voice, text, video, or control information.
  • the baseband subsystem can implement signal processing operations such as modulation and demodulation, encoding and decoding.
  • signal processing operations such as modulation and demodulation, encoding and decoding.
  • the baseband subsystem may simultaneously include multiple processing cores, or multiple HACs.
  • the radio frequency signal is an analog signal
  • the signal processed by the baseband subsystem is mainly a digital signal
  • an analog-to-digital conversion device is also required in the electronic equipment.
  • the analog-to-digital conversion device includes an analog-to-digital converter (analog to digital converter, ADC) that converts an analog signal to a digital signal, and a digital-to-analog converter (digital to analog converter, DAC) that converts a digital signal to an analog signal.
  • ADC analog to digital converter
  • DAC digital to analog converter
  • the analog-to-digital conversion device may be set in the baseband subsystem, or may be set in the radio frequency subsystem.
  • the processing core may represent a processor, and the processor may be a general-purpose processor or a processor designed for a specific field.
  • the processor may be a central processing unit (center processing unit, CPU), or a digital signal processor (digital signal processor, DSP).
  • the processor can also be a microcontroller (micro control unit, MCU), a graphics processing unit (graphics processing unit, GPU), an image signal processor (image signal processing, ISP), an audio signal processor (audio signal processor, ASP) ), and processors specifically designed for artificial intelligence (AI) applications.
  • AI processors include but are not limited to neural network processing unit (NPU), tensor processing unit (TPU) and processors called AI engines.
  • Hardware accelerators can be used to implement some sub-functions with high processing overhead, such as assembly and analysis of data packets, encryption and decryption of data packets, etc. These sub-functions can also be implemented by using a general-purpose processor, but due to performance or cost considerations, it may be more appropriate to use a hardware accelerator. Therefore, the type and number of hardware accelerators can be specifically selected based on requirements. In a specific implementation manner, one or a combination of a field programmable gate array (field programmable gate array, FPGA) and an application specific integrated circuit (application specified intergated circuit, ASIC) can be used to implement. Of course, one or more processing cores may also be used in a hardware accelerator.
  • field programmable gate array field programmable gate array
  • ASIC application specified intergated circuit
  • Memory can be divided into volatile memory (volatile memory) and non-volatile memory (non-volatile memory, NVM).
  • Volatile memory refers to memory in which data stored inside will be lost when the power supply is interrupted.
  • volatile memory is mainly random access memory (random access memory, RAM), including static random access memory (static RAM, SRAM) and dynamic random access memory (dynamic RAM, DRAM).
  • RAM random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • Non-volatile memory refers to memory in which the data stored inside will not be lost even if the power supply is interrupted.
  • Common non-volatile memories include read only memory (ROM), optical discs, magnetic disks, and various memories based on flash memory technology.
  • volatile memory can be selected for internal memory
  • non-volatile memory such as magnetic disk or flash memory can be selected for mass storage.
  • the baseband subsystem and the radio frequency subsystem together form a communication subsystem, which provides wireless communication functions for electronic devices.
  • the baseband subsystem is responsible for managing the hardware and software resources of the communication subsystem, and can configure the working parameters of the radio frequency subsystem.
  • One or more processing cores of the baseband subsystem may be integrated into one or more chips, which may be called baseband processing chips or baseband chips.
  • an RFIC may be called a radio frequency processing chip or a radio frequency chip.
  • the functional division of the RF subsystem and the baseband subsystem in the communication subsystem can also be adjusted.
  • radio frequency subsystem some functions of the radio frequency subsystem are integrated into the baseband subsystem, or some functions of the baseband subsystem are integrated into the radio frequency subsystem.
  • electronic devices may use combinations of different numbers and types of processing cores.
  • the radio frequency subsystem may include an independent antenna, an independent radio frequency front end (RF front end, RFFE) device, and an independent radio frequency chip.
  • RF chips are sometimes called receivers, transmitters or transceivers.
  • Antennas, RF front-end devices, and RF processing chips can all be manufactured and sold separately.
  • the radio frequency subsystem can also use different devices or different integration methods based on power consumption and performance requirements. For example, if some devices belonging to the radio frequency front end are integrated into the radio frequency chip, and even the antenna and the radio frequency front end devices are integrated into the radio frequency chip, the radio frequency chip can also be called a radio frequency antenna module or an antenna module.
  • the baseband subsystem may be an independent chip, and the chip may be called a modem (modem) chip.
  • the hardware components of the baseband subsystem can be manufactured and sold in units of modem chips. Modem chips are sometimes called baseband chips or baseband processors.
  • the baseband subsystem can also be further integrated into the SoC chip, and manufactured and sold in units of the SoC chip.
  • the software components of the baseband subsystem can be built into the hardware components of the chip before the chip leaves the factory, or can be imported into the hardware components of the chip from other non-volatile memories after the chip leaves the factory, or can be downloaded online through the network and update these software components.
  • the antenna, the radio frequency front-end, and the RFIC in the above-mentioned electronic device can be realized by the chip package structure shown in FIG. 15 and FIG. 16 . That is to say, the antenna, the radio frequency front-end and the RFIC can be packaged into the above-mentioned chip packaging structure shown in FIG. 15 and FIG. 16 to improve the integration of various device modules in the electronic equipment.

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Abstract

本申请提供一种芯片封装结构以及制作方法、电子设备。该芯片封装结构中采用双面封装结构，该双面封装结构中，在封装第一芯片的第二塑封层内设置第一导体柱，在第二塑封层远离基板的一侧设置RDL布线层。该RDL布线层用于引出外部焊接管脚，作为引出I/O管脚。第一导体柱分别与基板和RDL布线层相耦接，使得RDL布线层上的引出I/O管脚能够与基板实现信号连接，从而在提高芯片封装结构的集成度的基础上，使该芯片封装结构能够适用更多的应用场景，进而提高对引出I/O管脚数量具有更高要求的电子设备的小型化竞争力。

Description

芯片封装结构以及制作方法、电子设备
本申请要求于2021年05月27日提交国家知识产权局、申请号为202110586730.4、发明名称为“芯片封装结构以及制作方法、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及芯片封装技术领域，尤其涉及一种芯片封装结构以及制作方法、电子设备。
背景技术
随着封装内系统(system in package，SiP)技术的发展，会不断增加封装模组中单位体积内芯片或器件的密度，满足电子设备小型化的要求。
为提高封装模组的集成度，一般采用双面封装技术。随着双面封装模组中集成度的要求提高，对双面封装模组的引出输入/输出(input/output，I/O)管脚数量的需求也会增加。目前，由于双面封装模组结构的限制，使得双面封装模组的引出I/O管脚数量也受到限制，从而影响双面封装模组的应用范围。
发明内容
本申请实施例提供一种芯片封装结构以及制作方法、电子设备，能够提高封装后的封装模组的引出I/O管脚的数量，提高封装模组的集成度以及封装模组的应用范围。
第一方面，本申请提供一种芯片封装结构。该芯片封装结构包括：基板、第一芯片、器件模组、第一塑封层和第二塑封层。其中，器件模组耦接于基板的第一面，且被第一塑封层包覆塑封。第一芯片耦接于基板的第二面，且被第二塑封层包覆塑封。第二塑封层远离基板的一侧设置有RDL布线层，RDL布线层用于引出外部焊接管脚。第二塑封层内设置有第一导体柱，且第一导体柱的第一端与基板耦接，第一导体柱的第二端与RDL布线层耦接。
基于上述芯片封装结构，该芯片封装结构中采用双面封装结构，该双面封装结构中，在封装第一芯片的第二塑封层内设置第一导体柱，在第二塑封层远离基板的一侧设置RDL布线层。该RDL布线层用于引出外部焊接管脚，作为引出I/O管脚。第一导体柱分别与基板和RDL布线层相耦接，使得RDL布线层上的引出I/O管脚能够与基板实现信号连接，从而在提高芯片封装结构的集成度的基础上，使该芯片封装结构能够适用更多的应用场景，进而提高对引出I/O管脚数量具有更高要求的电子设备的小型化竞争力。
结合第一方面，一种可能的设计方式中，上述器件模组可以包括无源器件、WB芯片以及焊接芯片的一种或多种。在上述芯片封装结构中，可以适用多种芯片封装场景。
结合第一方面，一种可能的设计方式中，上述芯片封装结构还可以包括第二芯片。第二芯片堆叠于第一芯片远离基板的一侧，且被第二塑封层包覆塑封。第二芯片远离第一芯片的一侧具有焊接凸点；焊接凸点与RDL布线层耦接。如此，当双面封装结构 的其中一面需要封装至少两个芯片(如第一芯片和第二芯片)时，可以通过堆叠的方式进行封装，从而降低芯片封装结构的横向尺寸，提高芯片封装结构中器件的集成度。
结合第一方面，一种可能的设计方式中，第二塑封层可以包括第二内部塑封层和第二外部塑封层。第二内部塑封层用于对第一芯片包覆塑封。第二外部塑封层用于对第二芯片包覆塑封。第一导体柱包括第一内侧导体柱和第一外侧导体柱。第一内侧导体柱位于第二内部塑封层内。第一外侧导体柱位于第二外部塑封层内。第一内侧导体柱与第一外侧导体柱相耦接。如此，在芯片封装结构的制作过程中，可以对第一芯片和第一内侧导体柱通过第二内部塑封层塑封；还可对第二芯片和第一外侧导体柱通过第二外部塑封层塑封。在完成第二内部塑封层的塑封时，不仅可以对第二内部塑封层进行减薄处理，还可以对第一芯片的衬底进行减薄处理，以降低第一芯片的厚度，从而降低整个芯片封装结构的厚度，提供芯片封装的集成度。
结合第一方面，一种可能的设计方式中，第一芯片和第二芯片之间可以通过贴片胶贴装。
结合第一方面，一种可能的设计方式中，上述基板内可以设置有接地层。第一塑封层的外表面设置有屏蔽层，屏蔽层与接地层耦接。如此，可以使基板内的接地层与屏蔽层之间形成法拉第笼结构，以对基板上的器件模组进行电磁屏蔽，提高芯片封装结构的性能。
结合第一方面，一种可能的设计方式中，屏蔽层的外侧还可以设置有第三塑封层；第三塑封层远离屏蔽层的一侧贴装有天线结构。第一塑封层内设置有第二导体柱；第三塑封层内设置有第三导体柱。第二导体柱的第一端与基板耦接，第二导体柱的第二端与第三导体柱的第一端耦接，第三导体柱的第二端与天线结构耦接。如此，可以利用封装天线(antenna in package，AIP)技术对天线结构进行封装，提高芯片的集成度，满足芯片模组小型化的要求。
结合第一方面，一种可能的设计方式中，天线结构与第三塑封层之间设置有第一介质层。制作时，可以先在第三塑封层远离基板的一面制作第一介质层，在第一介质层上更容易通过溅射种子层、图形转移、电镀和蚀刻等工艺实现天线结构的制作，从而提高芯片封装结构的稳定性和可靠性。
结合第一方面，一种可能的设计方式中，第二塑封层与RDL布线层之间设置有第二介质层；第二介质层靠近第一导体柱的位置处设置有第一通孔结构，第一导体柱通过第一通孔结构与RDL布线层连接。制作时，可以先在第二塑封层远离基板的一面制作第二介质层，在第二介质层上更容易通过溅射种子层、图形转移、电镀和蚀刻等工艺实现RDL布线层的制作，从而提高芯片封装结构的稳定性和可靠性。
第二方面，本申请提供一种电子设备。该电子设备包括外接部件以及与外接部件相耦接的至少一个如上第一方面任一种可能的芯片封装结构。
可选地，上述外接部件包括封装基板、转接板，或者，扇出型的至少一层重布线层中的至少一种。
第三方面，本申请提供一种芯片封装结构的制作方法。该制作方法包括：在基板的第一面上设置器件模组，使器件模组与基板耦接。在基板的第一面上设置第一塑封层，使器件模组被第一塑封层包覆塑封。在基板的第二面上设置第一芯片和第一导体 柱，使第一芯片和第一导体柱均与基板耦接。在基板的第二面上设置第二塑封层，使第一芯片和第一导体柱被第二塑封层包覆塑封。在第二塑封层远离基板的一侧制作RDL布线层，且在RDL布线层上引出外部焊接管脚。
结合第三方面，一种可能的设计方式中，上述方法还可以包括：在第一芯片远离基板的一侧设置第二芯片，第二芯片远离第一芯片的一侧具有焊接凸点；焊接凸点与RDL布线层耦接。
结合第三方面，一种可能的设计方式中，在基板的第二面上设置第一芯片和第一导体柱，包括：在基板的第二面上设置第一芯片和第一内侧导体柱，使第一芯片和第一导体柱均与基板耦接。在第一内侧导体柱上焊接第一外侧导体柱。在基板的第二面上设置第二塑封层，包括：在基板的第二面上设置第二内部塑封层，使第一芯片和第一内侧导体柱被第二内部塑封层包覆塑封。在第二内部塑封层远离基板的一面上设置第二外部塑封层，使第二芯片和第一外侧导体柱被第二外部塑封层包覆塑封。
结合第三方面，一种可能的设计方式中，方法还可以包括：在第一塑封层远离基板的一面制作屏蔽层。
结合第三方面，一种可能的设计方式中，方法还可以包括：在基板的第一面上焊接第二导体柱。
结合第三方面，一种可能的设计方式中，上述方法还可以包括：在第二导体柱远离基板的一端焊接第三导体柱。在屏蔽层远离基板的一侧设置第三塑封层，使屏蔽层和第三导体柱被第三塑封层包覆塑封。在第三塑封层远离屏蔽层的一侧贴装天线结构，使天线结构与第三导体柱耦接。
可以理解地，上述提供的任一种芯片封装结构的制作方法、电子设备等，均可以由上文所提供的对应的芯片封装结构来实现，或与上文所提供的对应的芯片封装结构相关联，因此，其所能达到的有益效果可参考上文所提供的芯片封装结构中的有益效果，此处不再赘述。
附图说明
图1为本申请实施例提供的一种电子设备的结构示意图；
图2为本申请实施例提供的芯片封装结构的结构示意图一；
图3为本申请实施例提供的芯片封装结构的制作方法的流程图一；
图4为执行图3中的S301形成的结构示意图；
图5为执行图3中的S302形成的结构示意图；
图6为执行图3中的S303形成的结构示意图；
图7为执行图3中的S304形成的结构示意图；
图8为执行图3中的S305形成的结构示意图；
图9为本申请实施例提供的芯片封装结构的结构示意图二；
图10为执行图3中的S303形成的另一种结构示意图；
图11为执行图3中的S304形成的另一种结构示意图；
图12为执行图3中的S305形成的另一种结构示意图；
图13为本申请实施例提供的芯片封装结构的结构示意图三；
图14为执行图3中的S303和S304形成的另一种结构示意图；
图15为本申请实施例提供的芯片封装结构的结构示意图四；
图16为本申请实施例提供的芯片封装结构的结构示意图五；
图17为本申请实施例提供的芯片封装结构的制作方法的流程图二；
图18为执行图17中的S1701形成的一种结构示意图；
图19为执行图17中的S1702形成的一种结构示意图；
图20为执行图17中的S1703和S1704形成的一种结构示意图；
图21为执行图17中的S1705形成的一种中间结构示意图；
图22为执行图17中的S1705形成的一种结构示意图；
图23为执行图18中的S1706、S1707和S1708形成的结构示意图；
图24为本申请实施例提供的另一种电子设备的结构示意图。
附图标记：01-电子设备；10-外接部件；20-芯片封装结构；101-基板；1011-接地层；1012-焊盘；1013-基板的第一面；1014-基板的第二面；102-器件模组；1021-WB芯片；1022-焊接芯片；1023-无源器件；103-第一芯片；1031-芯片焊球；104-第一塑封层；105-第二塑封层；1051-第二内部塑封层；1052-第二外部塑封层；106-第一导体柱；1061-第一内侧导体柱；1062-第一外侧导体柱；107-RDL布线层；108-介质层；1081-第一互连孔；109-外部焊接管脚；201-第二芯片；2011-焊接凸点；202-屏蔽层；203-第三塑封层；204-天线结构；205-第二导体柱；206-第三导体柱；207-介质层。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
以下，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
此外，本申请中，“上”、“下”等方位术语是相对于附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件所放置的方位的变化而相应地发生变化。
在本申请中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“耦接”可以是实现信号传输的电性连接的方式。“耦接”可以是直接的电性连接，也可以通过中间媒介间接电性连接。
本申请实施例提供一种的电子设备。该电子设备包括手机(mobile phone)、平板电脑(pad)、电脑、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备等电子产品。本申请实施例对上述电子设备的具体形式不做特殊限制。
如图1所示，上述电子设备01包括外接部件10以及与该外接部件10相耦接的至少一个芯片封装结构20。其中，上述外接部件10可以包括封装基板、硅基转接板(interposer)以及扇出型(integrated fan-out，InFO)的至少一层重布线层(redistribution layer，RDL)中的至少一种。
上述芯片封装结构20可以包括多个芯片或器件模组。该芯片封装结构20中的芯片可以为逻辑芯片，也可以为存储芯片。芯片封装结构20可以设置如图1所示的焊球阵列(ball grid array，BGA)，或者多个阵列排布的铜柱凸块(copper pillar bump)，用于与外接部件10相耦接。
此外，电子设备01还包括印刷电路板(printed circuit boards，PCB)。上述外接部件10还可以通过电连接件(如BGA焊球阵列)与PCB相耦接。在此情况下，上述芯片封装结构20可以通过外接部件10与PCB上其他芯片或者芯片封装结构实现信号传输。
以下对上述芯片封装结构20进行说明。
在本申请的一些实施例中，如图2所示，上述芯片封装结构20可以包括基板101、第一芯片103、器件模组102、第一塑封层104和第二塑封层105。其中，基板101是芯片封装的载体，基板101中包括一个或多个布线层，可以对基板101上设置的多个芯片提供电连接，以实现封装后芯片的功能。器件模组102可以包括无源器件1023、打线(wire bonding，WB)芯片1021以及焊接芯片1022的一种或多种，还可以包括已经完成封装的球珊阵列封装(ball grid array，BGA)器件、栅格阵列封装(land grid array，LGA)器件、或者方形扁平无引脚封装(quad flat no-leads package，QFN)器件，本申请实施例不做特殊限制。
示例性地，如图2所示，上述器件模组102耦接于上述基板101的第一面1013，且被第一塑封层104包覆塑封。该器件模组102可以包括无源器件1023、WB芯片1021以及焊接芯片1022。应理解，无源器件1023可以通过表面贴装技术(surface mounted technology，SMT)实现与基板101相耦接。WB芯片1021可以指在芯片封装时，通过金属丝线将芯片的电路结构耦合至基板101的芯片。也就是说，WB芯片1021可以通过金属丝线(wirebond)与基板101耦接。焊接芯片1022可以指在芯片封装时，通过焊接(如焊盘和焊球)的方式将芯片的电路结构耦合至基板101的芯片。也就是说，焊接芯片1022可以通过焊接的方式与基板101相耦接。
上述器件模组102耦接至基板101之后，可以通过第一塑封层104实现该器件模组102中各器件或芯片的包裹，以实现不同器件或芯片之间的隔离以及器件或芯片与外部器件的隔离。该第一塑封层104的材质可以为树脂和填料混合而成的热固型材料，其中树脂可以为环氧树脂等树脂材料，填料可以为氧化硅(SiO2)或氮化硼(BN)等无机材料，填料可以调整树脂的特性，实现高导热、高熔点、低热膨胀系数(coefficient of thermal expansion，CTE)的材料特性。当然，第一塑封层104的材质也可以为其他类型的材料，如陶瓷或玻璃等，本申请实施例不做特殊限制。
上述第一芯片103耦接于上述基板101的第二面1014，且被第二塑封层105包覆塑封。该第一芯片103可以为焊接芯片1022，并通过焊接(如焊盘、焊球)的方式耦接至上述基板101。例如，如图2所示，基板101远离器件模组102的一面设置有多个焊盘1012，该第一芯片103通过多个芯片焊球1031焊接至基板101上的多个焊盘1012，从而实现第一芯片103与基板101相耦接。
为了使芯片封装结构20具有用于与外接部件相耦接的焊球阵列，或多个阵列排布的铜柱凸块。在第二塑封层105远离基板101的一侧设置有RDL布线层107，该RDL 布线层107可以用于引出外部焊接管脚109。该外部焊接管脚109可以是如图2所示的BGA焊球阵列，也可以是LGA连接触点，也可以是多个阵列排布的铜柱凸块，本申请实施例不做特殊限制。
在上述芯片封装结构20中，RDL布线层107引出的外部焊接管脚109可以与图1所示的外接部件10实现信号连接。为了使外接部件10能够与芯片封装结构20内部的芯片结构(如第一芯片或器件模组)形成信号连接，则RDL布线层107引出的外部焊接管脚109需要与芯片封装结构20中的基板101实现信号连接。
在此情况下，可以通过铜柱实现RDL布线层107与基板101的信号连接。具体地，可以在第二塑封层105内设置有第一导体柱106，且第一导体柱106的第一端与基板101耦接，第一导体柱106的第二端与上述RDL布线层107耦接。其中，第一导体柱106可以为设置在第二塑封层105内部的铜柱。也即，铜柱的第一端与基板101相耦接，铜柱的第二端与RDL布线层107，从而实现RDL布线层107与基板101的信号连接。
应理解，本申请实施例中的导体柱(如第一导体柱106)是由金属导电材料制成的柱体结构，如采用铜、镍、钨等金属导电材料。导体柱的结构可以是圆柱、三棱柱、圆台状柱体结构等任意柱体结构，本申请实施例不做特殊限制。
如此一来，该芯片封装结构20中采用双面封装结构，该双面封装结构中，在封装第一芯片103的第二塑封层105内设置第一导体柱106，在第二塑封层105远离基板101的一侧设置RDL布线层107。该RDL布线层107用于引出外部焊接管脚109，作为引出I/O管脚。第一导体柱106分别与基板101和RDL布线层107相耦接，使得RDL布线层107上的引出I/O管脚能够与基板101实现信号连接，从而在提高芯片封装结构的集成度的基础上，使该芯片封装结构能够适用更多的应用场景，进而提高对引出I/O管脚数量具有更高要求的电子设备的小型化竞争力。
需要说明的是，RDL布线层107可以包括一层布线层，也可以包括多个层叠设置的布线层，本申请实施例不做特殊限制。当RDL布线层107包括多个层叠设置的布线层时，相邻的布线层之间可以通过互连结构互连，使得基板101与RDL布线层107上的引出焊接管脚109信号连接。
应理解，上述芯片(如第一芯片103、WB芯片1021、焊接芯片1022)可以包括衬底和设置与衬底上的电路结构。其中衬底可以为玻璃衬底、非晶硅(amorphous silicon，a-Si)衬底、或者碳化硅(SiC)衬底等，本申请实施例不做特殊限制。
此外，为了便于RDL布线层107的制作，提高RDL布线层107与第二塑封层105之间的结合力，提高整个芯片封装结构20的可靠性，在第二塑封层105与RDL布线层107之间设置有一介质层108(即第二介质层)。该介质层108的材质可以是聚酰亚胺(polyimide，PI)、苯并环丁烯(benzocyclobutene，BCB)等绝缘材料。为了实现RDL布线层107与第一导体柱106的互连，介质层108靠近第一导体柱106的位置处设置有第一互连孔1081。第一互连孔1081内可以填充金属材料(如铜、镍等)，从而使得第一导体柱106通过第一互连孔1081与RDL布线层107耦接。
以下对图2所示的芯片封装结构20的制作方法进行举例说明。如图3所示，该芯片封装结构的制作方法，包括：
S301，在基板101的第一面1013上设置器件模组102，使该器件模组102与基板101耦接。
示例性地，如图4所示，对于SMT器件(如无源器件1023)，可以在基板101的第一面1013上印刷锡膏，使SMT器件贴装在基板101的第一面1013上，并与基板101耦接。对于WB芯片1021，可以先将该芯片的衬底朝向基板101，并采用贴片胶或点胶的方式使WB芯片1021贴装在基板101的第一面1013上，然后再通过金属丝线将WB芯片1021的电路结构与基板101相连接，以实现WB芯片1021与基板101的互连以及信号传输。对于焊接芯片1022，可以将焊接芯片1022的焊接面(即设置芯片焊球的一面)朝向基板101，并且采用回流焊接、激光焊接等方式将焊接芯片1022焊接至基板101，从而实现焊接芯片1022与基板101的互连以及信号传输。
S302，在基板101的第一面1013上设置第一塑封层104，使该器件模组102被第一塑封层104包覆塑封。
示例性地，如图5所示，在实现了器件模组102与基板101之间的贴装或互连后，可以使用等离子(plasma)工艺对基板101或器件模组102进行处理。经过plasma处理后，可以采用塑封工艺对器件进行塑封包裹，并且器件与器件之间的间隙、器件与基板101之间的间隙均需实现塑封包裹。
S303，在基板101的第二面1014上设置第一芯片103和第一导体柱106，使第一芯片103和第一导体柱106均与基板101耦接。
示例性地，如图6所示，在基板101的第二面1014上，对于第一芯片103，可以将第一芯片103的焊接面朝向基板101，并且采用回流焊接、激光焊接等方式将第一芯片103焊接至基板101，从而实现第一芯片103与基板101的互连以及信号传输。
如图2所示，第一导体柱106可以为铜柱结构，在基板101的第二面1014上还可以将铜柱结构，采用回流焊接或激光焊接等方式焊接至基板101，从而实现第一导体柱106的第一端与基板101耦接。
S304，如图7所示，在基板101的第二面1014上设置第二塑封层105，使第一芯片103和第一导体柱106被第二塑封层105包覆塑封。
示例性地，在实现了第一芯片103和第一导体柱106与基板101相耦接后，可以采用塑封工艺对第一芯片103和第一导体柱106进行塑封包裹，形成第二塑封层105。其中，塑封时，需将第一芯片103和第一导体柱106完全包裹在塑封料的内部。也就是说，塑封料的高度需超出第一芯片103和第一导体柱106的高度。
需要说明的是，为了降低整个芯片封装结构20的厚度，第一导体柱106的高度可以略高于第一芯片103的厚度，甚至与第一芯片103的厚度相等，本申请实施例不做特殊限制。
S305，在第二塑封层105远离基板101的一侧制作RDL布线层107，且在RDL布线层107上引出外部焊接管脚109。
示例性地，在完成了第二塑封层105对第一芯片103和第一导体柱106的塑封包裹后，为了露出第一导体柱106，可以通过减薄几台对第二塑封层105进行减薄处理，从而裸露出第一导体柱106。
裸露出第一导体柱106后，可以在第二塑封层105远离基板101的一侧采用喷涂 聚酰亚胺等绝缘材料制作形成介质层108，然后在介质层108正对第一导体柱106的位置处采用采用光刻工艺(包括掩膜、曝光、显影以及刻蚀等工艺)形成第一互连孔1081，在第一互连孔1081中填充导电材料(如铜、镍等)。最后，可以在介质层108远离第二塑封层105的一侧制作RDL布线层107，如图8所示。
在制作RDL布线层107时，可以采用溅射种子层、RDL图形转移、电镀、刻蚀等工艺步骤实现。RDL布线层107可以为一层，也可以为多层互连结构，本申请实施例不做特殊限制。其中，种子层(seed layer)，是一层通过化学镀、溅射、或蒸镀等工艺制作在基材表面的很薄的金属层，作为RDL布线层107制作过程中执行电镀工艺的起始金属层，也叫籽晶层。种子层的材料可以为铜、镍等导电金属。RDL图形转移可以通过光刻胶或光敏感光膜等材料经过曝光、显影等工艺实现。
在完成了RDL布线层107的制作之后，可以使上述芯片封装结构20的引出I/O管脚扇出到芯片封装结构20的一侧的整个面上，从而可以实现更多的引出外部焊接管脚109(如焊球)，可以适用于该芯片封装结构20中的芯片/器件模组102与外部器件互连链路较多的场景。
在本申请的另一些实施例中，如图9所示，上述芯片封装结构20还可以包括第二芯片201。该第二芯片201堆叠于上述第一芯片103远离基板101的一侧，并且也可以被第二塑封层105包覆塑封。如此，当双面封装结构的其中一面需要封装至少两个芯片(如第一芯片103和第二芯片201)时，可以通过堆叠的方式进行封装，从而降低芯片封装结构的横向尺寸，提高芯片封装结构中器件的集成度。
需要说明的是，上述第二芯片201可以为带焊接凸点(bump)2011的芯片。为了使第二芯片201能够与基板101实现信号连接，如图9所示，可以将第二芯片201与第一芯片103背靠背进行贴装，即可以将第一芯片103的衬底和第二芯片201的衬底，通过贴片胶实现贴装。也就是说，在贴装完成后，第二芯片201远离第一芯片103的一侧是具有焊接凸点2011的。该第二芯片201的焊接凸点2011可以与RDL布线层107相耦接。当第二芯片201的焊接凸点2011与RDL布线层107相耦接后，由于RDL布线层107通过第一导体柱106与基板101实现信号连接，从而使得第二芯片201也可以与基板101实现信号连接。
在此情况下，在上述包括第二芯片201的芯片封装结构20在制作过程中，可以在上述S303步骤中，完成了第一芯片103焊接至基板101后，在第一芯片103的背面(即第一芯片103远离基板101的一面)上点胶，然后将第二芯片201的衬底朝向第一芯片103，使第二芯片201贴装到第一芯片103上，以形成如图10所示的结构。
在执行上述S304步骤时，还需要对第二芯片201进行塑封包裹，如图11所示。由于第二芯片201具有焊接凸点2011，第二塑封层105中塑封料的高度，需超出第一导体柱106的高度，以及需超出第一芯片103和第二芯片201的厚度之和。应理解，为降低整个芯片封装结构20的厚度，第一导体柱106的高度可以略高于第一芯片103和第二芯片201的厚度之和，例如，第一导体柱106的高度可以比第一芯片103和第二芯片201的厚度之和高0至200微米(um)，或者第一导体柱106的高度可以与第一芯片103和第二芯片201的厚度相等。
在执行上述S305步骤时，为了使第二芯片201的焊接凸点2011可以与RDL布线 层107相耦接，需要对第二塑封层105进行减薄，并裸露出第二芯片201的焊接凸点2011以及第一导体柱106。如图12所示，在第二塑封层105远离基板101的一侧制作形成的介质层108上，对应第二芯片201的焊接凸点2011的位置处还需采用光刻工艺形成第一互连孔，并在互连孔内填充导电材料，以使第二芯片201与RDL布线层107形成互连，从而在RDL布线层107通过第一导体柱106与基板101形成互连的情况下，第二芯片201也可以与基板101形成互连而实现信号连接。
在本申请的另一些实施例中，如图13所示所示的芯片封装结构20中，图9所示的第二塑封层105可以包括第二内部塑封层1051和第二外部塑封层1052。其中，第二内部塑封层1051可以用于对第一芯片103包覆塑封。第二外部塑封层1052可以用于对第二芯片201包覆塑封。图9所示的第一导体柱106也可以分为第一内侧导体柱1061和第一外侧导体柱1062。第一内侧导体柱1061位于所述第二内部塑封层1051内。第一外侧导体柱1062位于第二外部塑封层1052内。第一内侧导体柱1061与第一外侧导体柱1062相耦接。
需要说明的是，在图9所示的芯片封装结构20中，通过第二塑封层105对第一芯片103、第二芯片201、第一导体柱106整体塑封，塑封后的高度至少是第一芯片和第二芯片的厚度之和。然而，在图13所示的芯片封装结构20中，第一芯片103和第一内侧导体柱1061由第二内部塑封层1051包覆塑封，塑封后可以对第一芯片103的衬底、第一内侧导体柱1061以及第二内部塑封层1051整体减薄，从而降低第一芯片103的厚度。相应地，第二芯片201、第一外侧导体柱1062由第二外部塑封层1052包覆塑封。塑封完成后，第二内部塑封层1051和第二外部塑封层1052的高度为减薄后的第一芯片103的厚度与第二芯片201的厚度之和，从而可以降低芯片封装结构20的厚度。
在此情况下，在对图13所示的芯片封装结构20的制作过程中，可以先执行上述S303步骤，在基板101的第二面1014上设置第一芯片103和第一内侧导体柱1061，然后执行上述S304步骤，如图14中的(a)所示，对第一芯片103和第一内侧导体柱1061完成塑封包裹，形成第二内部塑封层1051。在形成第二内部塑封层1051后，可以对形成的第二内部塑封层1051进行减薄处理。在减薄处理的过程中，不仅可以对第二内部塑封层1051进行减薄处理，还可以对第一芯片103的衬底进行减薄处理，以降低第一芯片103的厚度，并裸露出第一内侧导体柱1061。
在完成对第二内部塑封层1051的减薄处理之后，如图14中的(b)所示，可以在第一芯片103的背面(即第一芯片103的衬底面)贴装第二芯片201，并且在第一内侧导体柱1061上焊接铜柱，作为第一外侧导体柱1062。在完成了第一外侧导体柱1062的焊接和第二芯片201的贴装后，可以执行上述S304步骤中的类似方法，对第二芯片201和第一外侧导体柱1062进行塑封包裹，以形成第二外部塑封层1052，如图14中的(c)所示。接着，可以对第二外部塑封层1052进行减薄处理，并裸露出第二芯片201的焊接凸点以及第一外侧导体柱1062。
此外，在上述图2、图9和图13所示的芯片封装结构20中，基板101内还设置有接地层1011。在第一塑封层104的外表面设置有屏蔽层202。该屏蔽层202与基板101内的接地层1011实现耦接，从而使基板101内的接地层1011与屏蔽层202之间 形成法拉第笼结构，以对基板101上的器件模组102进行电磁屏蔽。具体地，如图2、图9和图13所示，在基板101的侧面上有从基板101的内部延伸至基板101的边缘的接地网络层(即接地层1011)，在第一塑封层104的外表面形成的屏蔽层202沿着第一塑封层104的外表面延伸至基板101的接地层1011处，并与接地层1011耦接。
在此情况下，屏蔽层202的制作可以采用溅射工艺实现，屏蔽层202的结构可以为三层金属薄膜结构，例如不锈钢层(steel use stainless，SUS)、铜层以及不锈钢层SUS三层结构。当然，屏蔽层202的制作也可以采用喷涂工艺实现，利用喷涂工艺制作的屏蔽层202可以采用导电银浆等屏蔽材料，本申请实施例对屏蔽层202的材质和制作方法不做特殊限制。
在本申请的另一些实施例中，可以利用封装天线(antenna in package，AIP)技术对天线进行封装，例如对于射频集成电路(radio frequency intergreted circuit，RFIC)射频前端(radio frequency front end，RFFE)器件，以及天线(antenna，ANT)结构可以封装到一个芯片封装结构20中，以提高芯片的集成度，满足芯片模组小型化的要求。
下面以天线结构204封装至图2或图9所示的芯片封装结构20为例进行说明。示例性地，如图15和图16所示，在图2和图9所述的芯片封装结构20的基础上，可以在屏蔽层202的外侧设置第三塑封层203，使第三塑封层203将整个屏蔽层202进行包覆塑封。对于天线结构204，可以将天线结构204贴装在第三塑封层203远离上述屏蔽层202的一侧。其中，屏蔽层202也可以作为天线结构204的接地参考面。
为了使天线结构204与基板101之间形成馈电连接，可以在上述第一塑封层104内设置第二导体柱205，可以在上述第三塑封层203内设置第三导体柱206。其中，第二导体柱205的第一端与基板101耦接，第二导体柱205的第二端与第三导体柱206的第一端耦接，第三导体柱206的第二端与天线结构204耦接。应理解，第二导体柱205和第三导体柱206均可以为铜柱结构。
在此情况下，制作该包括天线结构204的芯片封装结构20的方法，如图17所示，可以包括：
S1701，在基板101的第一面1013上设置器件模组102，并焊接第二导体柱205，使该器件模组102和第二导体柱205均与基板耦接。
示例性地，可以在执行上述图3中的S301步骤时，将第二导体柱205焊接至基板101的第一面1013上，如图18所示。
S1702，在基板101的第一面1013上设置第一塑封层104，使该器件模组102和第二导体柱205被第一塑封层104包覆塑封。
示例性地，可以在执行上述S302步骤，将器件模组102和第二导体柱205均塑封在第一塑封层104内，如图19所示。
S1703，在基板101的第二面1014上设置第一芯片103和第一导体柱106，使第一芯片103和第一导体柱106均与基板101耦接。
S1704，在基板101的第二面1014上设置第二塑封层105，使第一芯片103和第一导体柱106被第二塑封层105包覆塑封。
在第一塑封层104制作完成之后，可以执行上述S1703和S1704步骤，形成如图 20中的(a)或图20中的(b)所示的结构，具体的制作方法可以参考上述S303和S304中的描述，此处不再赘述。
S1705，在第一塑封层远离基板的一面制作屏蔽层。
在形成如图20中的(a)或图20中的(b)所示的结构后，可以采用减薄几台对第一塑封层104进行减薄处理，使第二导体柱205的第二端裸露出来。然后可以通过分板机从第一塑封层104的上表面(即远离基板101的一面)向基板101的第二面1014切割形成L形区域，并裸露出基板101上的接地网络(即接地层1011)，如图21中的(a)或图21中的(b)所示。接着，可以在经过减薄后的第一塑封层104的表面(即远离基板101的一面)，以及切割形成的L形区域制作屏蔽层202，最终可以形成L形结构的屏蔽层200，如图22中的(a)或图22中的(b)所示。屏蔽层202的制作可以采用溅射工艺或喷涂工艺实现，屏蔽层202的材质可以为三层金属薄膜结构，也可以是导电银浆等屏蔽材料。
需要说明的是，在此芯片封装结构20中，屏蔽层202的制作需要裸露出第二导体柱205，也就是说，在第二导体柱205的第二端上以及第二导体柱205的第二端周围的部分不需要制作屏蔽层202，以便实现天线结构204通过第二导体柱205与第三导体柱206与基板101实现信号连接。
S1706，在第二导体柱远离基板的一端焊接第三导体柱。
在屏蔽层202制作完成之后，如图23中的(a)或图23中的(b)所示，可以在裸露出的第二导体柱205的第二端上焊接第三导体柱206。第三导体柱206可以通过回流焊接或激光焊接的方式进行焊接。
S1707，在屏蔽层远离基板的一侧制作第三塑封层，使屏蔽层和第三导体柱通过第三塑封层包覆塑封。
如图23中的(a)或图23中的(b)所示，在第三导体柱206焊接到第二导体柱205之后，可以在屏蔽层202上面(即屏蔽层202远离基板101的一面)上进行二次塑封，形成第三塑封层203，并且使第三塑封层203可以将整个屏蔽层202以及整个第三导体柱206覆盖。
S1708，在第三塑封层远离屏蔽层的一侧贴装天线结构，使天线结构与第三导体柱耦接。
如图23中的(a)或图23中的(b)所示，在第三塑封层203制作完成之后，可以采用减薄几台对第三塑封层203进行减薄处理，使第三导体柱206的第二端裸露出来。接着，可以在第三塑封层203的表面(即第三塑封层203远离屏蔽层202的一面)制作天线结构204。天线结构204可以通过溅射种子层、图形转移、电镀、蚀刻等工艺实现。
此外，在图15和图16所示的芯片封装结构20中，天线结构204与第三塑封层203之间设置有介质层207(即第一介质层)。相比于第三塑封层203，介质层207能够提高天线结构204与第三塑封层203之间的结合力，在介质层207上更容易通过溅射种子层、图形转移、电镀和蚀刻等工艺实现天线结构204的制作，从而提高芯片封装结构的稳定性和可靠性。
S1709，在第二塑封层105远离基板101的一侧制作RDL布线层107，且在RDL 布线层107上引出外部焊接管脚109。
在上述天线结构204制作完成形成图23中的(a)或图23中的(b)的结构后，可以在执行上述S1709步骤完成RDL布线层的制作，以及外部焊接管脚的制作，该S1709步骤可以参考上述S305步骤，此处不再赘述。
示例性地，图24为本申请实施例提供的另一种电子设备的结构示意图。该电子设备可以是终端设备，也可以是基站。如图24所示，该电子设备可包括应用子系统，内存(memory)，大容量存储器(massive storge)，基带子系统，射频集成电路(radio frequency intergreted circuit，RFIC)，射频前端(radio frequency front end，RFFE)器件，以及天线(antenna，ANT)，这些器件可以通过各种互联总线或其他电连接方式耦合。
图24中，ANT_1表示第一天线，ANT_N表示第N天线，N为大于1的正整数。Tx表示发射路径，Rx表示接收路径，不同的数字表示不同的路径。FBRx表示反馈接收路径，PRx表示主接收路径，DRx表示分集接收路径。HB表示高频，LB表示低频，两者是指频率的相对高低。BB表示基带。应理解，图24中的标记和组件仅为示意目的，仅作为一种可能的实现方式，本申请实施例还包括其他的实现方式。
其中，应用子系统可作为电子设备的主控制系统或主计算系统，用于运行主操作系统和应用程序，管理整个电子设备的软硬件资源，并可为用户提供用户操作界面。应用子系统可包括一个或多个处理核心。此外，应用子系统中也可包括与其他子系统(例如基带子系统)相关的驱动软件。基带子系统也可包括以及一个或多个处理核心，以及硬件加速器(hardware accelerator，HAC)和缓存等。
图24中，RFFE器件，RFIC 1(以及可选的RFIC 2)可以共同组成射频子系统。射频子系统可以进一步分为射频接收通道(RF receive path)和射频发射通道(RF transmit path)。射频接收通道可通过天线接收射频信号，对该射频信号进行处理(如放大、滤波和下变频)以得到基带信号，并传递给基带子系统。射频发射通道可接收来自基带子系统的基带信号，对基带信号进行射频处理(如上变频、放大和滤波)以得到射频信号，并最终通过天线将该射频信号辐射到空间中。具体地，射频子系统可包括天线开关，天线调谐器，低噪声放大器(low noise amplifier，LNA)，功率放大器(power amplifier，PA)，混频器(mixer)，本地振荡器(local oscillator，LO)、滤波器(filter)等电子器件，这些电子器件可以根据需要集成到一个或多个芯片中。天线有时也可以认为是射频子系统的一部分。
基带子系统可以从基带信号中提取有用的信息或数据比特，或者将信息或数据比特转换为待发射的基带信号。这些信息或数据比特可以是表示语音、文本、视频等用户数据或控制信息的数据。例如，基带子系统可以实现诸如调制和解调，编码和解码等信号处理操作。对于不同的无线接入技术，例如5G NR和4G LTE，往往具有不完全相同的基带信号处理操作。因此，为了支持多种移动通信模式的融合，基带子系统可同时包括多个处理核心，或者多个HAC。
此外，由于射频信号是模拟信号，基带子系统处理的信号主要是数字信号，电子设备中还需要有模数转换器件。模数转换器件包括将模拟信号转换为数字信号的模数转换器(analog to digital converter，ADC)，以及将数字信号转换为模拟信号的数模 转换器(digital to analog converter，DAC)。本申请实施例中，模数转换器件可以设置在基带子系统中，也可以设置在射频子系统中。
应理解，本申请实施例中，处理核心可表示处理器，该处理器可以是通用处理器，也可以是为特定领域设计的处理器。例如，该处理器可以是中央处理单元(center processing unit，CPU)，也可以是数字信号处理器(digital signal processor，DSP)。该处理器也可以是微控制器(micro control unit，MCU)，图形处理器(graphics processing unit，GPU)、图像信号处理器(image signal processing，ISP)，音频信号处理器(audio signal processor，ASP)，以及为人工智能(artificial intelligence，AI)应用专门设计的处理器。AI处理器包括但不限于神经网络处理器(neural network processing unit，NPU)，张量处理器(tensor processing unit，TPU)以及被称为AI引擎的处理器。
硬件加速器可用于实现一些处理开销较大的子功能，如数据包(data packet)的组装和解析，数据包的加解密等。这些子功能采用通用功能的处理器也可以实现，但是因为性能或成本的考量，采用硬件加速器可能更加合适。因此，硬件加速器的种类和数目可以基于需求来具体选择。在具体的实现方式中，可以使用现场可编程门阵列(field programmable gate array，FPGA)和专用集成电路(application specified intergated circuit，ASIC)中的一种或组合来实现。当然，硬件加速器中也可以使用一个或多个处理核心。
存储器可分为易失性存储器(volatile memory)和非易失性存储器(non-volatile memory，NVM)。易失性存储器是指当电源供应中断后，内部存放的数据便会丢失的存储器。目前，易失性存储器主要是随机存取存储器(random access memory，RAM)，包括静态随机存取存储器(static RAM，SRAM)和动态随机存取存储器(dynamic RAM，DRAM)。非易失性存储器是指即使电源供应中断，内部存放的数据也不会因此丢失的存储器。常见的非易失性存储器包括只读存储器(read only memory，ROM)、光盘、磁盘以及基于闪存(flash memory)技术的各种存储器等。通常来说，内存可以选用易失性存储器，大容量存储器可以选用非易失性存储器，例如磁盘或闪存。
本申请实施例中，基带子系统和射频子系统共同组成通信子系统，为电子设备提供无线通信功能。通常，基带子系统负责管理通信子系统的软硬件资源，并且可以配置射频子系统的工作参数。基带子系统的一个或多个处理核心可以集成为一个或多个芯片，该芯片可称为基带处理芯片或基带芯片。类似地，RFIC可以被称为射频处理芯片或射频芯片。此外，随着技术的演进，通信子系统中射频子系统和基带子系统的功能划分也可以有所调整。例如，将部分射频子系统的功能集成到基带子系统中，或者将部分基带子系统的功能集成到射频子系统中。在实际应用中，基于应用场景的需要，电子设备可采用不同数目和不同类型的处理核心的组合。
本申请实施例中，射频子系统可包括独立的天线，独立的射频前端(RF front end，RFFE)器件，以及独立的射频芯片。射频芯片有时也被称为接收机(receiver)、发射机(transmitter)或收发机(transceiver)。天线、射频前端器件和射频处理芯片都可以单独制造和销售。当然，射频子系统也可以基于功耗和性能的需求，采用不同的器件或者不同的集成方式。例如，将属于射频前端的部分器件集成在射频芯片中，甚至将天线和射频前端器件都集成射频芯片中，该射频芯片也可以称为射频天线模组或 天线模组。
本申请实施例中，基带子系统可以作为独立的芯片，该芯片可被称调制解调器(modem)芯片。基带子系统的硬件组件可以按照modem芯片为单位来制造和销售。modem芯片有时也被称为基带芯片或基带处理器。此外，基带子系统也可以进一步集成在SoC芯片中，以SoC芯片为单位来制造和销售。基带子系统的软件组件可以在芯片出厂前内置在芯片的硬件组件中，也可以在芯片出厂后从其他非易失性存储器中导入到芯片的硬件组件中，或者还可以通过网络以在线方式下载和更新这些软件组件。
需要说明的是，上述电子设备中的天线、射频前端、以及RFIC可以通过上述图15和图16所示的芯片封装结构实现。也就是说，天线、射频前端以及RFIC可以封装到上述图15和图16所示的芯片封装结构中，以提高电子设备中各器件模组的集成度。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种芯片封装结构，其特征在于，包括：基板、第一芯片、器件模组、第一塑封层和第二塑封层；
    所述器件模组耦接于所述基板的第一面，且被所述第一塑封层包覆塑封；
    所述第一芯片耦接于所述基板的第二面，且被所述第二塑封层包覆塑封；
    所述第二塑封层远离所述基板的一侧设置有RDL布线层，所述RDL布线层用于引出外部焊接管脚；
    所述第二塑封层内设置有第一导体柱，且所述第一导体柱的第一端与所述基板耦接，所述第一导体柱的第二端与所述RDL布线层耦接。
  2. 根据权利要求1所述的芯片封装结构，其特征在于，所述器件模组包括无源器件、WB芯片以及焊接芯片的一种或多种。
  3. 根据权利要求1或2所述的芯片封装结构，其特征在于，所述芯片封装结构还包括第二芯片；所述第二芯片堆叠于所述第一芯片远离所述基板的一侧，且被所述第二塑封层包覆塑封；
    所述第二芯片远离所述第一芯片的一侧具有焊接凸点；所述焊接凸点与所述RDL布线层耦接。
  4. 根据权利要求3所述的芯片封装结构，其特征在于，所述第二塑封层包括第二内部塑封层和第二外部塑封层；所述第二内部塑封层用于对所述第一芯片包覆塑封；所述第二外部塑封层用于对所述第二芯片包覆塑封；
    第一导体柱包括第一内侧导体柱和第一外侧导体柱；所述第一内侧导体柱位于所述第二内部塑封层内；所述第一外侧导体柱位于所述第二外部塑封层内；所述第一内侧导体柱与所述第一外侧导体柱相耦接。
  5. 根据权利要求3或4所述的芯片封装结构，其特征在于，所述第一芯片和第二芯片之间通过贴片胶贴装。
  6. 根据权利要求1至5任一项所述的芯片封装结构，其特征在于，所述基板内设置有接地层；所述第一塑封层的外表面设置有屏蔽层，所述屏蔽层与所述接地层耦接。
  7. 根据权利要求6所述的芯片封装结构，其特征在于，所述屏蔽层的外侧还设置有第三塑封层；所述第三塑封层远离所述屏蔽层的一侧贴装有天线结构；
    所述第一塑封层内设置有第二导体柱；所述第三塑封层内设置有第三导体柱；
    所述第二导体柱的第一端与所述基板耦接，所述第二导体柱的第二端与所述第三导体柱的第一端耦接，所述第三导体柱的第二端与所述天线结构耦接。
  8. 根据权利要求7所述的芯片封装结构，其特征在于，所述天线结构与所述第三塑封层之间设置有第一介质层。
  9. 根据权利要求1至8任一项所述的芯片封装结构，其特征在于，所述第二塑封层与所述RDL布线层之间设置有第二介质层；所述第二介质层靠近所述第一导体柱的位置处设置有第一通孔结构，所述第一导体柱通过所述第一通孔结构与所述RDL布线层连接。
  10. 一种电子设备，其特征在于，包括外接部件以及与所述外接部件相耦接的至少一个如权利要求1至9任一项所述的芯片封装结构。
  11. 根据权利要求10所述的电子设备，其特征在于，所述外接部件包括封装基板、转接板，或者，扇出型的至少一层重布线层中的至少一种。
  12. 一种芯片封装结构的制作方法，其特征在于，包括：
    在基板的第一面上设置器件模组，使所述器件模组与所述基板耦接；
    在所述基板的第一面上设置第一塑封层，使所述器件模组被所述第一塑封层包覆塑封；
    在所述基板的第二面上设置第一芯片和第一导体柱，使所述第一芯片和所述第一导体柱均与所述基板耦接；
    在所述基板的第二面上设置第二塑封层，使所述第一芯片和所述第一导体柱被所述第二塑封层包覆塑封；
    在所述第二塑封层远离所述基板的一侧制作RDL布线层，且在所述RDL布线层上引出外部焊接管脚。
  13. 根据权利要求12所述的方法，其特征在于，所述方法还包括：
    在所述第一芯片远离所述基板的一侧设置第二芯片，所述第二芯片远离所述第一芯片的一侧具有焊接凸点；所述焊接凸点与所述RDL布线层耦接。
  14. 根据权利要求13所述的方法，其特征在于，所述在所述基板的第二面上设置第一芯片和第一导体柱，包括：
    在所述基板的第二面上设置第一芯片和第一内侧导体柱，使所述第一芯片和所述第一导体柱均与所述基板耦接；
    在所述第一内侧导体柱上焊接第一外侧导体柱；
    所述在所述基板的第二面上设置第二塑封层，包括：
    在所述基板的第二面上设置第二内部塑封层，使所述第一芯片和所述第一内侧导体柱被所述第二内部塑封层包覆塑封；
    在所述第二内部塑封层远离所述基板的一面上设置第二外部塑封层，使所述第二芯片和所述第一外侧导体柱被所述第二外部塑封层包覆塑封。
  15. 根据权利要求12至14任一项所述的方法，其特征在于，所述方法还包括：
    在所述第一塑封层远离基板的一面制作屏蔽层。
  16. 根据权利要求15所述的方法，其特征在于，其特征在于，所述方法还包括：
    在所述基板的第一面上焊接第二导体柱。
  17. 根据权利要求16所述的方法，其特征在于，所述方法还包括：
    在所述第二导体柱远离所述基板的一端焊接第三导体柱；
    在所述屏蔽层远离所述基板的一侧设置第三塑封层，使所述屏蔽层和所述第三导体柱被第三塑封层包覆塑封；
    在所述第三塑封层远离所述屏蔽层的一侧贴装天线结构，使所述天线结构与所述第三导体柱耦接。
PCT/CN2022/070373 2021-05-27 2022-01-05 芯片封装结构以及制作方法、电子设备 WO2022247294A1 (zh)

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