TWI673840B - 雙面扇出型系統級封裝結構 - Google Patents

雙面扇出型系統級封裝結構 Download PDF

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TWI673840B
TWI673840B TW107136429A TW107136429A TWI673840B TW I673840 B TWI673840 B TW I673840B TW 107136429 A TW107136429 A TW 107136429A TW 107136429 A TW107136429 A TW 107136429A TW I673840 B TWI673840 B TW I673840B
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chip
redistribution layer
memory
memory chip
package structure
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TW202017124A (zh
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潘吉良
李念庭
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力成科技股份有限公司
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Priority to CN201811228748.1A priority patent/CN111063663B/zh
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Abstract

本發明係關於一雙面扇出型系統級封裝結構，係包含一第一重佈線層、一第二重佈線層與設置在該第一及第二重佈線層之間之一晶片及一晶片組；其中該晶片電性連接該第一重佈線層並形成有矽穿孔，該第二重佈線層電性連接至該晶片的矽穿孔與該晶片組，該晶片組可透過該第二重佈線層及矽穿孔與該晶片及第一重佈線電性連接；如此，該晶片及晶片組之間的電性連接即可不必透過堆疊設置或使用矽中介板或其他封裝載板，進而能有效減低封裝結構的高度；此外，包覆該晶片及晶片組之封膠體使得第一重佈線層與第二重佈線層相互隔離，可有效避免晶片及晶片組之高速訊號彼此相互干擾。

Description

雙面扇出型系統級封裝結構
本發明係關於一種系統封裝結構，尤指一種雙面扇出型系統級封裝結構。
隨著電子裝置需要儲存及處理的資料量愈來愈大，其要求相關電子元件規格提升、數量也隨之增加，且必須設置在有限的空間內；為符合此要求，一種系統級封裝(System in Package,SiP)結構被提出，將相關功能的晶片整合於單一封裝結構，該系統級封裝結構包含有以下數種形式。
請參閱圖3所示，係為一種堆疊式封裝結構50(Package on Package；PoP)，於一下重佈線層51上電性連接有一邏輯晶片52，接著以第一封膠體53包覆該邏輯晶片52；之後，於該第一封膠體53及該邏輯晶片52上形成一上重佈線層54，將至少一記憶晶片55打線電性連接在該上重佈線層54之金屬接點541，再以第二封膠體56包覆該記憶晶片55；其中該上、下重佈線層54、51之間透過金屬柱57相互電性連接；若因應更大儲存空間需求，如圖4所示，則進一步於該記憶晶片55上再疊設其它記憶晶片55，惟該堆疊式封裝結構50’的高度會增加。
請參閱圖5所示，係為一種多晶片封裝結構60(Multi-Chip Package；MCP)係將一邏輯晶片61及至少一記憶晶片組62電性連接在一矽中介板63上，由於該矽中介板63之相鄰外接墊631間距過小，通常會進一步電性連接至一封裝用載板64上，該封裝用載板64的相鄰外接墊641的間距即符合電子元件之 相鄰外接墊的間距；如此，即可將該邏輯晶片61及該至少一記憶晶片組62同時封裝成單一電子元件。
上述無論是堆疊式封裝結構或多晶片封裝結構的高度都較高，對於輕薄電子裝置來說，電子元件設置空間的高度仍有限制，故而有必要進一步提出改良。
有鑑於前揭多晶片封裝結構的高度過高，本發明的主要發明目的係提供一種薄化之雙面扇出型多晶片封裝結構。
欲達上述目的所使用的主要技術手段係令該雙面扇出型多晶片封裝結構包含有：一第一重佈線層，係於一第一介電本體內形成有複數第一連接線，該第一介電本體的一側形成有複數內接點，另一相對側係形成有複數外接墊，並透過該些第一連接線與該些內接點電性連接；一邏輯晶片，係包含一第一主動面及一相對該第一主動面之一第一背面，該第一主動面係包含有複數接點；其中該些接點分別電性連接於該第一重佈線層的對應內接點，且該邏輯晶片形成有複數第一矽穿孔，各該第一矽穿孔的第一端係與對應的該接點電性連接，而各該第一矽穿孔的第二端係外露於該第一背面；至少一記憶晶片組，各該記憶晶片組係包含有：一控制晶片，係包含有一第二背面，該第二背面係固定在該第一重佈線層；以及複數記憶晶片，係堆疊設置於該控制晶片上，各該記憶晶片包含有複數第二矽穿孔，以與相鄰記憶晶片及該控制晶片電性連接；其中遠離該控制晶片的記憶晶片係包含有一第二主動面； 一封膠層，係形成於該第一重佈線層上並包覆該邏輯晶片及各該記憶晶片組；其中該邏輯晶片的各該第一矽穿孔的第二端及各該記憶晶片組中之該記憶晶片的第二主動面外露於該封膠體；以及一第二重佈線層，係共同形成於該封膠層、該邏輯晶片的第一背面及各該記憶晶片組中之該記憶晶片的第二主動面上，以與該邏輯晶片之各該第一矽穿孔的第二端及各該記憶晶片組中之該記憶晶片的第二主動面電性連接。
由上述說明可知，本發明的雙面扇出型多晶片封裝結構主要將不同功能的邏輯晶片的第一主動面及記憶晶片組中之該記憶晶片的第二主動面分別電性連接在不同位置的第一及第二重佈線層，再配合該邏輯晶片的矽穿孔，仍可將各該記憶晶片組中之該記憶晶片的第二主動面與該邏輯晶片及第一重佈線的對應內接點電性連接；如此，該邏輯晶片及記憶晶片組即可不必堆疊設置或使用矽中介板或其他封裝載板，能有效減低封裝結構的高度；此外，由於該邏輯晶片的第一主動面及記憶晶片組中之該記憶晶片的第二主動面分別電性連接在不同位置的第一及第二重佈線層，而封膠體使得第一重佈線層與第二重佈線層相互隔離，可有效避免邏輯晶片及記憶晶片組之高速訊號彼此相互干擾。
10、10a、10b‧‧‧系統級封裝結構
11‧‧‧第一重佈線層
111‧‧‧第一介電本體
112‧‧‧第一連接線
113‧‧‧外接墊
114‧‧‧內接點
12‧‧‧封膠體
13‧‧‧第二重佈線層
131‧‧‧第二介電本體
132‧‧‧第二連接線
14‧‧‧黏著層
20‧‧‧晶片
21‧‧‧第一主動面
211‧‧‧第一接點
212‧‧‧第二接點
22‧‧‧第一背面
23‧‧‧第一矽穿孔
231‧‧‧第一端
232‧‧‧第二端
30‧‧‧晶片組
301‧‧‧控制晶片
302‧‧‧記憶晶片
31‧‧‧第二主動面
32‧‧‧第二背面
33‧‧‧第二矽穿孔
40‧‧‧被動元件、去耦合電容元件
41‧‧‧金屬接點
42‧‧‧第三背面
50、50’‧‧‧堆疊式封裝結構
51‧‧‧下重佈線層
52‧‧‧邏輯晶片
53‧‧‧第一封膠體
54‧‧‧上重佈線層
541‧‧‧金屬接點
55‧‧‧記憶晶片
56‧‧‧第二封膠體
57‧‧‧金屬柱
60‧‧‧多晶片封裝結構
61‧‧‧邏輯晶片
62‧‧‧記憶晶片組
63‧‧‧矽中介板
631‧‧‧外接墊
64‧‧‧封裝用載板
641‧‧‧外接墊
圖1：係本發明堆疊式封裝結構的第一較佳實施例的剖面圖。
圖2A：係本發明堆疊式封裝結構的第二較佳實施例的剖面圖。
圖2B：係本發明堆疊式封裝結構的第三較佳實施例的剖面圖。
圖3：係既有一種堆疊式封裝結構的剖面圖。
圖4：係既有另一種堆疊式封裝結構的剖面圖。
圖5：係既有一種多晶片封裝結構的剖面圖。
本發明係針對系統級封裝結構提出改良，使其封裝結構的高度得以減縮，也可進一步改善高速訊號干擾的問題，以下謹以複數實施例配合圖式詳加說明本發明的技術內容。
首先請參閱圖1所示，係為本發明雙面扇出型系統級封裝結構10的第一較佳實施例，其包含有一第一重佈線層11、一晶片20、至少一晶片組30、一封膠層12以及一第二重佈線層13；其中該晶片20及各該晶片組30係共同設置在該第一及第二重佈線層11、13之間。
上述第一重佈線層11係於一第一介電本體111內形成有複數第一連接線112，並於一側形成與該些第一連接線112電性連接的複數外接墊113，於另一相對側形成與該些第一連接線112電性連接的複數內接點114；於本實施例，該些外接墊113為錫球，亦可為金屬凸塊，均不以此為限。
上述晶片20包含有一第一主動面21及一相對該第一主動面21之第一背面22；其中該第一主動面21係包含有複數第一接點211及複數第二接點212；其中該些第一接點211及第二接點212係分別電性連接於該第一重佈線層11的對應內接點114，且該晶片20形成有複數第一矽穿孔23，各該第一矽穿孔23的第一端231係與該第一主動面21的對應第二接點212電性連接，各該第一矽穿孔23的第二端232則外露於該第一背面22；於本實施例中，該晶片20為一邏輯晶片(如：中央處理器CPU、繪圖處理器GPU等)。
上述各該晶片組30係包含有一第二主動面31及一相對該第二主動面31之一第二背面32；其中各該晶片組30之該第二背面32係固定於該第一重佈線層11上；於本實施例，該第二背面32係以一黏著層14固定在該第一重佈線層11，且各該晶片組30為一記憶晶片組，其包含有一控制晶片301及至少一記憶晶 片302，該控制晶片301及該至少一記憶晶片302係堆疊設置，且各該記憶晶片302形成有第二矽穿孔33，以與相鄰的記憶晶片302及該控制晶片301電性連接，且該控制晶片301的背面係固定於該第一重佈線層11上，而相對位在最外的記憶晶片302的主動面即是該晶片組30的第二主動面31。
上述封膠層12係形成在該第一重佈線層11上並包覆該晶片20及各該晶片組30，惟該晶片20的各該第一矽穿孔23的第二端232及各該晶片組30的第二主動面31係外露於該封膠體12，即該晶片20的第一背面22與各該晶片組30的該第二主動面31齊平。
上述第二重佈線層13係共同形成於該封膠層12、該晶片20及各該晶片組30上，並與該晶片20之各該第一矽穿孔23的第二端232與各該晶片組30的第二主動面31電性連接。該第二重佈線層13係於一第二介電本體131內形成有複數第二連接線132，用以電性連接該晶片20之各該第一矽穿孔23的第二端232與各該晶片組30的第二主動面31；如此，各該晶片組30的第二主動面31係透過該第二連接線132、該第一矽穿孔23及第二接點212，以與該晶片20及第一重佈線層11電性連接。
由上述說明可知，本發明之雙面扇出型系統級封裝結構10係包含有雙層的第一及第二重佈線層11、13，不同功能的晶片及晶片組20、30係設置在該第一及第二重佈線層11、13之間，並分別與對應的第一或第二重佈線層11、13電性連接，以隔離該晶片及晶片組20、30傳送訊號相互干擾；又第二重佈線層13再透過該晶片20的第一矽穿孔23及該晶片20的第二接點212電性連接至該第一重佈線層11，且該晶片20的高度可與該晶片組30的高度實質相同。
再請參閱圖2A所示，本發明之雙面扇出型系統級封裝結構10a的第二較佳實施例，其大多結構與圖1所示之第一較佳實施例相同，惟進一步包含有一被動元件40，該被動元件40係包含有金屬接點41；於本實施例中，該被動元 件40可為一去耦合電容元件40，其主要用以提供一穩定且低雜訊之電源給予晶片20及晶片組30，故其金屬接點41係對應電性連接至該些第二連接線132，即該晶片20的該第一背面22、各該晶片組30的第二主動面31及該去耦合電容40的金屬接點41齊平，且去耦合電容元件40的第三背面42設置在該第一重佈線層11上；於本實施例，該第三背面42係以一黏著層14固定在該第一重佈線層11上；又該去耦合電容元件40係與該第二重佈線層13之第二連接線132的系統電源及接地電源電性連接。於本實施例中，該被動元件40可為一貼片式元件(Surface mount device)或內藏基板式元件(Embedded substrate device)的一例，並不以此為限。於本實施例中，該去耦合電容元件40僅為被動元件的一例，並不以此為限。
再如圖2B所示，本發明之雙面扇出型系統級封裝結構10b的第三較佳實施例，其結構與圖2A所示之第二較佳實施例相同，且該去耦合電容元件40主要用以提供一穩定且低雜訊之電源給予晶片20及晶片組30，惟該去耦合電容元件40的金屬接點41係對應電性連接至該些第一連接線112，其第三背面42設置在該第二重佈線層13內側面，即該晶片20的第一背面22、各該晶片組30的第二主動面31與該去耦合電容元件40的第三背面43齊平；又該去耦合電容元件40係與該第一重佈線層11之第一連接線112的系統電源及接地電源電性連接。
此外，前揭該晶片20的高度、各該晶片組30的高度與該被動元件40的高度係可實質相同，故該被動元件40與該晶片20及各該晶片組30共平面。
綜上所述，本發明的雙面扇出型多晶片封裝結構主要將不同功能的晶片的第一主動面及晶片組的第二主動面分別電性連接在不同位置的第一及第二重佈線層，再配合該晶片的矽穿孔，仍可將各該晶片組的第二主動面與該晶片及第一重佈線的對應內接點電性連接；如此，該晶片及晶片組即可不必堆疊設置或使用矽中介板或其他封裝載板，能有效減低封裝結構的高度；此外，由於該晶片及晶片組分別電性連接在不同位置的第一及第二重佈線層，而封膠體使得 第一重佈線層與第二重佈線層相互隔離，，可有效避免晶片及晶片組之高速訊號彼此相互干擾。
以上所述僅是本發明的實施例而已，並非對本發明做任何形式上的限制，雖然本發明已以實施例揭露如上，然而並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明技術方案的範圍內，當可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例，但凡是未脫離本發明技術方案的內容，依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾，均仍屬於本發明技術方案的範圍內。

Claims (9)

  1. 一種雙面扇出型多晶片封裝結構，包括：一第一重佈線層，係於一第一介電本體內形成有複數第一連接線，該第一介電本體的一側形成有複數內接點，另一相對側係形成有複數外接墊，並透過該些第一連接線與該些內接點電性連接；一邏輯晶片，係包含一第一主動面及一相對該第一主動面之一第一背面，該第一主動面係包含有複數接點；其中該些接點分別電性連接於該第一重佈線層的對應內接點，且該邏輯晶片形成有複數第一矽穿孔，各該第一矽穿孔的第一端係與對應的該接點電性連接，而各該第一矽穿孔的第二端係外露於該第一背面；至少一記憶晶片組，各該記憶晶片組係包含有：一控制晶片，係包含有一第二背面，該第二背面係固定在該第一重佈線層；以及複數記憶晶片，係堆疊設置於該控制晶片上，各該記憶晶片包含有複數第二矽穿孔，以與相鄰記憶晶片及該控制晶片電性連接；其中遠離該控制晶片的記憶晶片係包含有一第二主動面；一封膠層，係形成於該第一重佈線層上並包覆該邏輯晶片及各該記憶晶片組；其中該邏輯晶片的各該第一矽穿孔的第二端及各該記憶晶片組中之該記憶晶片的第二主動面外露於該封膠體；以及一第二重佈線層，係共同形成於該封膠層、該邏輯晶片的第一背面及各該記憶晶片組中之該記憶晶片的第二主動面上，以與該邏輯晶片之各該第一矽穿孔的第二端及各該記憶晶片組中之該記憶晶片的第二主動面電性連接。
  2. 如請求項1所述之雙面扇出型多晶片封裝結構，各該記憶晶片組中之該控制晶片的第二背面係以一黏著層固定於該第一重佈線層上。
  3. 如請求項1所述之雙面扇出型多晶片封裝結構，係進一步包含有：一被動元件，其第三背面係固定於該第一重佈線層上，且其複數金屬接點係與該第二重佈線層電性連接，或該第三背面係固定於該第二重佈線層內側面，且其複數金屬接點係與該第一重佈線層電性連接。
  4. 如請求項1或2所述之雙面扇出型多晶片封裝結構，該邏輯晶片的該第一背面與各該記憶晶片組中之該記憶晶片的該第二主動面齊平。
  5. 如請求項1所述之雙面扇出型多晶片封裝結構，該邏輯晶片的高度與各該記憶晶片組的高度實質相同。
  6. 如請求項3所述之雙面扇出型多晶片封裝結構，該被動元件係與該邏輯晶片與各該記憶晶片組共平面。
  7. 如請求項3所述之雙面扇出型多晶片封裝結構，該邏輯晶片的高度、各該記憶晶片組的高度與該被動元件的高度實質相同。
  8. 如請求項1所述之雙面扇出型多晶片封裝結構，該第二重佈層係包含有一第二介電本體，該第二介電本體內形成有複數第二連接線，以電性連接該邏輯晶片之各該第一矽穿孔的第二端與各該記憶晶片組中之該記憶晶片的第二主動面。
  9. 如請求項3、6或7所述之雙面扇出型多晶片封裝結構，該被動元件為一去耦合電容元件。
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