CN111063663A - 双面扇出型系统级封装结构 - Google Patents

双面扇出型系统级封装结构 Download PDF

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CN111063663A
CN111063663A CN201811228748.1A CN201811228748A CN111063663A CN 111063663 A CN111063663 A CN 111063663A CN 201811228748 A CN201811228748 A CN 201811228748A CN 111063663 A CN111063663 A CN 111063663A
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chip
package structure
electrically connected
active surface
redistribution layer
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CN111063663B (zh
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潘吉良
李念庭
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Powertech Technology Inc
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Abstract

本发明关于一双面扇出型系统级封装结构，包含一第一重布线层、一第二重布线层与设置在该第一及第二重布线层之间的一芯片及一芯片组；其中该芯片电性连接该第一重布线层并形成有硅穿孔，该第二重布线层电性连接至该芯片的硅穿孔与该芯片组，该芯片组可通过该第二重布线层及硅穿孔与该芯片及第一重布线电性连接；如此，该芯片及芯片组之间的电性连接即可不必通过堆叠设置或使用硅中介板或其他封装载板，进而能有效减低封装结构的高度；此外，包覆该芯片及芯片组的封胶体使得第一重布线层与第二重布线层相互隔离，可有效避免芯片及芯片组的高速信号彼此相互干扰。

Description

双面扇出型系统级封装结构
技术领域
本发明关于一种系统封装结构，尤指一种双面扇出型系统级封装结构。
背景技术
随着电子装置需要储存及处理的数据量愈来愈大，其要求相关电子元件规格提升、数量也随之增加，且必须设置在有限的空间内；为符合此要求，一种系统级封装(Systemin Package，SiP)结构被提出，将相关功能的芯片整合于单一封装结构，该系统级封装结构包含有以下数种形式。
请参阅图3所示，为一种堆叠式封装结构50(Package on Package；PoP)，于一下重布线层51上电性连接有一逻辑芯片52，接着以第一封胶体53包覆该逻辑芯片52；之后，于该第一封胶体53及该逻辑芯片52上形成一上重布线层54，将至少一存储芯片55打线电性连接在该上重布线层54的金属接点541，再以第二封胶体56包覆该存储芯片55；其中该上、下重布线层54、51之间通过金属柱57相互电性连接；若因应更大储存空间需求，如图4所示，则进一步于该存储芯片55上再叠设其它存储芯片55，惟该堆叠式封装结构50’的高度会增加。
请参阅图5所示，为一种多芯片封装结构60(Multi-Chip Package；MCP)，将一逻辑芯片61及至少一存储芯片组62电性连接在一硅中介板63上，由于该硅中介板63的相邻外接垫631间距过小，通常会进一步电性连接至一封装用载板64上，该封装用载板64的相邻外接垫641的间距即符合电子元件的相邻外接垫的间距；如此，即可将该逻辑芯片61及该至少一存储芯片组62同时封装成单一电子元件。
上述无论是堆叠式封装结构或多芯片封装结构的高度都较高，对于轻薄电子装置来说，电子元件设置空间的高度仍有限制，故而有必要进一步提出改良。
发明内容
有鉴于前述多芯片封装结构的高度过高，本发明的主要发明目的在于提供一种薄化的双面扇出型多芯片封装结构。
欲达上述目的所使用的主要技术手段为使该双面扇出型多芯片封装结构包含有：
一第一重布线层，于一第一介电本体内形成有多个第一连接线，该第一介电本体的一侧形成有多个内接点，另一相对侧形成有多个外接垫，并通过该些第一连接线与该些内接点电性连接；
一芯片，包含一第一有源面及一相对该第一有源面的一第一背面，该第一有源面包含有多个接点；其中该些接点分别电性连接于该第一重布线层的对应内接点，且该芯片形成有多个第一硅穿孔，各该第一硅穿孔的第一端与对应的该接点电性连接，而各该第一硅穿孔的第二端外露于该第一背面；
至少一芯片组，各该芯片组包含有一第二有源面及一相对该第二有源面的一第二背面，该第二背面固定于该第一重布线层上；
一封胶层，形成于该第一重布线层上并包覆该芯片及各该芯片组；其中该芯片的各该第一硅穿孔的第二端及各该芯片组的第二有源面外露于该封胶体；以及
一第二重布线层，共同形成于该封胶层、该芯片的第一背面及各该芯片组的第二有源面上，以与该芯片的各该第一硅穿孔的第二端及各该芯片组的第二有源面电性连接。
由上述说明可知，本发明的双面扇出型多芯片封装结构主要将不同功能的芯片的第一有源面及芯片组的第二有源面分别电性连接在不同位置的第一及第二重布线层，再配合该芯片的硅穿孔，仍可将各该芯片组的第二有源面与该芯片及第一重布线的对应内接点电性连接；如此，该芯片及芯片组即可不必堆叠设置或使用硅中介板或其他封装载板，能有效减低封装结构的高度；此外，由于该芯片的第一有源面及芯片组的第二有源面分别电性连接在不同位置的第一及第二重布线层，而封胶体使得第一重布线层与第二重布线层相互隔离，可有效避免芯片及芯片组的高速信号彼此相互干扰。
以下结合附图和具体实施例对本发明进行详细描述，但不作为对本发明的限定。
附图说明
图1：本发明堆叠式封装结构的第一较佳实施例的剖面图。
图2A：本发明堆叠式封装结构的第二较佳实施例的剖面图。
图2B：本发明堆叠式封装结构的第三较佳实施例的剖面图。
图3：现有一种堆叠式封装结构的剖面图。
图4：现有另一种堆叠式封装结构的剖面图。
图5：现有一种多芯片封装结构的剖面图。
其中，附图标记：
10、10a、10b 系统级封装结构 11 第一重布线层
111 第一介电本体 112 第一连接线
113 外接垫 114 内接点
12 封胶体 13 第二重布线层
131 第二介电本体 132 第二连接线
14 黏着层 20 芯片
21 第一有源面 211 第一接点
212 第二接点 22 第一背面
23 第一硅穿孔 231 第一端
232 第二端 30 芯片组
301 控制芯片 302 存储芯片
31 第二有源面 32 第二背面
33 第二硅穿孔 40 无源元件、去耦合电容元件
41 金属接点 42 第三背面
50、50’ 堆叠式封装结构 51 下重布线层
52 逻辑芯片 53 第一封胶体
54 上重布线层 541 金属接点
55 存储芯片 56 第二封胶体
57 金属柱 60 多芯片封装结构
61 逻辑芯片 62 存储芯片组
63 硅中介板 631 外接垫
64 封装用载板
641 外接垫
具体实施方式
下面结合附图对本发明的结构原理和工作原理作具体的描述：
本发明针对系统级封装结构提出改良，使其封装结构的高度得以减缩，也可进一步改善高速信号干扰的问题，以下谨以多个实施例配合图式详加说明本发明的技术内容。
首先请参阅图1所示，为本发明双面扇出型系统级封装结构10的第一较佳实施例，其包含有一第一重布线层11、一芯片20、至少一芯片组30、一封胶层12以及一第二重布线层13；其中该芯片20及各该芯片组30共同设置在该第一及第二重布线层11、13之间。
上述第一重布线层11于一第一介电本体111内形成有多个第一连接线112，并于一侧形成与该些第一连接线112电性连接的多个外接垫113，于另一相对侧形成与该些第一连接线112电性连接的多个内接点114；于本实施例，该些外接垫113为锡球，亦可为金属凸块，均不以此为限。
上述芯片20包含有一第一有源面21及一相对该第一有源面21的第一背面22；其中该第一有源面21包含有多个第一接点211及多个第二接点212；其中该些第一接点211及第二接点212分别电性连接于该第一重布线层11的对应内接点114，且该芯片20形成有多个第一硅穿孔23，各该第一硅穿孔23的第一端231与该第一有源面21的对应第二接点212电性连接，各该第一硅穿孔23的第二端232则外露于该第一背面22；于本实施例中，该芯片20为一逻辑芯片(如：中央处理器CPU、绘图处理器GPU等)。
上述各该芯片组30包含有一第二有源面31及一相对该第二有源面31的一第二背面32；其中各该芯片组30的该第二背面32固定于该第一重布线层11上；于本实施例，该第二背面32以一粘着层14固定在该第一重布线层11，且各该芯片组30为一存储芯片组，其包含有一控制芯片301及至少一存储芯片302，该控制芯片301及该至少一存储芯片302堆叠设置，且各该存储芯片302形成有第二硅穿孔33，以与相邻的存储芯片302及该控制芯片301电性连接，且该控制芯片301的背面固定于该第一重布线层11上，而相对位在最外的存储芯片302的有源面即是该芯片组30的第二有源面31。
上述封胶层12形成在该第一重布线层11上并包覆该芯片20及各该芯片组30，惟该芯片20的各该第一硅穿孔23的第二端232及各该芯片组30的第二有源面31外露于该封胶体12，即该芯片20的第一背面22与各该芯片组30的该第二有源面31齐平。
上述第二重布线层13共同形成于该封胶层12、该芯片20及各该芯片组30上，并与该芯片20的各该第一硅穿孔23的第二端232与各该芯片组30的第二有源面31电性连接。该第二重布线层13于一第二介电本体131内形成有多个第二连接线132，用以电性连接该芯片20的各该第一硅穿孔23的第二端232与各该芯片组30的第二有源面31；如此，各该芯片组30的第二有源面31通过该第二连接线132、该第一硅穿孔23及第二接点212，以与该芯片20及第一重布线层11电性连接。
由上述说明可知，本发明的双面扇出型系统级封装结构10包含有双层的第一及第二重布线层11、13，不同功能的芯片及芯片组20、30设置在该第一及第二重布线层11、13之间，并分别与对应的第一或第二重布线层11、13电性连接，以隔离该芯片及芯片组20、30传送信号相互干扰；又第二重布线层13再通过该芯片20的第一硅穿孔23及该芯片20的第二接点212电性连接至该第一重布线层11，且该芯片20的高度可与该芯片组30的高度实质相同。
再请参阅图2A所示，本发明的双面扇出型系统级封装结构10a的第二较佳实施例，其大多结构与图1所示的第一较佳实施例相同，惟进一步包含有一无源元件40，该无源元件40包含有金属接点41；于本实施例中，该无源元件40可为一去耦合电容元件40，其主要用以提供一稳定且低噪声的电源给予芯片20及芯片组30，故其金属接点41对应电性连接至该些第二连接线132，即该芯片20的该第一背面22、各该芯片组30的第二有源面31及该去耦合电容40的金属接点41齐平，且去耦合电容元件40的第三背面42设置在该第一重布线层11上；于本实施例，该第三背面42以一粘着层14固定在该第一重布线层11上；又该去耦合电容元件40与该第二重布线层13的第二连接线132的系统电源及接地电源电性连接。于本实施例中，该无源元件40可为一贴片式元件(Surface mount device)或内嵌基板式元件(Embedded substrate device)的一例，并不以此为限。于本实施例中，该去耦合电容元件40仅为无源元件的一例，并不以此为限。
再如图2B所示，本发明的双面扇出型系统级封装结构10b的第三较佳实施例，其结构与图2A所示的第二较佳实施例相同，且该去耦合电容元件40主要用以提供一稳定且低噪声的电源给予芯片20及芯片组30，惟该去耦合电容元件40的金属接点41对应电性连接至该些第一连接线112，其第三背面42设置在该第二重布线层13内侧面，即该芯片20的第一背面22、各该芯片组30的第二有源面31与该去耦合电容元件40的第三背面43齐平；又该去耦合电容元件40与该第一重布线层11的第一连接线112的系统电源及接地电源电性连接。
此外，前述该芯片20的高度、各该芯片组30的高度与该无源元件40的高度可实质相同，故该无源元件40与该芯片20及各该芯片组30共平面。
综上所述，本发明的双面扇出型多芯片封装结构主要将不同功能的芯片的第一有源面及芯片组的第二有源面分别电性连接在不同位置的第一及第二重布线层，再配合该芯片的硅穿孔，仍可将各该芯片组的第二有源面与该芯片及第一重布线的对应内接点电性连接；如此，该芯片及芯片组即可不必堆叠设置或使用硅中介板或其他封装载板，能有效减低封装结构的高度；此外，由于该芯片及芯片组分别电性连接在不同位置的第一及第二重布线层，而封胶体使得第一重布线层与第二重布线层相互隔离，可有效避免芯片及芯片组的高速信号彼此相互干扰。
当然，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形，但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。

Claims (10)

1.一种双面扇出型多芯片封装结构，其特征在于，包括：
一第一重布线层，于一第一介电本体内形成有多个第一连接线，该第一介电本体的一侧形成有多个内接点，另一相对侧形成有多个外接垫，并通过该些第一连接线与该些内接点电性连接；
一芯片，包含一第一有源面及一相对该第一有源面的一第一背面，该第一有源面包含有多个接点；其中该些接点分别电性连接于该第一重布线层的对应内接点，且该芯片形成有多个第一硅穿孔，各该第一硅穿孔的第一端与对应的该接点电性连接，而各该第一硅穿孔的第二端外露于该第一背面；
至少一芯片组，各该芯片组包含有一第二有源面及一相对该第二有源面的一第二背面，该第二背面固定于该第一重布线层上；
一封胶层，形成于该第一重布线层上并包覆该芯片及各该芯片组；其中该芯片的各该第一硅穿孔的第二端及各该芯片组的第二有源面外露于该封胶体；以及
一第二重布线层，共同形成于该封胶层、该芯片的第一背面及各该芯片组的第二有源面上，以与该芯片的各该第一硅穿孔的第二端及各该芯片组的第二有源面电性连接。
2.如权利要求1所述的双面扇出型多芯片封装结构，其特征在于，各该芯片组的第二背面以一黏着层固定于该第一重布线层上。
3.如权利要求1所述的双面扇出型多芯片封装结构，其特征在于，其中：
该芯片为一逻辑芯片；以及
各该芯片组为一存储芯片组，该存储芯片组包含有：
一控制芯片，其背面固定在该第一重布线层；以及
多个存储芯片，堆叠设置于该控制芯片上，各该存储芯片包含有多个第二硅穿孔，以与相邻存储芯片及该控制芯片电性连接。
4.如权利要求3所述的双面扇出型多芯片封装结构，其特征在于，进一步包含有：
一无源元件，其第三背面固定于该第一重布线层上，且其多个金属接点与该第二重布线层电性连接，或该第三背面固定于该第二重布线层内侧面，且其多个金属接点与该第一重布线层电性连接。
5.如权利要求1至3中任一项所述的双面扇出型多芯片封装结构，其特征在于，该芯片的该第一背面与各该芯片组的该第二有源面齐平。
6.如权利要求1所述的双面扇出型多芯片封装结构，其特征在于，该芯片的高度与各该芯片组的高度实质相同。
7.如权利要求4所述的双面扇出型多芯片封装结构，其特征在于，该无源元件与该芯片与各该芯片组共平面。
8.如权利要求4所述的双面扇出型多芯片封装结构，其特征在于，该芯片的高度、各该芯片组的高度与该无源元件的高度实质相同。
9.如权利要求1所述的双面扇出型多芯片封装结构，其特征在于，该第二重布层包含有一第二介电本体，该第二介电本体内形成有多个第二连接线，以电性连接该芯片的各该第一硅穿孔的第二端与各该芯片组的第二有源面。
10.如权利要求4、7或8所述的双面扇出型多芯片封装结构，其特征在于，该无源元件为一去耦合电容元件。
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