CN107799499A - 半导体封装结构及其制造方法 - Google Patents

半导体封装结构及其制造方法 Download PDF

Info

Publication number
CN107799499A
CN107799499A CN201710664209.1A CN201710664209A CN107799499A CN 107799499 A CN107799499 A CN 107799499A CN 201710664209 A CN201710664209 A CN 201710664209A CN 107799499 A CN107799499 A CN 107799499A
Authority
CN
China
Prior art keywords
chip
redistribution layer
encapsulant
layer
semiconductor package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710664209.1A
Other languages
English (en)
Other versions
CN107799499B (zh
Inventor
郑心圃
许峰诚
陈硕懋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN107799499A publication Critical patent/CN107799499A/zh
Application granted granted Critical
Publication of CN107799499B publication Critical patent/CN107799499B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02372Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199Material of the matrix
    • H01L2224/13294Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/132 - H01L2224/13291
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298Fillers
    • H01L2224/13299Base material
    • H01L2224/133Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171Disposition
    • H01L2224/17104Disposition relative to the bonding areas, e.g. bond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171Disposition
    • H01L2224/1718Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331Disposition
    • H01L2224/3318Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73259Bump and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/9202Forming additional connectors after the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92222Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92224Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06524Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06527Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544Design considerations for via connections, e.g. geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06548Conductive via connections through the substrate, container, or encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06572Auxiliary carrier between devices, the carrier having an electrical connection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06582Housing for the assembly, e.g. chip scale package [CSP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本揭露实施例揭露一种半导体封装结构及其制造方法。其中该半导体封装结构包含重布层RDL、第一芯片、至少一个第二芯片、囊封物及第三芯片。所述重布层具有彼此对置的第一表面及第二表面。所述第一芯片位于所述重布层的所述第一表面上方且电连接到所述重布层。所述第二芯片位于所述重布层的所述第一表面上方。所述第二芯片包含多个通孔结构。所述囊封物位于所述重布层的所述第一表面上方,其中所述囊封物包围所述第一芯片及所述第二芯片。所述第三芯片位于所述囊封物上方且透过所述第二芯片的所述通孔结构及所述重布层电连接到所述第一芯片。

Description

半导体封装结构及其制造方法
技术领域
本揭露实施例涉及半导体封装结构及其制造方法。
背景技术
为试图进一步增大电路密度且减少成本,已开发三维(3D)半导体封装结构。随着半导体技术的演进,半导体装置变得越来越小,同时需要将更多功能集成到半导体装置中。相应地,半导体装置需要使越来越多输入/输出(I/O)端子封装到较小面积中,且I/O端子的密度随时间快速上升。因此,半导体装置的封装变得更困难,其不利地影响封装的成出率。
发明内容
根据本揭露的一实施例,一种半导体封装结构包括:重布层,其具有彼此对置的第一表面及第二表面;第一芯片,其位于所述重布层的所述第一表面上方且电连接到所述重布层;第二芯片,其位于所述重布层的所述第一表面上方,其中所述第二芯片包含多个通孔结构;囊封物,其位于所述重布层的所述第一表面上方,其中所述囊封物包围所述第一芯片及所述第二芯片;及第三芯片,其位于所述囊封物上方且透过所述第二芯片的所述通孔结构及所述重布层电连接到所述第一芯片。
根据本揭露的一实施例,一种半导体封装结构包括:第一重布层,其具有彼此对置的第一表面及第二表面;第一芯片,其位于所述第一重布层的所述第一表面上方;第二芯片,其位于所述第一重布层的所述第一表面上方,其中所述第二芯片包含多个通孔结构,且所述通孔结构的第一端子耦合到所述第一重布层;第一囊封物,其位于所述第一重布层的所述第一表面上方,其中所述第一囊封物包围所述第一芯片及所述第二芯片;第二重布层,其位于所述第一囊封物上方且电连接到所述通孔结构的第二端子,其中所述第二重布层具有彼此对置的第三表面及第四表面,且所述第三表面面向所述第一表面;第三芯片,其位于所述第二重布层的所述第四表面上方且电连接到所述第二重布层;及第二囊封物,其位于所述第二重布层上方。
根据本揭露的一实施例,一种用于制造半导体封装结构的方法包括:形成第一重布层;将第一芯片安置在所述第一重布层上方;将第二芯片安置在所述第一重布层上方,其中所述第二芯片包含多个通孔结构;使囊封物形成在所述第一重布层上方;及将第三芯片安置在所述囊封物上方,其中所述第三芯片及所述第一重布层透过所述第二芯片的所述通孔结构电连接。
附图说明
自结合附图来解读的以下详细描述最佳地理解本揭露的方面。应注意,根据行业标准做法,各种结构未按比例绘制。事实上,为使讨论清楚,可任意增大或减小各种结构的尺寸。
图1是绘示根据本揭露的各种方面的用于制造半导体封装结构的方法的流程图。
图2A、2B、2C、2D、2E、2F、2G、2H、2I、2J及2K是根据本揭露的一或多个实施例的制造半导体封装结构的各种操作的一者中的横截面图。
图3是根据本揭露的一或多个实施例的半导体封装结构的横截面图。
图4A、4B、4C、4D、4E、4F、4G、4H、4I、4J及4K是根据本揭露的一或多个实施例的制造半导体封装结构的各种操作的一者中的横截面图。
图5是根据本揭露的一或多个实施例的半导体封装结构的横截面图。
图6是根据本揭露的一或多个实施例的半导体封装结构的横截面图。
图7是根据本揭露的一或多个实施例的半导体封装结构的横截面图。
图8A、8B、8C、8D、8E、8F、8G、8H及8I是根据本揭露的一或多个实施例的制造半导体封装结构的各种操作的一者中的横截面图。
图9是根据本揭露的一或多个实施例的半导体封装结构的横截面图。
图10是根据本揭露的一或多个实施例的半导体封装结构的横截面图。
具体实施方式
本申请案主张2016年9月2日申请的美国临时申请案第62/382,912号的优先权,所述案的全文以引用的方式并入。
以下揭露提供用于实施所提供的目标的不同特征的诸多不同实施例或实例。下文将描述组件及布置的特定实例以简化本揭露。当然,此类仅为实例且不意在限制。例如,在以下描述中,“使第一构件形成在第二构件上方或第二构件上”可包含其中形成直接接触的所述第一构件及所述第二构件的实施例,且还可包含其中可形成介于所述第一构件与所述第二构件之间的额外构件使得所述第一构件及所述第二构件可不直接接触的实施例。另外,本揭露可在各种实例中重复组件符号及/或字母。此重复是为了简化及清楚且其本身不指示所讨论的各种实施例及/或配置之间的关系。
此外,为便于描述,诸如“下面”、“下方”、“下”、“上方”、“上面”、“上”及其类似者的空间相对术语可在本文中用于描述一组件或构件与另外(若干)组件或(若干)构件的关系,如图中所绘示。空间相对术语除涵盖图中所描绘的定向之外,还旨在涵盖装置在使用或操作中的不同定向。设备可依其它方式定向(旋转90度或依其它定向)且还可相应地解译本文所使用的空间相对描述词。
如本文所使用,诸如“第一”、“第二”及“第三”的术语描述各种组件、组件、区域、层及/或区段,此类组件、组件、区域、层及/或区段应不受限于此类术语。此类术语可仅用于区分一组件、组件、区域、层或区段与另一组件、组件、区域、层或区段。除非内文明确指示,否则本文所使用的诸如“第一”、“第二”及“第三”的术语不隐含序列或顺序。
如本文所使用,术语“近似”、“实质上”、“实质”及“约”用于描述及解释小变动。当所述术语与事件或状况一起使用时,所述术语可涉及其中所述事件或状况精确发生的例项以及其中所述事件或状况非常近似发生的例项。例如,当所述术语与数值一起使用时,所述术语可涉及小于或等于所述数值的±10%的变动范围,诸如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%,或小于或等于±0.05%。例如,如果两个数值之间的差值小于或等于所述值的平均值的±10%(诸如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%,或小于或等于±0.05%),那么所述值可被视为“实质上”相同或相等。例如,“实质上”平行可涉及小于或等于±10°的相对于0°的角变动范围,诸如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°,或小于或等于±0.05°。例如,“实质上”垂直可涉及小于或等于±10°的相对于90°的角变动范围,诸如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°,或小于或等于±0.05°。
如本文所使用,术语“载体衬底”或“暂时衬底”指代经配置为中间衬底以用于上覆层(诸如重布层、芯片、囊封物及其它结构)的制造设施或用于切割的载体。载体衬底或暂时衬底提供暂时支撑及固定功能,且会从上覆结构去除。
如本文所使用,术语“重布层(RDL)”指代由至少一个导电图案及至少一个绝缘层形成且经配置以与两个或多于两个装置电通信的一层堆叠。
如本文所使用,术语“导电凸块”指代经配置以透过其两端使两个导电结构电互连的导体。在一或多个实施例中,导电凸块由可通过低温操作而形成的低熔点材料形成。导电凸块形成在形成包围互连凸块的侧壁的囊封物之前。在一或多个实施例中,导电凸块是焊料凸块、焊料膏或其类似者。
如本文所使用,术语“导电柱”指代通过可实施精细节距的沉积、光刻及蚀刻操作而形成的导体。
如本文所使用,术语“中介层”是互连结构,其经配置以将安置在所述互连结构的两个对置表面上的两个或多于两个电子装置(诸如芯片、重布层或封装)电连接。在一或多个实施例中,中介层是预成形互连结构,其可安置在待互连到另一电子装置的电子装置的一者上。在一或多个实施例中,中介层包含具有精细节距的若干通孔结构,诸如穿硅通孔(TSV)。
如本文所使用,术语“穿绝缘体通孔(TIV)”是贯穿绝缘体且经配置以透过其两端将两个导电结构电连接的导体。
在本揭露的一或多个实施例中,半导体封装结构包含位于囊封物中且介于两个电子装置之间的芯片,且电子装置的各者独立地包含重布层、半导体裸片或封装。在一或多个实施例中,芯片的一部分包含经配置以提供两个电子装置之间的高密度互连的通孔结构(诸如TSV),而芯片的另一部分无需通孔结构来电连接到电子装置的一者。具有通孔结构的芯片提供用于两个电子装置之间的互连的短信号路径。在一些实施例中,具有通孔结构的芯片是不具有集成在其内的有源装置的中介层。在一些实施例中,具有通孔结构的芯片是包含集成在其内的TSV的有源装置芯片。在一或多个实施例中,穿绝缘体通孔(TIV)可布置在囊封物中以提供两个电子装置之间的额外信号路径来提高选路灵活性。在一或多个实施例中,半导体封装结构是扇出晶片级封装(FOWLP)。
图1是绘示根据本揭露的各种方面的用于制造半导体封装结构的方法的流程图。方法100开始于其中形成第一重布层的操作110。方法100继续到其中将第一芯片安置在所述第一重布层上方的操作120。方法100前进到其中将第二芯片安置在所述第一重布层上方的操作130,其中所述第二芯片包含多个通孔结构。方法100前进到其中使囊封物形成在所述第一重布层上方的操作140。方法100前进到其中将第三芯片安置在所述囊封物上方的操作150,其中所述第三芯片及所述第一重布层透过所述第二芯片的所述通孔结构电连接。
方法100仅为实例,且不旨在限制本揭露超出权利要求书中明确叙述的内容的范围。可在方法100之前、在方法100期间及在方法100之后提供额外操作,且可针对方法的额外实施例替换、消除或移动所描述的一些操作。
图2A、2B、2C、2D、2E、2F、2G、2H、2I、2J及2K是根据本揭露的一或多个实施例的制造半导体封装结构的各种操作的一者中的横截面图。如图2A中所描绘,第一重布层20形成在载体衬底10上方。在一或多个实施例中,载体衬底10经配置为用于形成重布层(诸如第一重布层20)的暂时衬底,且随后会被去除。在一或多个实施例中,载体衬底10是诸如玻璃衬底的绝缘衬底。载体衬底10可包含半导体衬底(诸如硅衬底)、导电衬底(诸如金属衬底)或其它适合衬底。
第一重布层20具有彼此对置的第一表面201及第二表面202。在一些实施例中,第一重布层20的第二表面202面向载体衬底10。第一重布层20由至少一个导电层22及至少一个绝缘层24形成,且经配置以与两个或多于两个芯片电通信。在一或多个实施例中,第一重布层20包含彼此堆叠的若干导电层22及若干绝缘层24。在一些实施例中,(若干)导电层22的材料可包含(但不限于)金属,诸如铜、钛、其类似者或其组合。(若干)绝缘层24的材料可包含(但不限于)无机及/或有机绝缘材料。
在一或多个实施例中,导电层22包含不同图案且彼此电连接。在一或多个实施例中,最上导电层22的一部分从第一重布层20的第一表面201暴露。在一或多个实施例中,若干接合垫26(诸如凸块下金属(UBM))形成在第一重布层20的最上导电层22的暴露部分上方且电连接到第一重布层20的最上导电层22的暴露部分。
如图2B中所描绘,一或多个第一芯片30安置在第一重布层20的第一表面201上方。在一或多个实施例中,第一芯片30电连接到第一重布层20。在一或多个实施例中,第一芯片30包含有源装置芯片及/或无源装置芯片。举例来说,有源装置芯片可包含芯片上系统(SOC)及/或其它芯片。无源装置芯片可包含形成在其内的电阻器、电容器、电感器或其组合。在一些实施例中,无源装置芯片可呈(但不限于)集成电路的形式。第一芯片30可透过表面粘着技术(SMT)或其它适合接合技术安装在第一重布层20上。在一些实施例中,第一芯片30包含若干电端子30P,且第一芯片30通过透过导电材料32(诸如导电膏、导电凸块或其它适合导电材料)将电端子30P接合到接合垫26的一部分而电连接到第一重布层20。
一或多个第二芯片36安置在第一重布层20上方且电连接到第一重布层20。在一或多个实施例中,第二芯片36包含诸如通孔结构36C的若干互连件。举例来说,通孔结构36C是穿硅通孔(TSV)。第二芯片36经配置以使安置在两个对置侧上的第一重布层20及另一装置(诸如第三芯片或第二重布层)互连,且可实施相邻通孔结构36C之间的精细节距。在一些实施例中,第二芯片36是形成为集成电路形式且无有源装置集成在其内的中介层。在一些实施例中,第二芯片36是包含集成在其内的TSV的有源装置芯片,诸如SOC。在一或多个实施例中,第二芯片36可更包含诸如金属-绝缘体-金属(MIM)电容器的嵌入式无源装置。第二芯片36可透过SMT或其它适合接合技术安装在第一重布层20上。在一些实施例中,第二芯片36包含若干接触垫36P,且第二芯片36通过透过导电材料38(诸如导电膏、导电凸块或其它适合导电材料)将接触垫36P接合到接合垫26的另一部分而电连接到第一重布层20。在一或多个实施例中,第二芯片36及第一芯片30具有实质上相同高度且位于实质上相同层级处。在一或多个实施例中,通孔结构36C包含两个端子,其中通孔结构36C的第一端子C1透过(例如)接触垫36P耦合到第一重布层20,且通孔结构36C的第二端子C2经配置以耦合到(若干)第三芯片或待形成的第二重布层。在一或多个实施例中,通孔结构36C的第二端子C2嵌入第二芯片36中,且将在后续操作中被暴露。
如图2C中所描绘,囊封物(诸如第一囊封物40)形成在第一重布层20的第一表面201上方。在一或多个实施例中,第一囊封物40的材料是模塑料。在一些实施例中,底胶填充层42可形成在第一芯片30与第一重布层20之间及形成在第二芯片36与第一重布层20之间。在一些实施例中,第一囊封物40是成型底胶填充(MUF)层且因此可无需额外底胶填充层。在一或多个实施例中,第一囊封物40覆盖第一芯片30及第二芯片36的上表面及侧壁。
如图2D中所描绘,通过(例如)研磨而去除第一囊封物40的一部分以暴露第二芯片36的第二端子C2。在一或多个实施例中,第一囊封物40通过研磨而薄化。
如图2E中所描绘,绝缘层44形成在第一囊封物40上方。在一或多个实施例中,绝缘层44的材料可包含(但不限于)诸如PBO的有机绝缘材料。绝缘层44包含暴露第二芯片36的第二端子C2的若干开口。若干接合垫46形成在绝缘层44上方且透过绝缘层44的开口电连接到第二芯片36的第二端子C2。在一或多个实施例中,接合垫46可包含(但不限于)凸块下金属(UBM)。
如图2F中所描绘,一或多个第三芯片50安置在第一囊封物40上方且电连接到第二芯片36。在一或多个实施例中,第三芯片50包含封装或存储器芯片。举例来说,第三芯片50包含彼此堆叠且电连接的若干DRAM装置52。在一或多个实施例中,DRAM装置52包含通孔结构56且透过诸如微导电凸块的互连件54而彼此电连接。第三芯片50可透过SMT或其它适合接合技术安装在第二芯片36上。在一些实施例中,第三芯片50透过导电材料48(诸如导电膏、导电凸块或其它适合导电材料)电连接到第二芯片36的接合垫46。
如图2G中所描绘,第二囊封物58形成在第一囊封物40上方。在一或多个实施例中,第二囊封物58的材料是模塑料。在一些实施例中,底胶填充层59可形成在第三芯片50与第一囊封物40之间。在一些实施例中,第二囊封物58是成型底胶填充(MUF)层且因此无需额外底胶填充层。在一或多个实施例中,第二囊封物58覆盖第三芯片50的上表面及侧壁。在一些实施例中,第三芯片50可包含光电芯片(诸如CMOS图像传感器芯片)、MEMS芯片、存储器芯片、高功率芯片,且第二囊封物58可(例如)通过研磨而薄化以暴露第三芯片50的上表面。
如图2H中所描绘,第二囊封物58附着到暂时衬底60。在一或多个实施例中,暂时衬底60是柔性膜,诸如固定在框架62上的胶带。在一些实施例中,暂时衬底60可包含其它类型的衬底,诸如刚性衬底。接着,载体衬底10从第一重布层20的第二表面202拆离。
如图2I中所描绘,第一重布层20的一部分从第二表面202去除以暴露经配置为接合垫的最下导电层22。在一或多个实施例中,第一重布层20通过诸如干式蚀刻的蚀刻而去除。
如图2J中所描绘,若干导体64形成在第一重布层20的第二表面202上方且电连接到第一重布层20。在一或多个实施例中,导体64包含(但不限于)导电凸块。在一或多个实施例中,一或多个第四芯片66安置在第一重布层20的第二表面202上方且电连接到第一重布层20。在一或多个实施例中,第四芯片66包含无源装置芯片。举例来说,无源装置芯片可包含形成在其内的电阻器、电容器、电感器或其组合。在一些实施例中,无源装置芯片可呈(但不限于)集成电路的形式。在一或多个实施例中,执行单粒化操作以形成若干半导体封装结构1。接着,半导体封装结构1从暂时衬底60去除,如图2K中所展示。
在半导体封装结构1中,第一芯片30透过面向第一重布层20的电端子30P电连接到第一重布层20。第三芯片50透过具有通孔结构36C(其具有精细节距)的第二芯片36电连接到第一重布层20。第二芯片36提供用于第一芯片30与第三芯片50之间的互连的短信号路径。第二芯片36避免在第一芯片30中形成通孔结构,其有助于改进第一芯片30的成出率。第二芯片36经配置以提供可与具有高I/O密度的芯片(诸如存储器芯片)集成的数目增加I/O计数。
本揭露的半导体封装结构不受限于上文所提及的实施例,而是可具有其它不同实施例。为简化描述且为便于本揭露的实施例的各者之间进行比较,以下实施例的各者中的相同组件使用相同组件符号来标记。为易于比较实施例之间的差异,以下描述将详述不同实施例之间的相异性且将不赘述相同构件。
图3是根据本揭露的一或多个实施例的半导体封装结构的横截面图。如图3中所描绘,半导体封装结构2包含安置在第一重布层20上方且电连接到第三芯片50及第一重布层20的两个或多于两个第二芯片36。
图4A、4B、4C、4D、4E、4F、4G、4H、4I、4J及4K是根据本揭露的一或多个实施例的制造半导体封装结构的各种操作的一者中的横截面图。如图4A中所描绘,第一重布层20形成在载体衬底10上方。第一重布层20具有彼此对置的第一表面201及第二表面202。在一些实施例中,第一重布层20的第二表面202面向载体衬底10。第一重布层20由至少一个导电层22及至少一个绝缘层24形成,且经配置以与两个或多于两个芯片电通信。在一或多个实施例中,最上导电层22的一部分从第一重布层20的第一表面201暴露。在一或多个实施例中,若干接合垫26(诸如凸块下金属(UBM))形成在第一重布层20的最上导电层22的暴露部分上方且电连接到第一重布层20的最上导电层22的暴露部分。
如图4B中所描绘,一或多个第一芯片30安置在第一重布层20的第一表面201上方。在一或多个实施例中,第一芯片30包含背向第一重布层20的第一表面201的若干电端子30P。在一些实施例中,电端子30P覆盖有钝化层33(诸如聚合层)且受钝化层33保护。在一或多个实施例中,第一芯片30透过粘着层31(诸如裸片附着膜(DAF))接合到第一重布层20的第一表面201。一或多个第二芯片36安置在第一重布层20上方且电连接到第一重布层20。
如图4C中所描绘,第一囊封物40形成在第一重布层20的第一表面201上方。在一或多个实施例中,第一囊封物40的材料是模塑料。在一些实施例中,底胶填充层42可形成在第一芯片30与第一重布层20之间及形成在第二芯片36与第一重布层20之间。在一些实施例中,第一囊封物40是成型底胶填充(MUF)层且因此无需额外底胶填充层。在一或多个实施例中,第一囊封物40覆盖第一芯片30及第二芯片36的上表面及侧壁。
如图4D中所描绘,通过(例如)研磨而去除第一囊封物40及钝化层33的一部分以暴露第二芯片36的第二端子C2及第一芯片30的电端子30P。在一或多个实施例中,第一囊封物40及钝化层33通过研磨而薄化。
如图4E中所描绘,绝缘层44形成在第一囊封物40上方。在一或多个实施例中,绝缘层44的材料可包含(但不限于)诸如PBO的有机绝缘材料。绝缘层44包含暴露第二芯片36的第二端子C2及第一芯片30的电端子30P的若干开口。
如图4F中所描绘,第二重布层70形成在第一囊封物40上方。第二重布层70具有彼此对置的第三表面703及第四表面704,且第三表面703面向第一表面201。第二重布层70透过第二端子C2电连接到第二芯片36且透过电端子30P电连接到第一芯片30。在一或多个实施例中,第二重布层70包含彼此堆叠的若干导电层72及若干绝缘层74。在一些实施例中,(若干)导电层72的材料可包含(但不限于)金属,诸如铜、钛、其类似者或其组合。(若干)绝缘层74的材料可包含(但不限于)无机及/或有机绝缘材料。第一芯片30透过第二重布层70电连接到第二芯片36。在一或多个实施例中,最上导电层72的一部分从第二重布层70的第四表面704暴露。在一或多个实施例中,若干接合垫76(诸如凸块下金属(UBM))形成在第二重布层70的最上导电层72的暴露部分上方且电连接到第二重布层70的最上导电层72的暴露部分。
如图4G中所描绘,一或多个第三芯片50安置在第二重布层70上方且电连接到第二重布层70。第三芯片50透过第二重布层70电连接到第一芯片30。在一些实施例中,第一芯片30的电端子30P的一部分透过第二重布层70的一部分电连接到第三芯片50,且第一芯片30的电端子30P的另一部分透过第二重布层70的另一部分电连接到第二芯片36。
如图4H中所描绘,第二囊封物58形成在第二重布层70上方以覆盖第三芯片50。
如图4I中所描绘,第二囊封物58附着到暂时衬底60。接着,载体衬底10从第一重布层20的第二表面202拆离。
如图4J中所描绘,第二重布层70的一部分从第四表面704去除以暴露经配置为接合垫的最下导电层72。在一或多个实施例中,第二重布层70通过诸如干式蚀刻的蚀刻而去除。若干导体64形成在第二重布层70的第四表面704上方且电连接到第二重布层70。在一或多个实施例中,导体64包含(但不限于)导电凸块。在一或多个实施例中,一或多个第四芯片66安置在第一重布层20的第二表面202上方且电连接到第二重布层70。在一或多个实施例中,执行单粒化操作以形成若干半导体封装结构3。接着,半导体封装结构3从暂时衬底60去除,如图4K中所展示。
在半导体封装结构3中,第三芯片50透过第二重布层70电连接到第一芯片30。第一芯片30透过面向第二重布层70的电端子30P电连接到第二重布层70。第一芯片30还透过第二重布层70及具有通孔结构36C(其具有精细节距)的第二芯片36电连接到第一重布层20。第二芯片36避免在第一芯片30中形成通孔结构,其有助于改进第一芯片30的成出率。第二芯片36经配置以提供可与具有高I/O密度的芯片(诸如存储器芯片)集成的数目增加I/O计数。
图5是根据本揭露的一或多个实施例的半导体封装结构的横截面图。如图5中所描绘,半导体封装结构4包含第一重布层20、一或多个第一芯片30、一或多个第二芯片36、第一囊封物40、第二重布层70及一或多个第三芯片50。第一芯片30安置在第一重布层20上方且透过电端子30P电连接到第一重布层20。第二芯片36安置在第一重布层20上方且电连接到第一重布层20及第二重布层70。第一囊封物40安置在第一重布层20上方,且包围第一芯片30及第二芯片36。第二重布层70安置在第一囊封物40上方。第三芯片50安置在第二重布层70上方且电连接到第二重布层70。在一或多个实施例中,半导体封装结构4更包含安置在第二重布层70上方的第二囊封物58及安置在第二囊封物58上方的一或多个第五芯片82。在一或多个实施例中,第五芯片82是诸如存储器封装的封装。在一或多个实施例中,第二囊封物58是成型底胶填充(MUF)层。在一或多个实施例中,第二囊封物58是底胶填充(UF)层。第五芯片82透过第二囊封物58中的第一互连件78电连接到第二重布层70。在一或多个实施例中,第一互连件78是(但不限于)导电凸块。
图6是根据本揭露的一或多个实施例的半导体封装结构的横截面图。如图6中所描绘,不同于半导体封装结构4,半导体封装结构5更包含介于第三芯片50与第二重布层70之间的底胶填充层59。在一或多个实施例中,第二囊封物58经配置为包围底胶填充层59的第二底胶填充层。
图7是根据本揭露的一或多个实施例的半导体封装结构的横截面图。如图7中所描绘,不同于半导体封装结构5,半导体封装结构6的第一互连件78包含导电凸块782及导电柱781,且导电凸块782耦合到导电柱781。在一或多个实施例中,导电凸块782是焊料凸块或焊料膏,其中导电凸块782的一端电连接到第五芯片82,且另一端电连接到各自导电柱781。导电柱781及导电凸块782的制造及材料是不同的。在一或多个实施例中,导电柱781通过沉积、光刻及蚀刻操作而形成,且因此可减小相邻导电柱781之间的节距。相应地,与导电凸块782相关联的导电柱781能够实现第二重布层70与第五芯片82之间的精细节距接合。在一或多个实施例中,第二囊封物58包含模塑料581及位于模塑料581上方的底胶填充层582。模塑料581安置在第二重布层70上方且包围第一芯片30及导电柱781的侧壁。底胶填充层582包围导电凸块782的侧壁。
图8A、8B、8C、8D、8E、8F、8G、8H及8I是根据本揭露的一或多个实施例的制造半导体封装结构的各种操作的一者中的横截面图。如图8A中所描绘,第一重布层20形成在载体衬底10上方。在一或多个实施例中,第二互连件84形成在第一重布层20的第一表面201上方且电连接到第一重布层20的第一表面201。在一些实施例中,第二互连件84是穿绝缘体通孔(TIV)。
如图8B中所描绘,一或多个第一芯片30安置在第一重布层20的第一表面201上方。一或多个第二芯片36安置在第一重布层20上方且电连接到第一重布层20。在一些实施例中,第一芯片30可包含不同类型的芯片且可具有不同厚度。举例来说,一些第一芯片30可包含诸如芯片上系统(SOC)的有源装置芯片,且一些第一芯片30可包含无源装置芯片。
如图8C中所描绘,第一囊封物40形成在第一重布层20的第一表面201上方。在一或多个实施例中,第一囊封物40的材料是模塑料。在一些实施例中,底胶填充层42可形成在第一芯片30与第一重布层20之间及形成在第二芯片36与第一重布层20之间。在一些实施例中,第一囊封物40是成型底胶填充(MUF)层且因此可无需额外底胶填充层。
如图8D中所描绘,通过(例如)研磨而去除第一囊封物40的一部分以暴露第二芯片36的第二端子C2。
如图8E中所描绘,绝缘层44形成在第一囊封物40上方。绝缘层44包含暴露第二芯片36的第二端子C2的开口。第二重布层70形成在第一囊封物40上方。第二重布层70透过第二端子C2电连接到第二芯片36。在一或多个实施例中,第二重布层70包含彼此堆叠的若干导电层72及若干绝缘层74。在一或多个实施例中,最上导电层72的一部分从第二重布层70的第四表面704暴露。在一或多个实施例中,若干接合垫76(诸如凸块下金属(UBM))形成在第二重布层70的最上导电层72的暴露部分上方且电连接到第二重布层70的最上导电层72的暴露部分。
如图8F中所描绘,一或多个第三芯片50安置在第二重布层70上方且电连接到第二重布层70。在一些实施例中,第三芯片50的一部分透过第二重布层70及第一芯片30电连接到第一重布层20。在一些实施例中,第三芯片50的另一部分透过第二重布层70及第二互连件84电连接到第一重布层20。在一些实施例中,第三芯片50的一部分经由接合线51(诸如金线)电连接到第二重布层70。在一或多个实施例中,第三芯片50包含存储器芯片、光电芯片、MEMS芯片、无源芯片或其组合。
如图8G中所描绘,第二囊封物58形成在第二重布层70上方以覆盖第三芯片50。
如图8H中所描绘,第二囊封物58附着到暂时衬底60。接着,载体衬底10从第一重布层20的第二表面202拆离。在一些实施例中,第二重布层70的一部分从第四表面704去除以暴露经配置为接合垫的最下导电层72。在一或多个实施例中,第二重布层70通过诸如干式蚀刻的蚀刻而去除。若干导体64形成在第二重布层70的第四表面704上方且电连接到第二重布层70。在一或多个实施例中,导体64包含(但不限于)导电凸块。在一或多个实施例中,一或多个第四芯片66安置在第一重布层20的第二表面202上方且电连接到第二重布层70。在一或多个实施例中,执行单粒化操作以形成若干半导体封装结构7。接着,半导体封装结构7从暂时衬底60去除,如图8I中所展示。
图9是根据本揭露的一或多个实施例的半导体封装结构的横截面图。如图9中所描绘,半导体封装结构8的一或多个第三芯片50的上表面50U从第二囊封物58暴露,使得第三芯片50能够建立外部通信。在一些实施例中,第三芯片50可包含光电芯片(诸如CMOS图像传感器芯片)、MEMS芯片及高功率芯片。
图10是根据本揭露的一或多个实施例的半导体封装结构的横截面图。如图10中所描绘,半导体封装结构9更包含第二囊封物58及第三芯片50上方的散热器90。散热器90由具有高导热性的材料(诸如金属)形成且经配置以改进第三芯片50的散热性。在一些实施例中,第三芯片50可包含光电芯片(诸如CMOS图像传感器芯片)、MEMS芯片、存储器芯片、高功率芯片、在操作期间产生热的其它芯片或其它热敏芯片。
在一或多个实施例中,半导体封装结构包含诸如芯片的若干堆叠电子装置。包含通孔结构的第二芯片经安置以提供两个电子装置之间的高密度互连及高选路灵活性。第二芯片提供用于芯片之间的互连的短信号路径。在一或多个实施例中,半导体封装结构是扇出晶片级封装(FOWLP)。在一或多个实施例中,半导体封装结构与具有小外型尺寸的多层堆叠芯片兼容。在一或多个实施例中,半导体封装结构与异质集成设计(其中可集成具有不同大小及厚度的不同电子装置,诸如半导体裸片、芯片、封装及中介层)兼容。在一或多个实施例中,半导体封装结构与散热器兼容以增强散热能力。
在一例示性方面中,一种半导体封装结构包含重布层(RDL)、第一芯片、第二芯片、囊封物及第三芯片。所述重布层具有彼此对置的第一表面及第二表面。所述第一芯片位于所述重布层的所述第一表面上方且电连接到所述重布层。所述第二芯片位于所述重布层的所述第一表面上方且电连接到所述重布层。所述第二芯片包含多个通孔结构。所述囊封物位于所述重布层的所述第一表面上方,其中所述囊封物包围所述第一芯片及所述第二芯片。所述第三芯片位于所述囊封物上方且透过所述第二芯片的所述通孔结构及所述重布层电连接到所述第一芯片。
在另一例示性方面中,一种半导体封装结构包含第一重布层(RDL)、第一芯片、第二芯片、第一囊封物、第二重布层、第三芯片及第二囊封物。所述第一重布层具有彼此对置的第一表面及第二表面。所述第一芯片位于所述第一重布层的所述第一表面上方。所述第二芯片位于所述第一重布层的所述第一表面上方。所述第二芯片包含多个通孔结构,且所述通孔结构的第一端子耦合到所述第一重布层。所述第一囊封物位于所述第一重布层的所述第一表面上方,其中所述第一囊封物包围所述第一芯片及所述第二芯片。所述第二重布层位于所述第一囊封物上方且电连接到所述通孔结构的第二端子。所述第二重布层具有彼此对置的第三表面及第四表面,且所述第三表面面向所述第一表面。所述第三芯片位于所述第二重布层的所述第四表面上方且电连接到所述第二重布层。所述第二囊封物位于所述第二重布层上方。
在又一方面中,一种用于制造半导体封装结构的方法包含以下操作。形成第一重布层。将第一芯片安置在所述第一重布层上方。将第二芯片安置在所述第一重布层上方,其中所述第二芯片包含多个通孔结构。使囊封物形成在所述第一重布层上方。使第三芯片形成在所述囊封物上方,其中所述第三芯片及所述第一重布层透过所述第二芯片的所述通孔结构电连接。
上文已概述若干实施例的结构,使得所属领域的技术人员可较佳理解本揭露的方面。所属领域的技术人员应了解,其可容易地使用本揭露作为设计或修改用于实施相同目的及/或达成本文所引入的实施例的相同优点的其它制程及结构的基础。所属领域的技术人员还应认识到,此类等效构造不应背离本揭露的精神及范围,且其可在不背离本揭露的精神及范围的情况下对本文作出各种改变、取代及更改。
符号说明
1 半导体封装结构
2 半导体封装结构
3 半导体封装结构
4 半导体封装结构
5 半导体封装结构
6 半导体封装结构
7 半导体封装结构
8 半导体封装结构
9 半导体封装结构
10 载体衬底
20 第一重布层
22 导电层
24 绝缘层
26 接合垫
30 第一芯片
30P 电端子
31 粘着层
32 导电材料
33 钝化层
36 第二芯片
36C 通孔结构
36P 接触垫
38 导电材料
40 第一囊封物
42 底胶填充层
44 绝缘层
46 接合垫
48 导电材料
50 第三芯片
50U 上表面
51 接合线
52 DRAM装置
54 互连件
56 通孔结构
58 第二囊封物
59 底胶填充层
60 暂时衬底
62 框架
64 导体
66 第四芯片
70 第二重布层
72 导电层
74 绝缘层
76 接合垫
78 第一互连件
82 第五芯片
84 第二互连件
90 散热器
100 方法
110 操作
120 操作
130 操作
140 操作
150 操作
201 第一表面
202 第二表面
581 模塑料
582 底胶填充层
703 第三表面
704 第四表面
781 导电柱
782 导电凸块
C1 第一端子
C2 第二端子

Claims (1)

1.一种半导体封装结构,其包括:
重布层,其具有彼此对置的第一表面及第二表面;
第一芯片,其位于所述重布层的所述第一表面上方且电连接到所述重布层;
第二芯片,其位于所述重布层的所述第一表面上方,其中所述第二芯片包含多个通孔结构;
囊封物,其位于所述重布层的所述第一表面上方,其中所述囊封物包围所述第一芯片及所述第二芯片;及
第三芯片,其位于所述囊封物上方且透过所述第二芯片的所述通孔结构及所述重布层电连接到所述第一芯片。
CN201710664209.1A 2016-09-02 2017-08-04 半导体封装结构及其制造方法 Active CN107799499B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662382912P 2016-09-02 2016-09-02
US62/382,912 2016-09-02
US15/388,434 2016-12-22
US15/388,434 US10535632B2 (en) 2016-09-02 2016-12-22 Semiconductor package structure and method of manufacturing the same

Publications (2)

Publication Number Publication Date
CN107799499A true CN107799499A (zh) 2018-03-13
CN107799499B CN107799499B (zh) 2022-11-29

Family

ID=61280764

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710664209.1A Active CN107799499B (zh) 2016-09-02 2017-08-04 半导体封装结构及其制造方法

Country Status (3)

Country Link
US (3) US10535632B2 (zh)
CN (1) CN107799499B (zh)
TW (1) TWI719202B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111063663A (zh) * 2018-10-16 2020-04-24 力成科技股份有限公司 双面扇出型系统级封装结构
CN111755344A (zh) * 2019-03-28 2020-10-09 台湾积体电路制造股份有限公司 封装结构及其形成方法
CN111952296A (zh) * 2019-05-15 2020-11-17 联发科技股份有限公司 半导体封装

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018063263A1 (en) 2016-09-29 2018-04-05 Intel Corporation Panel level packaging for multi-die products interconnected with very high density (vhd) interconnect layers
US10217720B2 (en) * 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10461022B2 (en) * 2017-08-21 2019-10-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof
KR101982057B1 (ko) * 2017-11-30 2019-05-24 삼성전기주식회사 팬-아웃 반도체 패키지
TWI678766B (zh) * 2018-04-26 2019-12-01 沅顧科技有限公司 一種製造一系統於一可主動控制基板上的方法
US11276676B2 (en) * 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US11424197B2 (en) * 2018-07-27 2022-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package, package structure with redistributing circuits and antenna elements and method of manufacturing the same
US10665572B2 (en) * 2018-08-15 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
KR102536269B1 (ko) * 2018-09-14 2023-05-25 삼성전자주식회사 반도체 패키지 및 그 제조 방법
TWI679744B (zh) * 2018-10-04 2019-12-11 力成科技股份有限公司 多層封裝基板
WO2020071021A1 (ja) * 2018-10-05 2020-04-09 株式会社村田製作所 高周波モジュールおよび通信装置
KR102538181B1 (ko) 2018-10-24 2023-06-01 삼성전자주식회사 반도체 패키지
KR102530320B1 (ko) * 2018-11-21 2023-05-09 삼성전자주식회사 반도체 패키지
KR102624986B1 (ko) * 2018-12-14 2024-01-15 삼성전자주식회사 반도체 패키지
US10770433B1 (en) 2019-02-27 2020-09-08 Apple Inc. High bandwidth die to die interconnect with package area reduction
US11133282B2 (en) * 2019-05-31 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. COWOS structures and methods forming same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
KR102653499B1 (ko) * 2019-06-28 2024-03-29 삼성전자주식회사 반도체 패키지
US11450733B2 (en) * 2019-07-18 2022-09-20 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional metal insulator metal capacitor structure
KR20210011279A (ko) * 2019-07-22 2021-02-01 삼성전자주식회사 반도체 패키지
US11410902B2 (en) * 2019-09-16 2022-08-09 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US10943883B1 (en) 2019-09-19 2021-03-09 International Business Machines Corporation Planar wafer level fan-out of multi-chip modules having different size chips
US11824040B2 (en) * 2019-09-27 2023-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package component, electronic device and manufacturing method thereof
US11587905B2 (en) 2019-10-09 2023-02-21 Industrial Technology Research Institute Multi-chip package and manufacturing method thereof
TWI701777B (zh) * 2019-10-22 2020-08-11 財團法人工業技術研究院 影像感測器封裝件及其製造方法
US11791275B2 (en) * 2019-12-27 2023-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacturing
TWI768294B (zh) * 2019-12-31 2022-06-21 力成科技股份有限公司 封裝結構及其製造方法
US11837559B2 (en) 2020-04-03 2023-12-05 Wolfspeed, Inc. Group III nitride-based radio frequency amplifiers having back side source, gate and/or drain terminals
KR20220158261A (ko) 2020-04-03 2022-11-30 울프스피드, 인크. 소스, 게이트 및/또는 드레인 도전성 비아들을 갖는 iii족 질화물계 라디오 주파수 트랜지스터 증폭기들
KR20220001956A (ko) * 2020-06-30 2022-01-06 삼성전자주식회사 집적회로 소자 및 이를 포함하는 반도체 패키지
US20220037243A1 (en) * 2020-07-31 2022-02-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method
US11735554B2 (en) * 2020-08-14 2023-08-22 Sj Semiconductor (Jiangyin) Corporation Wafer-level chip scale packaging structure having a rewiring layer and method for manufacturing the wafer-level chip scale packaging structure
KR20220031237A (ko) * 2020-09-04 2022-03-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US11538761B2 (en) * 2021-01-07 2022-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having molded die and semiconductor die and manufacturing method thereof
TWI759095B (zh) * 2021-02-04 2022-03-21 欣興電子股份有限公司 封裝結構及其製作方法
TWI756094B (zh) * 2021-03-31 2022-02-21 力成科技股份有限公司 封裝結構及其製造方法
US20220367413A1 (en) * 2021-05-13 2022-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Packages With Multiple Types of Underfill and Method Forming The Same
US20230065615A1 (en) * 2021-08-27 2023-03-02 Advanced Semiconductor Engineering, Inc. Electronic device
WO2023135720A1 (ja) * 2022-01-14 2023-07-20 キヤノン株式会社 モジュールおよび機器

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100133704A1 (en) * 2008-12-01 2010-06-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias
US20110304045A1 (en) * 2010-06-15 2011-12-15 Chipmos Technologies Inc. Thermally enhanced electronic package and method of manufacturing the same
CN103021960A (zh) * 2011-09-27 2013-04-03 台湾积体电路制造股份有限公司 三维集成电路的制造方法
US20140191379A1 (en) * 2011-07-18 2014-07-10 Jiangyin Changdian Advanced Packaging Co., Ltd. Low-k chip packaging structure
CN104347601A (zh) * 2013-07-23 2015-02-11 三星电子株式会社 半导体封装件及其制造方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG106054A1 (en) * 2001-04-17 2004-09-30 Micron Technology Inc Method and apparatus for package reduction in stacked chip and board assemblies
TW566673U (en) * 2002-07-25 2003-12-11 Advanced Semiconductor Eng Semiconductor wafer and semiconductor device
US8178963B2 (en) * 2007-01-03 2012-05-15 Advanced Chip Engineering Technology Inc. Wafer level package with die receiving through-hole and method of the same
US7564115B2 (en) 2007-05-16 2009-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tapered through-silicon via structure
US7973413B2 (en) 2007-08-24 2011-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate via for semiconductor device
US8227902B2 (en) 2007-11-26 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Structures for preventing cross-talk between through-silicon vias and integrated circuits
US7843064B2 (en) 2007-12-21 2010-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and process for the formation of TSVs
US8278152B2 (en) 2008-09-08 2012-10-02 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding process for CMOS image sensor
US7825024B2 (en) 2008-11-25 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming through-silicon vias
US8158456B2 (en) * 2008-12-05 2012-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming stacked dies
US8183579B2 (en) 2010-03-02 2012-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. LED flip-chip package structure with dummy bumps
US8183578B2 (en) 2010-03-02 2012-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Double flip-chip LED package components
US8426961B2 (en) 2010-06-25 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded 3D interposer structure
US8581418B2 (en) * 2010-07-21 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-die stacking using bumps with different sizes
US8105875B1 (en) 2010-10-14 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for bonding dies onto interposers
US9167694B2 (en) * 2010-11-02 2015-10-20 Georgia Tech Research Corporation Ultra-thin interposer assemblies with through vias
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US8803292B2 (en) 2012-04-27 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias and methods for forming the same
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US8975726B2 (en) * 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US20150287697A1 (en) 2014-04-02 2015-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US10475770B2 (en) * 2017-02-28 2019-11-12 Amkor Technology, Inc. Semiconductor device having stacked dies and stacked pillars and method of manufacturing thereof
US10707050B2 (en) * 2018-07-26 2020-07-07 Varian Semiconductor Equipment Associates, Inc. System and method to detect glitches

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100133704A1 (en) * 2008-12-01 2010-06-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias
US20110304045A1 (en) * 2010-06-15 2011-12-15 Chipmos Technologies Inc. Thermally enhanced electronic package and method of manufacturing the same
US20140191379A1 (en) * 2011-07-18 2014-07-10 Jiangyin Changdian Advanced Packaging Co., Ltd. Low-k chip packaging structure
CN103021960A (zh) * 2011-09-27 2013-04-03 台湾积体电路制造股份有限公司 三维集成电路的制造方法
CN104347601A (zh) * 2013-07-23 2015-02-11 三星电子株式会社 半导体封装件及其制造方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111063663A (zh) * 2018-10-16 2020-04-24 力成科技股份有限公司 双面扇出型系统级封装结构
CN111063663B (zh) * 2018-10-16 2021-08-24 力成科技股份有限公司 双面扇出型系统级封装结构
CN111755344A (zh) * 2019-03-28 2020-10-09 台湾积体电路制造股份有限公司 封装结构及其形成方法
US11239173B2 (en) 2019-03-28 2022-02-01 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out feature
CN111755344B (zh) * 2019-03-28 2023-10-24 台湾积体电路制造股份有限公司 封装结构及其形成方法
US11948892B2 (en) 2019-03-28 2024-04-02 Taiwan Semiconductor Manufacturing Company, Ltd. Formation method of chip package with fan-out feature
CN111952296A (zh) * 2019-05-15 2020-11-17 联发科技股份有限公司 半导体封装
US11508707B2 (en) 2019-05-15 2022-11-22 Mediatek Inc. Semiconductor package with dummy MIM capacitor die
CN111952296B (zh) * 2019-05-15 2023-09-12 联发科技股份有限公司 半导体封装

Also Published As

Publication number Publication date
US10804244B2 (en) 2020-10-13
TW201813016A (zh) 2018-04-01
US20200411474A1 (en) 2020-12-31
US20200152603A1 (en) 2020-05-14
US20180068978A1 (en) 2018-03-08
TWI719202B (zh) 2021-02-21
US10535632B2 (en) 2020-01-14
US11469208B2 (en) 2022-10-11
CN107799499B (zh) 2022-11-29

Similar Documents

Publication Publication Date Title
CN107799499A (zh) 半导体封装结构及其制造方法
KR102660697B1 (ko) 반도체 장치 및 그 제조 방법
CN108417563B (zh) 半导体装置封装和其制造方法
US10658337B2 (en) Packages and packaging methods for semiconductor devices, and packaged semiconductor devices
US10157887B2 (en) Semiconductor device package and method of manufacturing the same
US9343333B2 (en) Wafer level semiconductor package and manufacturing methods thereof
CN103681367B (zh) 封装方法和封装器件
CN103681368B (zh) 半导体装置和将线柱形成为fo‑wlp中的垂直互连的方法
CN104064551B (zh) 一种芯片堆叠封装结构和电子设备
TWI469309B (zh) 積體電路封裝系統
CN103515260B (zh) 封装内封装及其形成方法
KR101653856B1 (ko) 반도체 장치 및 그 제조방법
US9159708B2 (en) Stackable molded microelectronic packages with area array unit connectors
EP3093877A2 (en) Semiconductor package and fabrication method thereof
TWI714120B (zh) 封裝層電感器
CN105097750A (zh) 封装结构及其制法
KR20180065937A (ko) 3d 인터포저 시스템-인-패키지 모듈을 형성하기 위한 반도체 소자 및 방법
CN106328632A (zh) 电子封装件及其制法
TWI717563B (zh) 半導體裝置封裝
CN110112115A (zh) 集成电路封装件及其形成方法
CN111052366A (zh) 具有保护机制的半导体装置及其相关系统、装置及方法
CN107452702A (zh) 半导体芯片的封装结构及封装方法
TWI636537B (zh) 扇出型多晶片堆疊封裝之電子裝置及形成該裝置之方法
CN107425031A (zh) 背照式cmos传感器的封装结构及封装方法
TWI441312B (zh) 具有打線結構之三維立體晶片堆疊封裝結構

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant