US20140191379A1 - Low-k chip packaging structure - Google Patents

Low-k chip packaging structure Download PDF

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Publication number
US20140191379A1
US20140191379A1 US14/233,596 US201114233596A US2014191379A1 US 20140191379 A1 US20140191379 A1 US 20140191379A1 US 201114233596 A US201114233596 A US 201114233596A US 2014191379 A1 US2014191379 A1 US 2014191379A1
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Prior art keywords
metal
chip
low
film layer
layer
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US14/233,596
Inventor
Li Zhang
Zhiming Lai
Dong Chen
Jinhui Chen
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Jiangyin Changdian Advanced Packaging Co Ltd
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Jiangyin Changdian Advanced Packaging Co Ltd
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Assigned to JIANGYIN CHANGDIAN ADVANCED PACKAGING CO., LTD. reassignment JIANGYIN CHANGDIAN ADVANCED PACKAGING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, DONG, CHEN, JINHUI, LAI, Zhiming, ZHANG, LI
Publication of US20140191379A1 publication Critical patent/US20140191379A1/en
Abandoned legal-status Critical Current

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

Definitions

  • the present invention relates to a low-k chip packaging structure, and belongs to the technical field of chip packaging.
  • the line width nodes of chips have mainly underwent the following several stages: 0.18 ⁇ m stage—the initial stage of semiconductor process technology, in which MOS tubes became popularized and chips were manufactured in relatively large sizes; 0.13 ⁇ m stage—in that stage, people were faith confident in semiconductor process technology and hoped to reduce chip area and cost by decreasing the feature size; those two stages were usually referred to as micrometer process technology stages. With the developed of nanometer technology, people's vision was no longer hunted to micrometer technology but turned to nano-scale semiconductor process technology.
  • Low-k dielectric loss constant
  • Porous materials are usually selected as low-k materials, as a result, the low-k materials are relatively brittle and may be easily fractured under external stress, causing line failures.
  • the chip packaging process and the chip structure have to be improved appropriately to adapt to the requirement for product application.
  • the packaging of low-k products still employs conventional flip-chip bonding or wire bonding, which results in severe loss of packaging yield.
  • the result of failure analysis indicates that the failure is mainly resulted from fracture of the dielectric layer under bonding electrodes (wire bonding and flip-chip bonding).
  • the general solution is to replace wire bonding packaging with flip-chip bonding packaging, and mange non-flow underfill on the substrate before flip-chip bonding.
  • the packaging structure is shown in FIG. 1 .
  • the underfill has features of ordinary underfill and features of fellow flux, therefore, the solder balls and the bonding pad on the substrate can wet each other.
  • the advantage of this method is that injuries to the dielectric layer in the chip caused by the stress of soldered balls during reflow in the conventional flip-chip packaging process can be alleviated, that is to say, the stress is redistributed via the non-flow underfill dining reflow, and thereby the dielectric layer in the chip will not be injured owing to stress concentration.
  • the biggest disadvantage of this method is that, owing to the existence of the underfill, the flux wetting effect is not enough to ensure that every soldered ball is bonded well to the bonding pad; in addition, cavities may occur in the underfill during the curing process owing to the existence of flux and the application of reflow.
  • the present invention provides a low-k chip packaging structure and a method for low-k chip packaging, which can prevent low-k chip failures resulted from stress concentration in the chip packaging process and provide a low-cost packaging solution for low-k chips.
  • a low-V chip packaging .structure comprising a chip body I. chip electrodes, and a chip. surface passivation layer, wherein, the chip body I is Wrapped With a film layer I, a supporting wafer is arranged on the back of the film layer I, the chip electrodes are led via metal redistribution wires to the film layer I in the peripheral area.
  • metal posts are arranged at the terminals of the metal redistribution wires, and the metal posts are wrapped with a film layer II, and the top of the metal posts is exposed out of the film layer II; a metal layer, with a solder bump on it, is arranged on the exposed top of each metal post.
  • the metal posts are made of electrical-conductive metals such as copper or nickel, etc . . . and the metal posts are in height within the range of 50 ⁇ m-100 ⁇ m.
  • the metal layer consists of a plurality of metal, and has a Ni/Au or Ni/Pd/Au structure, and the thickness of the metal layer is not greater than 5 ⁇ m.
  • a chip body II is embedded in the film layer I.
  • the metal redistribution wires are formed by metal wiring layer I and metal wiring layer II.
  • Both the film layer I and the film layer II are made of a non-photo-sensitive materials.
  • the supporting wafer is a silicon wafer or a metal wafer.
  • the bearer wafer adopts a silicon substrate or a glass substrate.
  • the present invention has the following advantages:
  • the chip electrodes are extended to the non-chip area by wire redistribution through a wafer-level process; therefore, the stress generated in attachment process of BGA structure is transferred, then the chip area is no longer in stressed state:
  • Metal post technique and structure are utilized to implement high power current carrying and uniform current distribution; in addition, the height of the copper posts is utilized to buffer the stress from BGA bumps, so that the stress will not be transferred to the redistribution layer;
  • Bumping technique, flip-chip technique and substrate technique are integrated to implement a BGA packaged wafer manufacturing process.
  • FIG. 1 is a schematic diagram of the low-k chip packaging structure in the prior art
  • FIG. 2 is a schematic diagram of the low-k chip packaging structure disclosed in embodiment 1 of the present invention.
  • FIG. 3 is a schematic diagram of the low-k chip packaging structure disclosed in embodiment 2 of the present invention.
  • FIG. 4 is a schematic diagram of the low-k chip packaging structure disclosed in embodiment 3 of the present invention.
  • the present invention provides a low-k chip packaging structure, comprising chip body I 2 - 1 , chip electrodes 2 - 2 , and chip surface passivation layer 2 - 3 , wherein, the chip body I 2 - 1 is wrapped with a film layer I 2 - 4 , the back of the film layer I 2 - 4 is bonded with a supporting wafer 2 - 5 , the chip electrodes 2 - 2 are led to the film layer I 2 - 4 in the peripheral area.
  • metal posts 2 - 7 are arranged at the terminals of the metal redistribution wires 2 - 6 , and the metal posts 2 - 7 are wrapped with a film layer II 2 - 8 , with the top of the metal posts 2 - 7 exposed out of the film layer II 2 - 8 ; a metal layer 2 - 9 , with a solder bump 2 - 10 on it, is arranged on the exposed top of the metal posts 2 - 7 .
  • a chip body II 2 - 11 is embedded in the film layer I 2 - 4 .
  • the metal redistribution wires 2 - 6 are formed by metal wiring layer I 2 - 6 - 1 and metal wiring layer II 2 - 6 - 2 .
  • Step 1 taking a low-k wafer and cutting it into individual chips.
  • Step 2 funning aligning marks by photo-lithography on a bearer wafer to complete the pattern layout on the bearer wafer;
  • the bearer wafer can be a silicon substrate or a glass substrate. Aligning marks are formed on the bearer wafer to facilitate the follow-up flip-chip mounting process and keep the chips at ideal positions.
  • Step 3 attaching a temporary strippable film to the bearer wafer and flip-chip mounting the chips obtained in step 1 one by one to the bearer wafer attached with the temporary strippable film.
  • the temporary strippable film is adhesive on both sides, and can bond well with both the bearer wafer and the subsequently flip-chip mounted chips.
  • the strippable film is thermally strippable or UV strippable. If the strippable film is UV strippable, a bearer wafer should be glass substrate or quartz substrate since LW irradiation is required for UV stripping. Accordingly, the substrate must be transparent for UV transmission,
  • Flip-chip mounting is selected for two purposes: one is to ensure chips different in thickness can be mounted with the face side in the same plane in the subsequent process, the other is to prevent glue coverage on the face side of the chips on the restructured wafer; so as to facilitate subsequent processing.
  • step 4 attaching a film layer I 2 - 4 to the bearer wafer for encapsulation after flip-chip mounting of the chips, bonding a supporting wafer 2 - 5 to the film, layer I 2 - 4 in the encapsulation process, and curing the film layer I 2 - 4 , then forming a restructured wafer composed of the chips, film layer I 2 - 4 and supporting wafer 2 - 5 .
  • the supporting wafer 2 - 5 is a silicon wafer or a metal wafer, and the wafer surface is kept smooth in the encapsulation process because the film layer I 2 - 4 has good fluidity under heating.
  • Step 5 shipping the restructured wafer from the bearer wafer by UV irradiation or thermal stripping and cleaning the surface of the chips on the restructured wafer to expose the chip electrodes 2 - 2 .
  • Step 6 forming single-layer or multi-layer metal redistribution wires 2 - 6 on the surface of the film layer I 2 - 4 and the chips by wafer-level photo-lithography, sputtering, or electroplating, so as to lead the chip electrodes 2 - 2 to the peripheral area of the chips (the area without chip) via metal redistribution wires 2 - 6 .
  • Step 7 forming metal posts 2 - 7 at the terminals of metal redistribution wires 2 - 6 by photo-lithography or electroplating,
  • the metal posts 2 - 7 are made of an electrical-conductive metal material such as copper or nickel, etc.; the height of the metal posts 2 - 7 can be adjusted according to the requirements of the structure and shall not be smaller than 50 ⁇ m, generally, the height of the metal posts 2 - 7 is within the range of 50 ⁇ m-100 ⁇ m.
  • the metal posts 2 - 7 have two functions: one function is to reduce crowding effect of electric current, i.e., with the metal posts, the electric current can be distributed uniformly and thereby the phenomenon of electric. migration can be reduced: the other .function is to utilize the height of the metal posts 2 - 7 to buffer the stress from the bumps 2 - 10 and thereby protect the low-k chips.
  • Step 8 attaching as film layer II 2 - 8 to the surface of the restructured wafer with the metal posts 2 - 7 for encapsulation curing the package, and then removing the film material on the top of the metal posts by laser ablation, to form complete Or partial openings on the metal posts 2 - 7 and expose the top of the metal posts 2 - 7 out of the film layer II 2 - 8 .
  • the film layer I 2 - 4 and film layer II 2 - 8 are made of non-photo-sensitive insulating resin materials.
  • Step 9 coating a metal layer 2 - 9 on the top of the metal posts 2 - 7 exposed out of the film layer II 2 - 8 .
  • the metal layer 2 - 9 adopts single layer metal or multilayer metal.
  • the multilayer metal usually has a Ni/Au or Ni/Pd/Au structure.
  • the thickness of the metal layer 2 - 9 should not be greater than 5 ⁇ m.
  • the metal layer 2 - 9 is used to prevent inter-diffusion between stannum and copper in the soldering flux and improve product reliability.
  • Step 10 forming BGA solder bumps 2 - 10 on the metal layer 2 - 9 by printing or bumping and finally cutting the restructured wafer with BGA solder bumps into individual BGA packages.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

A low-k chip packaging structure comprising chip body I (2-1), a chip electrode (2-2), and a chip surface passivation layer (2-3). Chip body I (2-1) has coated thereon thin film layer I (2-3). Thin film layer I (2-3) has arranged on a rear face thereof a support wafer (2-5). A chip electrode (2-2) is transferred to thin film layer I (2-4) around the exterior of the chip via a rewired metal wiring (2-6). The rewired metal wiring (2-6) has arranged at an end thereof a metal column (2-7). The metal column (2-7) has coated thereon thin film layer II (2-8). The top of the metal column protrudes thin film layer II (2-8). The protruding top of the metal column (2-7) has arranged thereon a metal layer (2-9). The metal layer (2-9) has arranged thereon soldering balls (2-10). The low-k chip packaging structure solves the problem of invalid low-k chip due to concentration of stress during chip packaging process and allows for reduced packaging costs and great product reliability.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a low-k chip packaging structure, and belongs to the technical field of chip packaging.
    • BACKGROUND ART
  • In the semiconductor manufacturing industry, the Moore's Law was always the power that pushed the industry to develop continuously, and Intel made great contributions in that aspect. The line width nodes of chips have mainly underwent the following several stages: 0.18 μm stage—the initial stage of semiconductor process technology, in which MOS tubes became popularized and chips were manufactured in relatively large sizes; 0.13 μm stage—in that stage, people were faith confident in semiconductor process technology and hoped to reduce chip area and cost by decreasing the feature size; those two stages were usually referred to as micrometer process technology stages. With the developed of nanometer technology, people's vision was no longer hunted to micrometer technology but turned to nano-scale semiconductor process technology. 90 nm process technology emerged first, and as the quantity of tube cores on unit area increased exponentially following the Moore's Law, 65 nm, 45 nm, 32 nm, and current 22 nm process technology emerged successively. However, the sharp reduction of feature size led to a pursuit for low dielectric loss constant (usually referred to as Low-k) of dielectric materials, for the purpose of reducing parasitic resistance, capacitance and inductance in circuits while ensuring favorable insulating performance of the circuits. Porous materials are usually selected as low-k materials, as a result, the low-k materials are relatively brittle and may be easily fractured under external stress, causing line failures.
  • Owing to the brittleness of low-k materials, the chip packaging process and the chip structure have to be improved appropriately to adapt to the requirement for product application. Up to now, the packaging of low-k products still employs conventional flip-chip bonding or wire bonding, which results in severe loss of packaging yield. The result of failure analysis indicates that the failure is mainly resulted from fracture of the dielectric layer under bonding electrodes (wire bonding and flip-chip bonding). At present, the general solution is to replace wire bonding packaging with flip-chip bonding packaging, and mange non-flow underfill on the substrate before flip-chip bonding. The packaging structure is shown in FIG. 1. The underfill has features of ordinary underfill and features of fellow flux, therefore, the solder balls and the bonding pad on the substrate can wet each other. The advantage of this method is that injuries to the dielectric layer in the chip caused by the stress of soldered balls during reflow in the conventional flip-chip packaging process can be alleviated, that is to say, the stress is redistributed via the non-flow underfill dining reflow, and thereby the dielectric layer in the chip will not be injured owing to stress concentration. However, the biggest disadvantage of this method is that, owing to the existence of the underfill, the flux wetting effect is not enough to ensure that every soldered ball is bonded well to the bonding pad; in addition, cavities may occur in the underfill during the curing process owing to the existence of flux and the application of reflow.
  • In summary, there are mainly two drawbacks in the low-k chip packaging process at present:
      • 1. With wire bonding and conventional flip-chip technology, stress concentration may occur at the chip electrodes because of stress produced in the technological process, resulting in fracture of the low-k dielectric layer and chip failure;
      • 2. With non-flow underfill, the flip-chip packaging process may generate poor bonding and cavities in the underfill after curing, causing degraded product reliability.
    DISCLOSURE OF THE INVENTION Technical Problem
  • To overcome the above-mentioned drawbacks, the present invention provides a low-k chip packaging structure and a method for low-k chip packaging, which can prevent low-k chip failures resulted from stress concentration in the chip packaging process and provide a low-cost packaging solution for low-k chips.
    • Technical Solution
  • The objects of the present invention are attained as follows: a low-V chip packaging .structure comprising a chip body I. chip electrodes, and a chip. surface passivation layer, wherein, the chip body I is Wrapped With a film layer I, a supporting wafer is arranged on the back of the film layer I, the chip electrodes are led via metal redistribution wires to the film layer I in the peripheral area. around the chip, metal posts are arranged at the terminals of the metal redistribution wires, and the metal posts are wrapped with a film layer II, and the top of the metal posts is exposed out of the film layer II; a metal layer, with a solder bump on it, is arranged on the exposed top of each metal post.
  • The metal posts are made of electrical-conductive metals such as copper or nickel, etc . . . and the metal posts are in height within the range of 50 μm-100 μm.
  • The metal layer consists of a plurality of metal, and has a Ni/Au or Ni/Pd/Au structure, and the thickness of the metal layer is not greater than 5 μm.
  • A chip body II is embedded in the film layer I.
  • The metal redistribution wires are formed by metal wiring layer I and metal wiring layer II.
  • Both the film layer I and the film layer II are made of a non-photo-sensitive materials.
  • The supporting wafer is a silicon wafer or a metal wafer.
  • The bearer wafer adopts a silicon substrate or a glass substrate.
    • Beneficial Effects
  • Compared to the prior art, the present invention has the following advantages:
      • 1. Since the chips are mounted onto the bearer wafer by direct flip-chip mounting, without experiencing reflow or stress concentration, therefore. Chip failures resulted from stress concentration in the flip-chip process of BGA packaging for low-k chips in the prior art can be prevented;
  • 2. The chip electrodes are extended to the non-chip area by wire redistribution through a wafer-level process; therefore, the stress generated in attachment process of BGA structure is transferred, then the chip area is no longer in stressed state:
  • 3. Metal post technique and structure are utilized to implement high power current carrying and uniform current distribution; in addition, the height of the copper posts is utilized to buffer the stress from BGA bumps, so that the stress will not be transferred to the redistribution layer;
  • 4. With wafer-level packaging technique and metal post technique, the packaging cost can be reduced while the low-k chips are packed with high
  • 5. The existing encapsulation technique in the prior art is replaced with a film attachment technique; therefore, the requirement for equipment in the packaging process is decreased;
  • 6. Bumping technique, flip-chip technique and substrate technique are integrated to implement a BGA packaged wafer manufacturing process.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic diagram of the low-k chip packaging structure in the prior art;
  • FIG. 2 is a schematic diagram of the low-k chip packaging structure disclosed in embodiment 1 of the present invention;
  • FIG. 3 is a schematic diagram of the low-k chip packaging structure disclosed in embodiment 2 of the present invention;
  • FIG. 4 is a schematic diagram of the low-k chip packaging structure disclosed in embodiment 3 of the present invention.
    •  AMONG THE FIGURES
    • 1-1: chip body
    • 1-2: chip electrode
    • 1-3 surface passivation layer
    • 1-4: metal layer under bumps
    • 1-5: solder bump
    • 1-6: substrate
    • 1-7: bonding pad on substrate I
    • 1-8: underfill
    • 1-9: bonding pad on substrate II
    • 1-10: BGA bump
    • 2-1: chip body I
    • 2-2: chip electrode
    • 2-3: chip surface passivation layer
    • 2-4: film layer I
    • 2-5: supporting wafer
    • 2-6: metal redistribution wire
    • 2-7: metal post
    • 2-8: film layer II
    • 2-9: metal layer
    • 2-10: solder bump
    • 2-11: chip body II
    • 2-12: dielectric layer
    • 2-6-1: metal wiring layer I
    • 2-6-2: metal wiring layer II
    DETAILED DESCRIPTION OF THE EMBODIMENTS
  • As shown in FIGS. 2, the present invention provides a low-k chip packaging structure, comprising chip body I 2-1, chip electrodes 2-2, and chip surface passivation layer 2-3, wherein, the chip body I 2-1 is wrapped with a film layer I 2-4, the back of the film layer I 2-4 is bonded with a supporting wafer 2-5, the chip electrodes 2-2 are led to the film layer I 2-4 in the peripheral area. around the chip via the metal redistribution wires 2-6, metal posts 2-7 are arranged at the terminals of the metal redistribution wires 2-6, and the metal posts 2-7 are wrapped with a film layer II 2-8, with the top of the metal posts 2-7 exposed out of the film layer II 2-8; a metal layer 2-9, with a solder bump 2-10 on it, is arranged on the exposed top of the metal posts 2-7.
  • As shown in FIG. 3, a chip body II 2-11 is embedded in the film layer I 2-4.
  • As shown in FIG. 4, the metal redistribution wires 2-6 are formed by metal wiring layer I 2-6-1 and metal wiring layer II 2-6-2.
  • The implementation procedures of the low-k chip packaging structure provided in the present invention are as follows;
  • Step 1: taking a low-k wafer and cutting it into individual chips.
  • Step 2: funning aligning marks by photo-lithography on a bearer wafer to complete the pattern layout on the bearer wafer;
  • The bearer wafer can be a silicon substrate or a glass substrate. Aligning marks are formed on the bearer wafer to facilitate the follow-up flip-chip mounting process and keep the chips at ideal positions.
  • Step 3: attaching a temporary strippable film to the bearer wafer and flip-chip mounting the chips obtained in step 1 one by one to the bearer wafer attached with the temporary strippable film.
  • The temporary strippable film is adhesive on both sides, and can bond well with both the bearer wafer and the subsequently flip-chip mounted chips. The strippable film is thermally strippable or UV strippable. If the strippable film is UV strippable, a bearer wafer should be glass substrate or quartz substrate since LW irradiation is required for UV stripping. Accordingly, the substrate must be transparent for UV transmission,
  • Flip-chip mounting is selected for two purposes: one is to ensure chips different in thickness can be mounted with the face side in the same plane in the subsequent process, the other is to prevent glue coverage on the face side of the chips on the restructured wafer; so as to facilitate subsequent processing.
  • step 4: attaching a film layer I 2-4 to the bearer wafer for encapsulation after flip-chip mounting of the chips, bonding a supporting wafer 2-5 to the film, layer I 2-4 in the encapsulation process, and curing the film layer I 2-4, then forming a restructured wafer composed of the chips, film layer I 2-4 and supporting wafer 2-5.
  • The supporting wafer 2-5 is a silicon wafer or a metal wafer, and the wafer surface is kept smooth in the encapsulation process because the film layer I 2-4 has good fluidity under heating.
  • Step 5: shipping the restructured wafer from the bearer wafer by UV irradiation or thermal stripping and cleaning the surface of the chips on the restructured wafer to expose the chip electrodes 2-2.
  • Step 6: forming single-layer or multi-layer metal redistribution wires 2-6 on the surface of the film layer I 2-4 and the chips by wafer-level photo-lithography, sputtering, or electroplating, so as to lead the chip electrodes 2-2 to the peripheral area of the chips (the area without chip) via metal redistribution wires 2-6.
  • Step 7: forming metal posts 2-7 at the terminals of metal redistribution wires 2-6 by photo-lithography or electroplating,
  • The metal posts 2-7 are made of an electrical-conductive metal material such as copper or nickel, etc.; the height of the metal posts 2-7 can be adjusted according to the requirements of the structure and shall not be smaller than 50 μm, generally, the height of the metal posts 2-7 is within the range of 50 μm-100 μm. Here, the metal posts 2-7 have two functions: one function is to reduce crowding effect of electric current, i.e., with the metal posts, the electric current can be distributed uniformly and thereby the phenomenon of electric. migration can be reduced: the other .function is to utilize the height of the metal posts 2-7 to buffer the stress from the bumps 2-10 and thereby protect the low-k chips.
  • Step 8: attaching as film layer II 2-8 to the surface of the restructured wafer with the metal posts 2-7 for encapsulation curing the package, and then removing the film material on the top of the metal posts by laser ablation, to form complete Or partial openings on the metal posts 2-7 and expose the top of the metal posts 2-7 out of the film layer II 2-8.
  • The film layer I 2-4 and film layer II 2-8 are made of non-photo-sensitive insulating resin materials.
  • Step 9: coating a metal layer 2-9 on the top of the metal posts 2-7 exposed out of the film layer II 2-8.
  • The metal layer 2-9 adopts single layer metal or multilayer metal. The multilayer metal usually has a Ni/Au or Ni/Pd/Au structure. The thickness of the metal layer 2-9 should not be greater than 5 μm. The metal layer 2-9 is used to prevent inter-diffusion between stannum and copper in the soldering flux and improve product reliability.
  • Step 10: forming BGA solder bumps 2-10 on the metal layer 2-9 by printing or bumping and finally cutting the restructured wafer with BGA solder bumps into individual BGA packages.

Claims (14)

1. A low-k chip packaging structure, comprising a chip body I (2-1), chip electrodes (2-2) and a chip surface passivation layer (2-3), wherein, the chip body (2-1) is wrapped with a film layer I (2-4), the back of the film layer I (2-4) is bonded with a supporting wafer (2-5), the chip electrodes (2-2) are led to the film layer I (2-4) in the peripheral area around the chip via metal redistribution wires (2-6), metal posts (2-7) are arranged at the terminals of the metal redistribution wires (2-6), and the metal posts (2-7) are wrapped with a film layer II (2-8), with the top of the metal posts (2-7) exposed out of the film layer II (2-8); a metal layer (2-9), with a solder bump (2-10) on it, is arranged on the exposed top of the metal posts (2-7).
2. The low-k chip packaging structure according to claim 1, wherein, the metal posts (2-7) are made of electrical-conductive metal materials such as Cu or Cu/Ni, etc., and the height of the metal posts(2-7) is within the range of 50 μm-100 μm.
3. The low-k chip packaging structure according to claim 1, wherein, the metal layer (2-9) adopts multilayer metal, has a Ni/Au or Ni/Pd/Au structure, and the thickness of the metal layer (2-9) is not greater than 5 μm.
4. The low-k chip packaging structure according to claim 1, wherein, a chip body II (2-1 1) is embedded in the film layer I (2-4).
5. The low-k chip packaging structure according to claim 1, wherein, the metal redistribution wires (2-6) are formed by metal wiring layer I (2-6-1) and metal wiring layer II (2-6-2).
6. The low-k chip packaging structure according to claim 1, wherein, both the film layer I (2-4) and the film layer II (2-8) are made of non-photo-sensitive materials.
7. The low-k chip packaging structure according to claim 1, wherein, the supporting wafer (2-5) is a silicon wafer or a metal wafer.
8. The low-k chip packaging structure according to claim 1, wherein, the bearer wafer adopts a silicon substrate or a glass substrate.
9. The low-k chip packaging structure according to claim 2, wherein, the metal layer (2-9) adopts multilayer metal, has a Ni/Au or Ni/Pd/Au structure, and the thickness of the metal layer (2-9) is not greater than 5 μm.
10. The low-k chip packaging structure according to claim 2, wherein, a chip body II (2-11) is embedded in the film layer I (2-4).
11. The low-k chip packaging structure according to claim 2, wherein, the metal redistribution wires (2-6) are formed by metal Wiring layer I (2-6-1) and metal wiring layer II (2-6-2).
12. The low-k chip packaging structure according to claim 2, wherein, both the film Layer II (2-4) and the film layer II (2-8) are made of non-photo-sensitive materials.
13. The low-k chip packaging structure according to claim 2, wherein, the supporting wafer (2-5) is a silicon wafer or a metal wafer.
14. The low-k chip packaging structure according to claim 2, wherein, the bearer wafer adopts a silicon substrate or a glass substrate.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180068978A1 (en) * 2016-09-02 2018-03-08 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and method of manufacturing the same
US10707168B2 (en) * 2017-12-22 2020-07-07 Intel Corporation Embedded multi-die interconnect bridge packages with lithographically formed bumps and methods of assembling same

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9111772B1 (en) * 2014-01-29 2015-08-18 Infineon Technologies Ag Electronic array and chip package
US9269887B1 (en) * 2015-01-06 2016-02-23 Triquint Semiconductor, Inc. Ultrathin flip-chip packaging techniques and configurations
CN104992936A (en) * 2015-05-19 2015-10-21 南通富士通微电子股份有限公司 Wafer level chip packaging structure
CN112435971B (en) * 2020-10-09 2024-06-18 上海天马微电子有限公司 Chip packaging structure and packaging method
CN114242868A (en) * 2021-11-26 2022-03-25 惠州雷曼光电科技有限公司 Application of nickel-palladium plate in COB packaging process

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5870289A (en) * 1994-12-15 1999-02-09 Hitachi, Ltd. Chip connection structure having diret through-hole connections through adhesive film and wiring substrate
US5976912A (en) * 1994-03-18 1999-11-02 Hitachi Chemical Company, Ltd. Fabrication process of semiconductor package and semiconductor package
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3891838B2 (en) * 2001-12-26 2007-03-14 株式会社ルネサステクノロジ Semiconductor device and manufacturing method thereof
TW577160B (en) * 2002-02-04 2004-02-21 Casio Computer Co Ltd Semiconductor device and manufacturing method thereof
AU2003253425C1 (en) * 2002-08-09 2006-06-15 Casio Computer Co., Ltd. Semiconductor device and method of manufacturing the same
US20050012225A1 (en) * 2002-11-15 2005-01-20 Choi Seung-Yong Wafer-level chip scale package and method for fabricating and using the same
TWI256095B (en) 2004-03-11 2006-06-01 Siliconware Precision Industries Co Ltd Wafer level semiconductor package with build-up layer and process for fabricating the same
TWI294694B (en) * 2005-06-14 2008-03-11 Ind Tech Res Inst Led wafer-level chip scale packaging
KR100987688B1 (en) * 2005-10-14 2010-10-13 가부시키가이샤후지쿠라 Printed wiring board and method for manufacturing printed wiring board
US20070196979A1 (en) * 2006-02-21 2007-08-23 Advanpack Solutions Pte Ltd Flip chip in package using flexible and removable leadframe
JP4559993B2 (en) * 2006-03-29 2010-10-13 株式会社東芝 Manufacturing method of semiconductor device
US20080122119A1 (en) * 2006-08-31 2008-05-29 Avery Dennison Corporation Method and apparatus for creating rfid devices using masking techniques
JP4950693B2 (en) * 2007-02-19 2012-06-13 株式会社フジクラ Electronic component built-in wiring board and its mounting parts
KR20080102641A (en) 2007-05-21 2008-11-26 삼성전자주식회사 Semiconductor package including a heat spreader
KR20090032225A (en) 2007-09-27 2009-04-01 주식회사 하이닉스반도체 Wafer level chip scale package and method of fabricating the same
US20090311849A1 (en) * 2008-06-17 2009-12-17 International Business Machines Corporation Methods of separating integrated circuit chips fabricated on a wafer
CN101419952B (en) * 2008-12-03 2010-09-15 晶方半导体科技（苏州）有限公司 Wafer stage chip encapsulation method and encapsulation construction
CN101630666A (en) * 2009-05-11 2010-01-20 江阴长电先进封装有限公司 Island rewiring chip encapsulation structure
CN101661917B (en) * 2009-05-11 2011-06-22 江阴长电先进封装有限公司 Chip packaging structure of resin core column
CN101604674B (en) 2009-06-26 2010-12-29 江阴长电先进封装有限公司 Wafer level fan-out chip packaging structure
CN102122624B (en) 2011-02-01 2013-02-13 南通富士通微电子股份有限公司 Wafer packaging method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5976912A (en) * 1994-03-18 1999-11-02 Hitachi Chemical Company, Ltd. Fabrication process of semiconductor package and semiconductor package
US5870289A (en) * 1994-12-15 1999-02-09 Hitachi, Ltd. Chip connection structure having diret through-hole connections through adhesive film and wiring substrate
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180068978A1 (en) * 2016-09-02 2018-03-08 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and method of manufacturing the same
CN107799499A (en) * 2016-09-02 2018-03-13 台湾积体电路制造股份有限公司 Semiconductor package and its manufacture method
US10535632B2 (en) * 2016-09-02 2020-01-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and method of manufacturing the same
US10707168B2 (en) * 2017-12-22 2020-07-07 Intel Corporation Embedded multi-die interconnect bridge packages with lithographically formed bumps and methods of assembling same
US11043457B2 (en) 2017-12-22 2021-06-22 Intel Corporation Embedded multi-die interconnect bridge packages with lithotgraphically formed bumps and methods of assembling same
US11764158B2 (en) 2017-12-22 2023-09-19 Intel Corporation Embedded multi-die interconnect bridge packages with lithographically formed bumps and methods of assembling same

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