CN101630666A - Island rewiring chip encapsulation structure - Google Patents
Island rewiring chip encapsulation structure Download PDFInfo
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- CN101630666A CN101630666A CN 200910027452 CN200910027452A CN101630666A CN 101630666 A CN101630666 A CN 101630666A CN 200910027452 CN200910027452 CN 200910027452 CN 200910027452 A CN200910027452 A CN 200910027452A CN 101630666 A CN101630666 A CN 101630666A
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- wiring metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
The invention relates to an island rewiring chip encapsulation structure, belonging to the technical field of chip encapsulation. The island rewiring chip encapsulation structure comprises a chip body (101), a chip electrode (102), a chip surface passivation layer (103), an island stress cushion layer (104), a rewiring metal layer (105), a rewiring metal surface protection layer (106) and a stress cushion layer upper solder salient point (107); the chip electrode (102) is arranged on the chip body (101), the chip surface passivation layer (103) is compounded on the surface of the chip body (101), the periphery and the outer edge of the surface of the chip electrode (102), the island stress cushion layer (104) is arranged on the chip surface passivation layer (103), the rewiring metal surface protection layer (106) is covered on the surface of the rewiring metal layer (105), and the stress cushion layer upper solder salient point (107) is arranged on the surface of a salient point lower metal layer (105A). The chip encapsulation structure of the invention can reduce chip stress and leakage current risk in the wafer machining process and improves the reliability of the chip in usage.
Description
(1) technical field
The present invention relates to a kind of island rewiring chip encapsulation structure.Belong to the chip encapsulation technology field.
(2) background technology
Traditionally, IC chip and outside being electrically connected are in the mode of bonding the I/O on the chip to be connected to package carrier and to realize through packaging pin with metal lead wire.Along with the expansion with integrated scale dwindled of IC chip features size, the spacing of I/O constantly reduces, quantity is on the increase.When the I/O spacing narrows down to 70um when following, Wire Bonding Technology is just no longer suitable, must seek new technological approaches.Wafer-Level Packaging Technology is utilized the film technology that distributes again, I/O can be distributed on the whole surface of IC chip and no longer only be confined to the neighboring area of narrow IC chip, thereby solved the problem that is electrically connected of high density, thin space I/O chip.
Wafer level packaging is a kind of CSP through improving and improving based on the BGA technology, has demonstrated fully the technical advantage of BGA, CSP.It has the advantage of many uniquenesses: 1. encapsulation process efficient height, and it is made with the mass production processes of disk form; 2. the advantage that has Flip-Chip Using is promptly light, thin, short, little; 3. wafer level packaging production facility expense is low, can make full use of the manufacturing equipment of disk, need not invest and build packing producing line in addition; 4. the chip design of wafer level packaging and package design can be unified to consider, carry out simultaneously that this will improve design efficiency, reduce design cost; 5. wafer level packaging from chip manufacturing, be encapsulated into the whole process that product mails to the user, intermediate link significantly reduces, the cycle shortens a lot, this will cause the reduction of cost; 6. the number of chips on the cost of wafer level packaging and each disk is closely related, and the chip-count on the disk is many more, and the cost of wafer level packaging is also low more.Wafer level packaging is the low-cost package of size minimum.
Film distribution circle sheet level chip scale package again is one of wafer level packaging technology.Because its cost is lower, simultaneously in the advantage that satisfies aspect the requiring of portable product plate level reliability standard, its range of application is more and more wider.
Current most typical film Wiring technique again is, adopt PI or BCB as the dielectric layer that distributes again, Cu or Ni adopt sputtering method deposit salient point bottom metal layers (UBM) as the line metal that distributes again, with planting ball or silk screen print method deposit soldering paste and refluxing, form solder bumps.
In the Wiring technique, mainly contain two kinds of big structures at present again, a kind of is that the wiring metal layer had both been done the usefulness that connects up again again, uses as the salient point bottom metal layers again simultaneously; A kind of structure is again that wiring metal is only done the usefulness that connects up again, and the salient point bottom metal layers is made again.The characteristics of these present two kinds of technologies all are to finish the covering of film on the entire chip surface, cause two problems that allow industry puzzle: the one, disk surfaces stress, along with increasing of chip functions, chip size is also in continuous increase, chip surface stress increases the weight of for chip reliability effect in use, and the covering fully of thin film dielectrics layer, the stress that acts on chip surface can't discharge, and has reduced chip reliability in use; On the other hand, in wafer level packaging technology, the enterprising row metal cabling of thin film dielectrics is easy to generate leakage current, particularly under the situation of thin space cabling.
(3) summary of the invention
The objective of the invention is to overcome above-mentioned deficiency, a kind of leakage current risk that can reduce the die stress and the disk course of processing greatly is provided, improve the island rewiring chip encapsulation structure of chip unfailing performance in use.
The object of the present invention is achieved like this: a kind of island rewiring chip encapsulation structure; it is characterized in that described chip-packaging structure comprises the chip body; chip electrode; the chip surface passivation layer; the isolated island stress-buffer layer; wiring metal layer again; solder bump on wiring metal sealer and the stress-buffer layer again; described chip electrode is arranged on the chip body; the chip surface passivation layer is compounded in chip body surface and chip electrode outer rim and surperficial neighboring; and the mid portion exposed chip surface passivation layer on chip electrode surface; described isolated island stress-buffer layer is arranged on the chip surface passivation layer; the described layer of wiring metal again covers the chip surface passivation layer surface; the chip electrode surface mid portion of exposed chip surface passivation layer and the surface of isolated island stress-buffer layer; the described sealer of wiring metal again covers the surface of wiring metal layer again; and the ubm layer that exposes isolated island stress-buffer layer over top mid portion, solder bumps is protruded and is arranged on described ubm layer surface on the described stress-buffer layer.
Beneficial effect of the present invention is:
By Wiring technique again, can realize the flexible design of chip electrode position and bump structure position, the existing transfer wiring of wiring metal function again has the function of metal under the salient point again, with soldered ball wetting formation takes place and reliably is connected.Pass through the design of isolated island stress-buffer layer simultaneously; greatly reduce die stress and the leakage current risk that has reduced the disk course of processing; improve the unfailing performance of bump structure, the wiring metal sealer has reduced the influence that chip circuit is avoided environment for use to the covering of wiring route more again.Wherein, the wiring metal layer is to the three kinds of situations that are coated with of isolated island stress-buffer layer again: cover (as Fig. 2) fully, a side sidewall does not cover fully, remainder covers (except the cabling, as Fig. 3) fully and a side sidewall sections covers, remainder covers (except the cabling, as Fig. 4) fully.These three kinds of structures can satisfy that different processing technology requires and to the demand of chip performance, have and highly select flexibility.Simultaneously, the wiring metal sealer can pass through thickness adjusted again.
(4) description of drawings
Fig. 1 is the vertical view of island rewiring chip encapsulation structure of the present invention.
Fig. 2 is the a-a cut-away view one of Fig. 1.
Fig. 3 is the a-a cut-away view two of Fig. 1.
Fig. 4 is the a-a cut-away view three of Fig. 1.
Among the figure: chip body 101, chip electrode 102, chip surface passivation layer 103, isolated island stress-buffer layer 104, wiring metal layer 105A, solder bumps 107 on wiring metal sealer 106, the stress-buffer layer more again under wiring metal layer 105, the salient point again.
(5) embodiment
Island rewiring chip encapsulation structure of the present invention, by chip body 101, chip electrode 102, chip surface passivation layer 103, isolated island stress-buffer layer 104, again wiring metal layer 105, solder bump 107 is formed on wiring metal sealer 106 and the stress-buffer layer again.
Described chip electrode 102 is arranged on the chip body 101; chip surface passivation layer 103 is compounded in chip body 101 surfaces and chip electrode 102 outer rims and surperficial neighboring; and the mid portion exposed chip surface passivation layer 103 on chip electrode 102 surfaces; isolated island stress-buffer layer 104 is arranged on the chip surface passivation layer 103; wiring metal layer 105 covers chip surface passivation layer 103 again; the chip electrode 102 surperficial mid portions of exposed chip surface passivation layer 103 and the surface of isolated island stress-buffer layer 104; the described sealer of wiring metal again 106 covers the surface of wiring metal layer 105 again; the ubm layer 105A that exposes isolated island stress-buffer layer 104 over top mid portions, solder bumps 107 is protruded and is arranged on described ubm layer 105A surface on the stress-buffer layer.
Its implementation procedure is:
1) utilizes the mode of photoetching or printing, on chip surface passivation layer 103, finish isolated island stress-buffer layer 104.
2) comprise the mode of chemical plating by sputter or plating,, finish the layer of wiring metal again 105 by chip electrode 102 105A position under the salient point in conjunction with the mask technology.
3) to wiring metal layer 105 usefulness more again wiring metal sealer 106 carry out surface coverage or comprise covering to chip surface is whole, expose the ubm layer 105A of isolated island stress-buffer layer 104 over top mid portions.
4) plant ball or printing soldering paste at described ubm layer 105A place, and solder bumps 107 on the formation stress-buffer layer that refluxes.
Described isolated island stress-buffer layer 104 is an insulating polymeric material, as polyimides, epoxy resin etc.
The described layer of wiring metal again 105 is the single or multiple lift metal material.
Described isolated island stress-buffer layer 104 is all covered by wiring metal layer 105 again.
Described isolated island stress-buffer layer 104 1 side sidewalls are not covered by wiring metal layer 105 again, and remainder is all covered by wiring metal layer 105 again.
Described isolated island stress-buffer layer 104 1 side sidewall sections are not covered by wiring metal layer 105 again, and remainder is all covered by wiring metal layer 105 again.
Claims (7)
1; a kind of island rewiring chip encapsulation structure; it is characterized in that described chip-packaging structure comprises chip body (101); chip electrode (102); chip surface passivation layer (103); isolated island stress-buffer layer (104); wiring metal layer (105) again; solder bump (107) on wiring metal sealer (106) and the stress-buffer layer again; described chip electrode (102) is arranged on the chip body (101); chip surface passivation layer (103) is compounded in chip body (101) surface and chip electrode (102) outer rim and surperficial neighboring; and the mid portion exposed chip surface passivation layer (103) on chip electrode (102) surface; described isolated island stress-buffer layer (104) is arranged on the chip surface passivation layer (103); the described layer of wiring metal again (105) covers chip surface passivation layer (103) surface; the surperficial mid portion of chip electrode (102) of exposed chip surface passivation layer (103) and the surface of isolated island stress-buffer layer (104); the described sealer of wiring metal again (106) covers the surface of wiring metal layer (105) again; and the ubm layer (105A) that exposes isolated island stress-buffer layer (104) over top mid portion, solder bumps on the described stress-buffer layer (107) protrude and are arranged on described ubm layer (105A) surface.
2, a kind of island rewiring chip encapsulation structure according to claim 1 is characterized in that described isolated island stress-buffer layer (104) is all covered by wiring metal layer (105) again.
3, a kind of island rewiring chip encapsulation structure according to claim 1 is characterized in that described isolated island stress-buffer layer (104) one side sidewalls are not covered by wiring metal layer (105) again, and all the other are all covered by wiring metal layer (105) again.
4, according to claim 1,2 or 3 described a kind of low stresses that are applied in the wafer level packaging chip-packaging structure that connects up again, it is characterized in that described isolated island stress-buffer layer (104) one side sidewall sections are not covered by wiring metal layer (105) again, all the other are all covered by wiring metal layer (105) again.
5,, it is characterized in that described isolated island stress-buffer layer (104) is an insulating polymeric material according to claim 1,2 or 3 described a kind of island rewiring chip encapsulation structures.
6, a kind of island rewiring chip encapsulation structure according to claim 5 is characterized in that described insulating polymeric material is polyimides or epoxy resin.
7,, it is characterized in that the described layer of wiring metal again (105) is the single or multiple lift metal material according to claim 1,2 or 3 described a kind of island rewiring chip encapsulation structures.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910027452 CN101630666A (en) | 2009-05-11 | 2009-05-11 | Island rewiring chip encapsulation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910027452 CN101630666A (en) | 2009-05-11 | 2009-05-11 | Island rewiring chip encapsulation structure |
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| CN101630666A true CN101630666A (en) | 2010-01-20 |
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| CN 200910027452 Pending CN101630666A (en) | 2009-05-11 | 2009-05-11 | Island rewiring chip encapsulation structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102244061A (en) * | 2011-07-18 | 2011-11-16 | 江阴长电先进封装有限公司 | Low-k chip package structure |
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2009
- 2009-05-11 CN CN 200910027452 patent/CN101630666A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102244061A (en) * | 2011-07-18 | 2011-11-16 | 江阴长电先进封装有限公司 | Low-k chip package structure |
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