TW201813016A - 半導體封裝結構及其製造方法 - Google Patents

半導體封裝結構及其製造方法 Download PDF

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TW201813016A
TW201813016A TW106114718A TW106114718A TW201813016A TW 201813016 A TW201813016 A TW 201813016A TW 106114718 A TW106114718 A TW 106114718A TW 106114718 A TW106114718 A TW 106114718A TW 201813016 A TW201813016 A TW 201813016A
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Taiwan
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wafer
redistribution layer
layer
chip
electrically connected
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TW106114718A
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TWI719202B (zh
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鄭心圃
許峰誠
陳碩懋
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台灣積體電路製造股份有限公司
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract

本揭露實施例揭露一種半導體封裝結構，其包含一重佈層(RDL)、一第一晶片、至少一第二晶片、一囊封物及一第三晶片。該重佈層具有彼此對置之一第一表面及一第二表面。該第一晶片位於該重佈層之該第一表面上方且電連接至該重佈層。該第二晶片位於該重佈層之該第一表面上方。該第二晶片包含複數個貫穿通路結構。該囊封物位於該重佈層之該第一表面上方，其中該囊封物包圍該第一晶片及該第二晶片。該第三晶片位於該囊封物上方且透過該第二晶片之該等貫穿通路結構及該重佈層電連接至該第一晶片。

Description

半導體封裝結構及其製造方法
本揭露實施例係有關半導體封裝結構及其製造方法。
為試圖進一步增大電路密度且減少成本，已開發三維(3D)半導體封裝結構。隨著半導體技術的演進，半導體裝置變得越來越小，同時需要將更多功能整合至半導體裝置中。相應地，半導體裝置需要使越來越多輸入/輸出(I/O)端子封裝至較小面積中，且I/O端子之密度隨時間快速上升。因此，半導體裝置之封裝變得更困難，其不利地影響封裝之良率。
根據本揭露一實施例，一種半導體封裝結構包括：一重佈層，其具有彼此對置之一第一表面及一第二表面；一第一晶片，其位於該重佈層之該第一表面上方且電連接至該重佈層；一第二晶片，其位於該重佈層之該第一表面上方，其中該第二晶片包含複數個貫穿通路結構；一囊封物，其位於該重佈層之該第一表面上方，其中該囊封物包圍該第一晶片及該第二晶片；及一第三晶片，其位於該囊封物上方且透過該第二晶片之該等貫穿通路結構及該重佈層電連接至該第一晶片。 根據本揭露一實施例，一種半導體封裝結構包括：一第一重佈層，其具有彼此對置之一第一表面及一第二表面；一第一晶片，其位於該第一重佈層之該第一表面上方；一第二晶片，其位於該第一重佈層之該第一表面上方，其中該第二晶片包含複數個貫穿通路結構，且該貫穿通路結構之一第一端子耦合至該第一重佈層；一第一囊封物，其位於該第一重佈層之該第一表面上方，其中該第一囊封物包圍該第一晶片及該第二晶片；一第二重佈層，其位於該第一囊封物上方且電連接至該貫穿通路結構之一第二端子，其中該第二重佈層具有彼此對置之一第三表面及一第四表面，且該第三表面面向該第一表面；一第三晶片，其位於該第二重佈層之該第四表面上方且電連接至該第二重佈層；及一第二囊封物，其位於該第二重佈層上方。 根據本揭露一實施例，一種用於製造一半導體封裝結構之方法包括：形成一第一重佈層；將一第一晶片安置於該第一重佈層上方；將一第二晶片安置於該第一重佈層上方，其中該第二晶片包含複數個貫穿通路結構；使一囊封物形成於該第一重佈層上方；及將一第三晶片安置於該囊封物上方，其中該第三晶片及該第一重佈層透過該第二晶片之該等貫穿通路結構電連接。
本申請案主張2016年9月2日申請之美國臨時申請案第62/382,912號之優先權，該案之全文以引用的方式併入。 以下揭露提供用於實施所提供之標的之不同特徵之諸多不同實施例或實例。下文將描述元件及配置之特定實例以簡化本揭露。當然，此等僅為實例且不意在限制。例如，在以下描述中，「使一第一構件形成於一第二構件上方或一第二構件上」可包含其中形成直接接觸之該第一構件及該第二構件的實施例，且亦可包含其中可形成介於該第一構件與該第二構件之間之額外構件使得該第一構件及該第二構件可不直接接觸的實施例。另外，本揭露可在各種實例中重複元件符號及/或字母。此重複係為了簡化及清楚且其本身不指示所討論之各種實施例及/或組態之間之一關係。 此外，為便於描述，諸如「下面」、「下方」、「下」、「上方」、「上面」、「上」及其類似者之空間相對術語可在本文中用於描述一元件或構件與另外(若干)元件或(若干)構件之關係，如圖中所繪示。空間相對術語除涵蓋圖中所描繪之定向之外，亦意欲涵蓋裝置在使用或操作中之不同定向。設備可依其他方式定向(旋轉90度或依其他定向)且亦可相應地解譯本文所使用之空間相對描述詞。 如本文所使用，諸如「第一」、「第二」及「第三」之術語描述各種元件、組件、區域、層及/或區段，此等元件、組件、區域、層及/或區段應不受限於此等術語。此等術語可僅用於區分一元件、組件、區域、層或區段與另一元件、組件、區域、層或區段。除非內文明確指示，否則本文所使用之諸如「第一」、「第二」及「第三」之術語不隱含一序列或順序。 如本文所使用，術語「近似」、「實質上」、「實質」及「約」用於描述及解釋小變動。當該等術語與一事件或狀況一起使用時，該等術語可涉及其中該事件或狀況精確發生的例項以及其中該事件或狀況非常近似發生的例項。例如，當該等術語與一數值一起使用時，該等術語可涉及小於或等於該數值之±10%的一變動範圍，諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%、或小於或等於±0.05%。例如，若兩個數值之間之一差值小於或等於該等值之一平均值之±10% (諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%、或小於或等於±0.05%)，則該等值可被視為「實質上」相同或相等。例如，「實質上」平行可涉及小於或等於±10°之相對於0°之一角變動範圍，諸如小於或等於±5°、小於或等於±4°、小於或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°、或小於或等於±0.05°。例如，「實質上」垂直可涉及小於或等於±10°之相對於90°之一角變動範圍，諸如小於或等於±5°、小於或等於±4°、小於或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°、或小於或等於±0.05°。 如本文所使用，術語「載體基板」或「暫時基板」係指經組態為一中間基板以用於上覆層(諸如重佈層、晶片、囊封物及其他結構)之製造設施或用於切割的一載體。載體基板或暫時基板提供暫時支撐及固定功能，且會自上覆結構移除。 如本文所使用，術語「重佈層(RDL)」係指由至少一導電圖案及至少一絕緣層形成且經組態以與兩個或兩個以上裝置電通信之一層堆疊。 如本文所使用，術語「導電凸塊」係指經組態以透過其兩端使兩個導電結構電互連之一導體。在一或多個實施例中，導電凸塊由可藉由低溫操作而形成之一低熔點材料形成。導電凸塊形成於形成包圍互連凸塊之側壁的囊封物之前。在一或多個實施例中，導電凸塊係一焊料凸塊、一焊料膏或其類似者。 如本文所使用，術語「導電柱」係指藉由可實施精細節距之沈積、光微影及蝕刻操作而形成之一導體。 如本文所使用，術語「中介層」係一互連結構，其經組態以將安置於該互連結構之兩個對置表面上之兩個或兩個以上電子裝置(諸如晶片、重佈層或封裝)電連接。在一或多個實施例中，中介層係一預成形互連結構，其可安置於待互連至另一電子裝置的電子裝置之一者上。在一或多個實施例中，中介層包含具有精細節距之若干貫穿通路結構，諸如貫穿矽通路(TSV)。 如本文所使用，術語「貫穿絕緣體通路(TIV)」係貫穿一絕緣體且經組態以透過其兩端將兩個導電結構電連接之一導體。 在本揭露之一或多個實施例中，半導體封裝結構包含位於一囊封物中且介於兩個電子裝置之間之晶片，且電子裝置之各者獨立地包含一重佈層、一半導體晶粒或一封裝。在一或多個實施例中，晶片之一部分包含經組態以提供兩個電子裝置之間之高密度互連的貫穿通路結構(諸如TSV)，而晶片之另一部分無需貫穿通路結構來電連接至電子裝置之一者。具有貫穿通路結構之晶片提供用於兩個電子裝置之間之互連之一短信號路徑。在一些實施例中，具有貫穿通路結構之晶片係不具有整合於其內之主動裝置的一中介層。在一些實施例中，具有貫穿通路結構之晶片係包含整合於其內之TSV的一主動裝置晶片。在一或多個實施例中，貫穿絕緣體通路(TIV)可配置於囊封物中以提供兩個電子裝置之間之一額外信號路徑來提高選路靈活性。在一或多個實施例中，半導體封裝結構係一扇出晶圓級封裝(FOWLP)。 圖1係繪示根據本揭露之各種態樣之用於製造一半導體封裝結構之一方法的一流程圖。方法100開始於其中形成一第一重佈層的操作110。方法100繼續至其中將一第一晶片安置於該第一重佈層上方的操作120。方法100前進至其中將一第二晶片安置於該第一重佈層上方的操作130，其中該第二晶片包含複數個貫穿通路結構。方法100前進至其中使一囊封物形成於該第一重佈層上方的操作140。方法100前進至其中將一第三晶片安置於該囊封物上方的操作150，其中該第三晶片及該第一重佈層透過該第二晶片之該等貫穿通路結構電連接。 方法100僅為一實例，且不意欲限制本揭露超出申請專利範圍中明確敘述之內容的範圍。可在方法100之前、在方法100期間及在方法100之後提供額外操作，且可針對方法之額外實施例替換、消除或移動所描述之一些操作。 圖2A、圖2B、圖2C、圖2D、圖2E、圖2F、圖2G、圖2H、圖2I、圖2J及圖2K係根據本揭露之一或多個實施例之製造半導體封裝結構之各種操作之一者中的橫截面圖。如圖2A中所描繪，一第一重佈層20形成於一載體基板10上方。在一或多個實施例中，載體基板10經組態為用於形成一重佈層(諸如一第一重佈層20)之一暫時基板，且隨後會被移除。在一或多個實施例中，載體基板10係諸如一玻璃基板之一絕緣基板。載體基板10可包含一半導體基板(諸如一矽基板)、一導電基板(諸如一金屬基板)或其他適合基板。 第一重佈層20具有彼此對置之一第一表面201及一第二表面202。在一些實施例中，第一重佈層20之第二表面202面向載體基板10。第一重佈層20由至少一導電層22及至少一絕緣層24形成，且經組態以與兩個或兩個以上晶片電通信。在一或多個實施例中，第一重佈層20包含彼此堆疊之若干導電層22及若干絕緣層24。在一些實施例中，(若干)導電層22之材料可包含(但不限於)金屬，諸如銅、鈦、其類似者或其等之一組合。(若干)絕緣層24之材料可包含(但不限於)無機及/或有機絕緣材料。 在一或多個實施例中，導電層22包含不同圖案且彼此電連接。在一或多個實施例中，一最上導電層22之一部分自第一重佈層20之第一表面201暴露。在一或多個實施例中，若干接合墊26 (諸如凸塊下金屬(UBM))形成於第一重佈層20之最上導電層22之暴露部分上方且電連接至第一重佈層20之最上導電層22之暴露部分。 如圖2B中所描繪，一或多個第一晶片30安置於第一重佈層20之第一表面201上方。在一或多個實施例中，第一晶片30電連接至第一重佈層20。在一或多個實施例中，第一晶片30包含主動裝置晶片及/或被動裝置晶片。舉例而言，主動裝置晶片可包含系統單晶片(SOC)及/或其他晶片。被動裝置晶片可包含形成於其內之電阻器、電容器、電感器或其等之一組合。在一些實施例中，被動裝置晶片可呈(但不限於)積體電路之形式。第一晶片30可透過表面黏著技術(SMT)或其他適合接合技術安裝於第一重佈層20上。在一些實施例中，第一晶片30包含若干電端子30P，且第一晶片30藉由透過導電材料32 (諸如導電膏、導電凸塊或其他適合導電材料)將電端子30P接合至接合墊26之一部分而電連接至第一重佈層20。 一或多個第二晶片36安置於第一重佈層20上方且電連接至第一重佈層20。在一或多個實施例中，第二晶片36包含諸如貫穿通路結構36C之若干互連件。舉例而言，貫穿通路結構36C係貫穿矽通路(TSV)。第二晶片36經組態以使安置於兩個對置側上之第一重佈層20及另一裝置(諸如一第三晶片或一第二重佈層)互連，且可實施相鄰貫穿通路結構36C之間之精細節距。在一些實施例中，第二晶片36係形成為積體電路形式且無主動裝置整合於其內之一中介層。在一些實施例中，第二晶片36係包含整合於其內之TSV的一主動裝置晶片，諸如SOC。在一或多個實施例中，第二晶片36可進一步包含諸如金屬-絕緣體-金屬(MIM)電容器之嵌入式被動裝置。第二晶片36可透過SMT或其他適合接合技術安裝於第一重佈層20上。在一些實施例中，第二晶片36包含若干接觸墊36P，且第二晶片36藉由透過導電材料38 (諸如導電膏、導電凸塊或其他適合導電材料)將接觸墊36P接合至接合墊26之另一部分而電連接至第一重佈層20。在一或多個實施例中，第二晶片36及第一晶片30具有實質上相同高度且位於實質上相同層級處。在一或多個實施例中，貫穿通路結構36C包含兩個端子，其中貫穿通路結構36C之一第一端子C1透過(例如)接觸墊36P耦合至第一重佈層20，且貫穿通路結構36C之一第二端子C2經組態以耦合至(若干)第三晶片或待形成之第二重佈層。在一或多個實施例中，貫穿通路結構36C之第二端子C2嵌入第二晶片36中，且將在後續操作中被暴露。 如圖2C中所描繪，一囊封物(諸如一第一囊封物40)形成於第一重佈層20之第一表面201上方。在一或多個實施例中，第一囊封物40之材料係一模塑料。在一些實施例中，一底膠填充層42可形成於第一晶片30與第一重佈層20之間及形成於第二晶片36與第一重佈層20之間。在一些實施例中，第一囊封物40係一成型底膠填充(MUF)層且因此可無需一額外底膠填充層。在一或多個實施例中，第一囊封物40覆蓋第一晶片30及第二晶片36之上表面及側壁。 如圖2D中所描繪，藉由(例如)研磨而移除第一囊封物40之一部分以暴露第二晶片36之第二端子C2。在一或多個實施例中，第一囊封物40藉由研磨而薄化。 如圖2E中所描繪，一絕緣層44形成於第一囊封物40上方。在一或多個實施例中，絕緣層44之材料可包含(但不限於)諸如PBO之有機絕緣材料。絕緣層44包含暴露第二晶片36之第二端子C2的若干開口。若干接合墊46形成於絕緣層44上方且透過絕緣層44之開口電連接至第二晶片36之第二端子C2。在一或多個實施例中，接合墊46可包含(但不限於)凸塊下金屬(UBM)。 如圖2F中所描繪，一或多個第三晶片50安置於第一囊封物40上方且電連接至第二晶片36。在一或多個實施例中，第三晶片50包含一封裝或一記憶體晶片。舉例而言，第三晶片50包含彼此堆疊且電連接之若干DRAM裝置52。在一或多個實施例中，DRAM裝置52包含貫穿通路結構56且透過諸如微導電凸塊之互連件54而彼此電連接。第三晶片50可透過SMT或其他適合接合技術安裝於第二晶片36上。在一些實施例中，第三晶片50透過導電材料48 (諸如導電膏、導電凸塊或其他適合導電材料)電連接至第二晶片36之接合墊46。 如圖2G中所描繪，一第二囊封物58形成於第一囊封物40上方。在一或多個實施例中，第二囊封物58之材料係一模塑料。在一些實施例中，一底膠填充層59可形成於第三晶片50與第一囊封物40之間。在一些實施例中，第二囊封物58係一成型底膠填充(MUF)層且因此無需一額外底膠填充層。在一或多個實施例中，第二囊封物58覆蓋第三晶片50之一上表面及一側壁。在一些實施例中，第三晶片50可包含光電晶片(諸如CMOS影像感測器晶片)、MEMS晶片、記憶體晶片、高功率晶片，且第二囊封物58可(例如)藉由研磨而薄化以暴露第三晶片50之上表面。 如圖2H中所描繪，第二囊封物58附著至一暫時基板60。在一或多個實施例中，暫時基板60係一撓性膜，諸如固定於一框架62上之一膠帶。在一些實施例中，暫時基板60可包含其他類型之基板，諸如一剛性基板。接著，載體基板10自第一重佈層20之第二表面202拆離。 如圖2I中所描繪，第一重佈層20之一部分自第二表面202移除以暴露經組態為接合墊之一最下導電層22。在一或多個實施例中，第一重佈層20藉由諸如乾式蝕刻之蝕刻而移除。 如圖2J中所描繪，若干導體64形成於第一重佈層20之第二表面202上方且電連接至第一重佈層20。在一或多個實施例中，導體64包含(但不限於)導電凸塊。在一或多個實施例中，一或多個第四晶片66安置於第一重佈層20之第二表面202上方且電連接至第一重佈層20。在一或多個實施例中，第四晶片66包含被動裝置晶片。舉例而言，被動裝置晶片可包含形成於其內之電阻器、電容器、電感器或其等之一組合。在一些實施例中，被動裝置晶片可呈(但不限於)積體電路之形式。在一或多個實施例中，執行一單粒化操作以形成若干半導體封裝結構1。接著，半導體封裝結構1自暫時基板60移除，如圖2K中所展示。 在半導體封裝結構1中，第一晶片30透過面向第一重佈層20之電端子30P電連接至第一重佈層20。第三晶片50透過具有貫穿通路結構36C (其具有精細節距)之第二晶片36電連接至第一重佈層20。第二晶片36提供用於第一晶片30與第三晶片50之間之互連的一短信號路徑。第二晶片36避免在第一晶片30中形成貫穿通路結構，其有助於改良第一晶片30之良率。第二晶片36經組態以提供可與具有高I/O密度之晶片(諸如記憶體晶片)整合的數目增加I/O計數。 本揭露之半導體封裝結構不受限於上文所提及之實施例，而是可具有其他不同實施例。為簡化描述且為便於本揭露之實施例之各者之間進行比較，以下實施例之各者中之相同組件使用相同元件符號來標記。為易於比較實施例之間之差異，以下描述將詳述不同實施例之間之相異性且將不贅述相同構件。 圖3係根據本揭露之一或多個實施例之一半導體封裝結構之一橫截面圖。如圖3中所描繪，半導體封裝結構2包含安置於第一重佈層20上方且電連接至第三晶片50及第一重佈層20之兩個或兩個以上第二晶片36。 圖4A、圖4B、圖4C、圖4D、圖4E、圖4F、圖4G、圖4H、圖4I、圖4J及圖4K係根據本揭露之一或多個實施例之製造半導體封裝結構之各種操作之一者中的橫截面圖。如圖4A中所描繪，一第一重佈層20形成於一載體基板10上方。第一重佈層20具有彼此對置之一第一表面201及一第二表面202。在一些實施例中，第一重佈層20之第二表面202面向載體基板10。第一重佈層20由至少一導電層22及至少一絕緣層24形成，且經組態以與兩個或兩個以上晶片電通信。在一或多個實施例中，一最上導電層22之一部分自第一重佈層20之第一表面201暴露。在一或多個實施例中，若干接合墊26 (諸如凸塊下金屬(UBM))形成於第一重佈層20之最上導電層22之暴露部分上方且電連接至第一重佈層20之最上導電層22之暴露部分。 如圖4B中所描繪，一或多個第一晶片30安置於第一重佈層20之第一表面201上方。在一或多個實施例中，第一晶片30包含背向第一重佈層20之第一表面201的若干電端子30P。在一些實施例中，電端子30P覆蓋有一鈍化層33 (諸如一聚合層)且受鈍化層33保護。在一或多個實施例中，第一晶片30透過一黏著層31 (諸如一晶粒附著膜(DAF))接合至第一重佈層20之第一表面201。一或多個第二晶片36安置於第一重佈層20上方且電連接至第一重佈層20。 如圖4C中所描繪，一第一囊封物40形成於第一重佈層20之第一表面201上方。在一或多個實施例中，第一囊封物40之材料係一模塑料。在一些實施例中，一底膠填充層42可形成於第一晶片30與第一重佈層20之間及形成於第二晶片36與第一重佈層20之間。在一些實施例中，第一囊封物40係一成型底膠填充(MUF)層且因此無需一額外底膠填充層。在一或多個實施例中，第一囊封物40覆蓋第一晶片30及第二晶片36之上表面及側壁。 如圖4D中所描繪，藉由(例如)研磨而移除第一囊封物40及鈍化層33之一部分以暴露第二晶片36之第二端子C2及第一晶片30之電端子30P。在一或多個實施例中，第一囊封物40及鈍化層33藉由研磨而薄化。 如圖4E中所描繪，一絕緣層44形成於第一囊封物40上方。在一或多個實施例中，絕緣層44之材料可包含(但不限於)諸如PBO之有機絕緣材料。絕緣層44包含暴露第二晶片36之第二端子C2及第一晶片30之電端子30P的若干開口。 如圖4F中所描繪，一第二重佈層70形成於第一囊封物40上方。第二重佈層70具有彼此對置之一第三表面703及一第四表面704，且第三表面703面向第一表面201。第二重佈層70透過第二端子C2電連接至第二晶片36且透過電端子30P電連接至第一晶片30。在一或多個實施例中，第二重佈層70包含彼此堆疊之若干導電層72及若干絕緣層74。在一些實施例中，(若干)導電層72之材料可包含(但不限於)金屬，諸如銅、鈦、其類似者或其等之一組合。(若干)絕緣層74之材料可包含(但不限於)無機及/或有機絕緣材料。第一晶片30透過第二重佈層70電連接至第二晶片36。在一或多個實施例中，一最上導電層72之一部分自第二重佈層70之第四表面704暴露。在一或多個實施例中，若干接合墊76 (諸如凸塊下金屬(UBM))形成於第二重佈層70之最上導電層72之暴露部分上方且電連接至第二重佈層70之最上導電層72之暴露部分。 如圖4G中所描繪，一或多個第三晶片50安置於第二重佈層70上方且電連接至第二重佈層70。第三晶片50透過第二重佈層70電連接至第一晶片30。在一些實施例中，第一晶片30之電端子30P之一部分透過第二重佈層70之一部分電連接至第三晶片50，且第一晶片30之電端子30P之另一部分透過第二重佈層70之另一部分電連接至第二晶片36。 如圖4H中所描繪，一第二囊封物58形成於第二重佈層70上方以覆蓋第三晶片50。 如圖4I中所描繪，第二囊封物58附著至一暫時基板60。接著，載體基板10自第一重佈層20之第二表面202拆離。 如圖4J中所描繪，第二重佈層70之一部分自第四表面704移除以暴露經組態為接合墊之一最下導電層72。在一或多個實施例中，第二重佈層70藉由諸如乾式蝕刻之蝕刻而移除。若干導體64形成於第二重佈層70之第四表面704上方且電連接至第二重佈層70。在一或多個實施例中，導體64包含(但不限於)導電凸塊。在一或多個實施例中，一或多個第四晶片66安置於第一重佈層20之第二表面202上方且電連接至第二重佈層70。在一或多個實施例中，執行一單粒化操作以形成若干半導體封裝結構3。接著，半導體封裝結構3自暫時基板60移除，如圖4K中所展示。 在半導體封裝結構3中，第三晶片50透過第二重佈層70電連接至第一晶片30。第一晶片30透過面向第二重佈層70之電端子30P電連接至第二重佈層70。第一晶片30亦透過第二重佈層70及具有貫穿通路結構36C (其具有精細節距)之第二晶片36電連接至第一重佈層20。第二晶片36避免在第一晶片30中形成貫穿通路結構，其有助於改良第一晶片30之良率。第二晶片36經組態以提供可與具有高I/O密度之晶片(諸如記憶體晶片)整合的數目增加I/O計數。 圖5係根據本揭露之一或多個實施例之一半導體封裝結構之一橫截面圖。如圖5中所描繪，半導體封裝結構4包含一第一重佈層20、一或多個第一晶片30、一或多個第二晶片36、一第一囊封物40、一第二重佈層70及一或多個第三晶片50。第一晶片30安置於第一重佈層20上方且透過電端子30P電連接至第一重佈層20。第二晶片36安置於第一重佈層20上方且電連接至第一重佈層20及第二重佈層70。第一囊封物40安置於第一重佈層20上方，且包圍第一晶片30及第二晶片36。第二重佈層70安置於第一囊封物40上方。第三晶片50安置於第二重佈層70上方且電連接至第二重佈層70。在一或多個實施例中，半導體封裝結構4進一步包含安置於第二重佈層70上方之一第二囊封物58及安置於第二囊封物58上方之一或多個第五晶片82。在一或多個實施例中，第五晶片82係諸如一記憶體封裝之一封裝。在一或多個實施例中，第二囊封物58係一成型底膠填充(MUF)層。在一或多個實施例中，第二囊封物58係一底膠填充(UF)層。第五晶片82透過第二囊封物58中之第一互連件78電連接至第二重佈層70。在一或多個實施例中，第一互連件78係(但不限於)導電凸塊。 圖6係根據本揭露之一或多個實施例之一半導體封裝結構之一橫截面圖。如圖6中所描繪，不同於半導體封裝結構4，半導體封裝結構5進一步包含介於第三晶片50與第二重佈層70之間之一底膠填充層59。在一或多個實施例中，第二囊封物58經組態為包圍底膠填充層59之一第二底膠填充層。 圖7係根據本揭露之一或多個實施例之一半導體封裝結構之一橫截面圖。如圖7中所描繪，不同於半導體封裝結構5，半導體封裝結構6之第一互連件78包含一導電凸塊782及一導電柱781，且導電凸塊782耦合至導電柱781。在一或多個實施例中，導電凸塊782係一焊料凸塊或一焊料膏，其中導電凸塊782之一端電連接至第五晶片82，且另一端電連接至各自導電柱781。導電柱781及導電凸塊782之製造及材料係不同的。在一或多個實施例中，導電柱781藉由沈積、光微影及蝕刻操作而形成，且因此可減小相鄰導電柱781之間之節距。相應地，與導電凸塊782相關聯之導電柱781能夠實現第二重佈層70與第五晶片82之間之精細節距接合。在一或多個實施例中，第二囊封物58包含一模塑料581及位於模塑料581上方之一底膠填充層582。模塑料581安置於第二重佈層70上方且包圍第一晶片30及導電柱781之側壁。底膠填充層582包圍導電凸塊782之側壁。 圖8A、圖8B、圖8C、圖8D、圖8E、圖8F、圖8G、圖8H及圖8I係根據本揭露之一或多個實施例之製造半導體封裝結構之各種操作之一者中的橫截面圖。如圖8A中所描繪，一第一重佈層20形成於一載體基板10上方。在一或多個實施例中，第二互連件84形成於第一重佈層20之第一表面201上方且電連接至第一重佈層20之第一表面201。在一些實施例中，第二互連件84係貫穿絕緣體通路(TIV)。 如圖8B中所描繪，一或多個第一晶片30安置於第一重佈層20之第一表面201上方。一或多個第二晶片36安置於第一重佈層20上方且電連接至第一重佈層20。在一些實施例中，第一晶片30可包含不同類型之晶片且可具有不同厚度。舉例而言，一些第一晶片30可包含諸如系統單晶片(SOC)之主動裝置晶片，且一些第一晶片30可包含被動裝置晶片。 如圖8C中所描繪，一第一囊封物40形成於第一重佈層20之第一表面201上方。在一或多個實施例中，第一囊封物40之材料係一模塑料。在一些實施例中，一底膠填充層42可形成於第一晶片30與第一重佈層20之間及形成於第二晶片36與第一重佈層20之間。在一些實施例中，第一囊封物40係一成型底膠填充(MUF)層且因此可無需一額外底膠填充層。 如圖8D中所描繪，藉由(例如)研磨而移除第一囊封物40之一部分以暴露第二晶片36之第二端子C2。 如圖8E中所描繪，一絕緣層44形成於第一囊封物40上方。絕緣層44包含暴露第二晶片36之第二端子C2的開口。一第二重佈層70形成於第一囊封物40上方。第二重佈層70透過第二端子C2電連接至第二晶片36。在一或多個實施例中，第二重佈層70包含彼此堆疊之若干導電層72及若干絕緣層74。在一或多個實施例中，一最上導電層72之一部分自第二重佈層70之第四表面704暴露。在一或多個實施例中，若干接合墊76 (諸如凸塊下金屬(UBM))形成於第二重佈層70之最上導電層72之暴露部分上方且電連接至第二重佈層70之最上導電層72之暴露部分。 如圖8F中所描繪，一或多個第三晶片50安置於第二重佈層70上方且電連接至第二重佈層70。在一些實施例中，第三晶片50之一部分透過第二重佈層70及第一晶片30電連接至第一重佈層20。在一些實施例中，第三晶片50之另一部分透過第二重佈層70及第二互連件84電連接至第一重佈層20。在一些實施例中，第三晶片50之一部分經由接合線51 (諸如金線)電連接至第二重佈層70。在一或多個實施例中，第三晶片50包含記憶體晶片、光電晶片、MEMS晶片、被動晶片或其等之一組合。 如圖8G中所描繪，一第二囊封物58形成於第二重佈層70上方以覆蓋第三晶片50。 如圖8H中所描繪，第二囊封物58附著至一暫時基板60。接著，載體基板10自第一重佈層20之第二表面202拆離。在一些實施例中，第二重佈層70之一部分自第四表面704移除以暴露經組態為接合墊之一最下導電層72。在一或多個實施例中，第二重佈層70藉由諸如乾式蝕刻之蝕刻而移除。若干導體64形成於第二重佈層70之第四表面704上方且電連接至第二重佈層70。在一或多個實施例中，導體64包含(但不限於)導電凸塊。在一或多個實施例中，一或多個第四晶片66安置於第一重佈層20之第二表面202上方且電連接至第二重佈層70。在一或多個實施例中，執行一單粒化操作以形成若干半導體封裝結構7。接著，半導體封裝結構7自暫時基板60移除，如圖8I中所展示。 圖9係根據本揭露之一或多個實施例之一半導體封裝結構之一橫截面圖。如圖9中所描繪，半導體封裝結構8之一或多個第三晶片50之一上表面50U自第二囊封物58暴露，使得第三晶片50能夠建立外部通信。在一些實施例中，第三晶片50可包含光電晶片(諸如CMOS影像感測器晶片)、MEMS晶片及高功率晶片。 圖10係根據本揭露之一或多個實施例之一半導體封裝結構之一橫截面圖。如圖10中所描繪，半導體封裝結構9進一步包含第二囊封物58及第三晶片50上方之一散熱器90。散熱器90由具有高導熱性之材料(諸如金屬)形成且經組態以改良第三晶片50之散熱性。在一些實施例中，第三晶片50可包含光電晶片(諸如CMOS影像感測器晶片)、MEMS晶片、記憶體晶片、高功率晶片、在操作期間產生熱之其他晶片或其他熱敏晶片。 在一或多個實施例中，半導體封裝結構包含諸如晶片之若干堆疊電子裝置。包含貫穿通路結構之一第二晶片經安置以提供兩個電子裝置之間之高密度互連及高選路靈活性。第二晶片提供用於晶片之間之互連的一短信號路徑。在一或多個實施例中，半導體封裝結構係一扇出晶圓級封裝(FOWLP)。在一或多個實施例中，半導體封裝結構與具有小外型尺寸之多層堆疊晶片相容。在一或多個實施例中，半導體封裝結構與異質整合設計(其中可整合具有不同大小及厚度之不同電子裝置，諸如半導體晶粒、晶片、封裝及中介層)相容。在一或多個實施例中，半導體封裝結構與散熱器相容以增強散熱能力。 在一例示性態樣中，一種半導體封裝結構包含一重佈層(RDL)、一第一晶片、一第二晶片、一囊封物及一第三晶片。該重佈層具有彼此對置之一第一表面及一第二表面。該第一晶片位於該重佈層之該第一表面上方且電連接至該重佈層。該第二晶片位於該重佈層之該第一表面上方且電連接至該重佈層。該第二晶片包含複數個貫穿通路結構。該囊封物位於該重佈層之該第一表面上方，其中該囊封物包圍該第一晶片及該第二晶片。該第三晶片位於該囊封物上方且透過該第二晶片之該等貫穿通路結構及該重佈層電連接至該第一晶片。 在另一例示性態樣中，一種半導體封裝結構包含一第一重佈層(RDL)、一第一晶片、一第二晶片、一第一囊封物、一第二重佈層、一第三晶片及一第二囊封物。該第一重佈層具有彼此對置之一第一表面及一第二表面。該第一晶片位於該第一重佈層之該第一表面上方。該第二晶片位於該第一重佈層之該第一表面上方。該第二晶片包含複數個貫穿通路結構，且該貫穿通路結構之一第一端子耦合至該第一重佈層。該第一囊封物位於該第一重佈層之該第一表面上方，其中該第一囊封物包圍該第一晶片及該第二晶片。該第二重佈層位於該第一囊封物上方且電連接至該貫穿通路結構之一第二端子。該第二重佈層具有彼此對置之一第三表面及一第四表面，且該第三表面面向該第一表面。該第三晶片位於該第二重佈層之該第四表面上方且電連接至該第二重佈層。該第二囊封物位於該第二重佈層上方。 在又一態樣中，一種用於製造一半導體封裝結構之方法包含以下操作。形成一第一重佈層。將一第一晶片安置於該第一重佈層上方。將一第二晶片安置於該第一重佈層上方，其中該第二晶片包含複數個貫穿通路結構。使一囊封物形成於該第一重佈層上方。使一第三晶片形成於該囊封物上方，其中該第三晶片及該第一重佈層透過該第二晶片之該等貫穿通路結構電連接。 上文已概述若干實施例之結構，使得熟習技術者可較佳理解本揭露之態樣。熟習技術者應瞭解，其可容易地使用本揭露作為設計或修改用於實施相同目的及/或達成本文所引入之實施例之相同優點之其他製程及結構的一基礎。熟習技術者亦應認識到，此等等效構造不應背離本揭露之精神及範疇，且其可在不背離本揭露之精神及範疇之情況下對本文作出各種改變、取代及更改。
1‧‧‧半導體封裝結構
2‧‧‧半導體封裝結構
3‧‧‧半導體封裝結構
4‧‧‧半導體封裝結構
5‧‧‧半導體封裝結構
6‧‧‧半導體封裝結構
7‧‧‧半導體封裝結構
8‧‧‧半導體封裝結構
9‧‧‧半導體封裝結構
10‧‧‧載體基板
20‧‧‧第一重佈層
22‧‧‧導電層
24‧‧‧絕緣層
26‧‧‧接合墊
30‧‧‧第一晶片
30P‧‧‧電端子
31‧‧‧黏著層
32‧‧‧導電材料
33‧‧‧鈍化層
36‧‧‧第二晶片
36C‧‧‧貫穿通路結構
36P‧‧‧接觸墊
38‧‧‧導電材料
40‧‧‧第一囊封物
42‧‧‧底膠填充層
44‧‧‧絕緣層
46‧‧‧接合墊
48‧‧‧導電材料
50‧‧‧第三晶片
50U‧‧‧上表面
51‧‧‧接合線
52‧‧‧DRAM裝置
54‧‧‧互連件
56‧‧‧貫穿通路結構
58‧‧‧第二囊封物
59‧‧‧底膠填充層
60‧‧‧暫時基板
62‧‧‧框架
64‧‧‧導體
66‧‧‧第四晶片
70‧‧‧第二重佈層
72‧‧‧導電層
74‧‧‧絕緣層
76‧‧‧接合墊
78‧‧‧第一互連件
82‧‧‧第五晶片
84‧‧‧第二互連件
90‧‧‧散熱器
100‧‧‧方法
110‧‧‧操作
120‧‧‧操作
130‧‧‧操作
140‧‧‧操作
150‧‧‧操作
201‧‧‧第一表面
202‧‧‧第二表面
581‧‧‧模塑料
582‧‧‧底膠填充層
703‧‧‧第三表面
704‧‧‧第四表面
781‧‧‧導電柱
782‧‧‧導電凸塊
C1‧‧‧第一端子
C2‧‧‧第二端子
自結合附圖來解讀之以下詳細描述最佳地理解本揭露之態樣。應注意，根據行業標準做法，各種結構未按比例繪製。事實上，為使討論清楚，可任意增大或減小各種結構之尺寸。 圖1係繪示根據本揭露之各種態樣之用於製造一半導體封裝結構之一方法的一流程圖。 圖2A、圖2B、圖2C、圖2D、圖2E、圖2F、圖2G、圖2H、圖2I、圖2J及圖2K係根據本揭露之一或多個實施例之製造半導體封裝結構之各種操作之一者中的橫截面圖。 圖3係根據本揭露之一或多個實施例之一半導體封裝結構之一橫截面圖。 圖4A、圖4B、圖4C、圖4D、圖4E、圖4F、圖4G、圖4H、圖4I、圖4J及圖4K係根據本揭露之一或多個實施例之製造半導體封裝結構之各種操作之一者中的橫截面圖。 圖5係根據本揭露之一或多個實施例之一半導體封裝結構之一橫截面圖。 圖6係根據本揭露之一或多個實施例之一半導體封裝結構之一橫截面圖。 圖7係根據本揭露之一或多個實施例之一半導體封裝結構之一橫截面圖。 圖8A、圖8B、圖8C、圖8D、圖8E、圖8F、圖8G、圖8H及圖8I係根據本揭露之一或多個實施例之製造半導體封裝結構之各種操作之一者中的橫截面圖。 圖9係根據本揭露之一或多個實施例之一半導體封裝結構之一橫截面圖。 圖10係根據本揭露之一或多個實施例之一半導體封裝結構之一橫截面圖。

Claims (1)

  1. 一種半導體封裝結構，其包括： 一重佈層，其具有彼此對置之一第一表面及一第二表面； 一第一晶片，其位於該重佈層之該第一表面上方且電連接至該重佈層； 一第二晶片，其位於該重佈層之該第一表面上方，其中該第二晶片包含複數個貫穿通路結構； 一囊封物，其位於該重佈層之該第一表面上方，其中該囊封物包圍該第一晶片及該第二晶片；及 一第三晶片，其位於該囊封物上方且透過該第二晶片之該等貫穿通路結構及該重佈層電連接至該第一晶片。
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