TW202125729A - 封裝及其形成方法 - Google Patents

封裝及其形成方法 Download PDF

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TW202125729A
TW202125729A TW109115389A TW109115389A TW202125729A TW 202125729 A TW202125729 A TW 202125729A TW 109115389 A TW109115389 A TW 109115389A TW 109115389 A TW109115389 A TW 109115389A TW 202125729 A TW202125729 A TW 202125729A
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Taiwan
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package
spacer
connector
solder
layer
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TW109115389A
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TWI721884B (zh
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曹智強
謝靜華
林修任
郭炫廷
張家綸
翁正軒
邱肇瑋
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台灣積體電路製造股份有限公司
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Publication of TWI721884B publication Critical patent/TWI721884B/zh
Publication of TW202125729A publication Critical patent/TW202125729A/zh

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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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Abstract

一種封裝包括第一封裝及第二封裝，且第一封裝具有翹曲形狀。附接至第一封裝的重佈線結構的第一連接件包括嵌入於其中的間隔物。附接至重佈線結構的第二連接件不含間隔物，且第一連接件的間隔物在將第一封裝附接至第二封裝期間保持第一封裝與第二封裝之間的最小距離。

Description

封裝及其形成方法
半導體業界已歸因於各種電子組件（例如，電晶體、二極體、電阻器、電容器等）的進行中的積體密度改良而經歷快速發展。主要而言，積體密度的改良已由最小特徵大小的迭代減小引起，此允許將更多組件整合至給定區域中。由於對縮小的電子元件的需求已增長，故已出現對更小且更具創造性的半導體晶粒的封裝技術的需要。此類封裝系統的實例為層疊式封裝（Package-on-Package；PoP）技術。在PoP元件中，頂部半導體封裝堆疊於底部半導體封裝的頂部上，以提供高水準的整合及組件密度。PoP技術通常使得能夠生產具有增強的功能性及在印刷電路板（printed circuit board；PCB）上的較小佔據面積的半導體元件。
以下揭露內容提供用於實施本發明的不同特徵的諸多不同實施例或實例。下文描述組件及配置的具體實例以簡化本揭露內容。當然，此等具體實例僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或第二特徵上形成可包含第一特徵與第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可形成於第一特徵與第二特徵之間使得第一特徵與第二特徵可能不直接接觸的實施例。此外，本揭露內容可在各種實例中重複附圖標號及/或字母。此重複是出於簡單及清楚的目的，且本身並不規定所論述的各種實施例及/或組態之間的關係。
另外，為易於描述，本文中可使用諸如「在......之下」、「在......下方」、「下部」、「在......之上」、「上部」以及類似者的空間相對術語來描述如在圖式中所示出的一個部件或特徵與另一部件或特徵的關係。除圖式中所描繪的定向之外，空間相對術語意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向（旋轉90度或處於其他定向）且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
實施例包含積體扇出（integrated fan-out；InFO）封裝，所述積體扇出封裝包含晶粒及積體重佈線結構。歸因於InFO封裝中的各種材料的熱膨脹係數（coefficient of thermal expansion；CTE）的不匹配，翹曲可導致InFO封裝彎折（bowing）。彎折可包含正偏（positive biased）彎折（「微笑」形狀）及負偏（negative biased）彎折（「哭泣」或「皺眉」形狀）兩者。歸因於翹曲，當將InFO封裝附接至諸如印刷電路板（PCB）的另一元件時，InFO封裝的一些區域比其他區域更靠近PCB。舉例而言，若翹曲導致皺眉形狀的InFO封裝，則當使InFO封裝對準至PCB以附接至PCB時，InFO封裝的邊緣與PCB之間的距離小於InFO封裝的中間與PCB之間的距離。當回焊焊料連接件以將InFO封裝附接至PCB時，翹曲的邊緣可能過於靠近PCB按壓。因此，在InFO封裝與PCB之間的較小空間擠壓焊料過於靠近相鄰連接件處可發生連接件之間的焊料橋接（solder bridging）。類似情況亦因微笑形狀翹曲而出現，其中InFO封裝的中心可能過於靠近PCB從而導致中心處的連接件之間的橋接。實施例藉由利用InFO封裝與PCB之間的間隔物來解決此問題，所述間隔物整合至連接件中以維持InFO封裝與PCB之間的最小距離。
圖1至圖28A以及圖28B示出根據一些實施例的用於形成積體扇出封裝100的製程的中間步驟的剖面視圖。積體扇出封裝100的形成可用於下文所論述的與連接件間隔物相關的實施例中的任一者中。圖1至圖12示出用於形成積體扇出封裝100的製程的中間步驟直至封裝100準備好容納連接件為止的剖面視圖。
在圖1中，提供載板102以用於封裝100，且釋放層104形成於載板102上。載板102可為玻璃載板、陶瓷載板或類似者。載板102可為晶圓，以使得多個封裝可同時形成於載板102上。釋放層104可由聚合物類材料形成，可將所述聚合物類材料連同載板102一起自將形成於後續步驟中的上覆結構移除。在一些實施例中，釋放層104為在加熱時損失其黏著性質的環氧類熱釋放材料，諸如光熱轉換（light-to-heat-conversion；LTHC）釋放塗層。在其他實施例中，釋放層104可為在暴露於UV光時損失其黏著性質的紫外（ultra-violet；UV）黏膠。釋放層104可配製為液體且經固化，可為疊層至載板102上的疊層膜，或可為類似者。釋放層104的頂部表面可為水平的（leveled）。
在圖2中，第一重佈線結構106形成於釋放層104上。第一重佈線結構106包含介電層108、介電層112、介電層116以及介電層120；以及金屬化圖案110、金屬化圖案114以及金屬化圖案118。金屬化圖案亦可被稱為重佈線層或重佈線（redistribution line）。第一重佈線結構106被作為實例繪示。更多或更少介電層及金屬化圖案可形成於第一重佈線結構106中。若待形成更少介電層及金屬化圖案，則可省略下文所論述的步驟及製程。若待形成更多介電層及金屬化圖案，則可重複下文所論述的步驟及製程。
作為用以形成第一重佈線結構106的實例，在釋放層104上沈積介電層108。在一些實施例中，介電層108由可使用微影罩幕來圖案化的感光性材料形成，諸如聚苯并噁唑（polybenzoxazole；PBO）、聚醯亞胺、苯環丁烷（benzocyclobutene；BCB）或類似者。介電層108可藉由旋轉塗佈、疊層、CVD、類似者或其組合來形成。接著使介電層108圖案化。圖案化形成暴露釋放層104的部分的開口。可藉由可接受的製程來圖案化，諸如藉由當介電層108為感光性材料時使介電層108暴露於光或藉由使用例如非等向性蝕刻來蝕刻。若介電層108為感光性材料，則介電層108可在暴露之後顯影。
接著形成金屬化圖案110。金屬化圖案110包含位於介電層108的主表面上且沿著所述介電層108的主表面延伸的導電線。金屬化圖案110更包含延伸穿過介電層108的導通孔。為形成金屬化圖案110，晶種層形成於介電層108上及延伸穿過介電層108的開口中。在一些實施例中，晶種層為金屬層，所述金屬層可為單一層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及所述鈦層上方的銅層。晶種層可使用例如PVD或類似者來形成。接著在晶種層上形成且圖案化光阻。光阻可藉由旋轉塗佈或類似者來形成且可暴露於光以用於圖案化。光阻的圖案對應於金屬化圖案110。圖案化形成穿過光阻的開口以暴露晶種層。接著導電材料形成於光阻的開口中及晶種層的暴露部分上。導電材料可藉由鍍覆形成，所述鍍覆諸如電鍍或無電式鍍覆或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。導電材料與其下方部分的晶種層的組合形成金屬化圖案110。移除其上未形成導電材料的光阻及晶種層的部分。可藉由可接受的灰化或剝除製程來移除光阻，諸如使用氧電漿或類似者。一旦移除光阻，則諸如藉由使用可接受的蝕刻製程（諸如藉由濕式或乾式蝕刻）來移除晶種層的暴露部分。
使介電層112沈積於金屬化圖案110及介電層108上。介電層112可以類似於介電層108的方式形成，且可由與介電層108相同的材料形成。
接著形成金屬化圖案114。金屬化圖案114包含位於介電層112的主表面上且沿著所述介電層112的主表面延伸的導電線。金屬化圖案114更包含延伸穿過介電層112的導通孔以實體連接且電性連接至金屬化圖案110。金屬化圖案114可以類似於金屬化圖案110的方式形成，且可由與金屬化圖案110相同的材料形成。金屬化圖案114的導通孔具有小於金屬化圖案110的導通孔的寬度。因此，當為了金屬化圖案114而使介電層112圖案化時，介電層112中的開口的寬度小於介電層108中的開口的寬度。
使介電層116沈積於金屬化圖案114及介電層112上。介電層116可以類似於介電層108的方式形成，且可由與介電層108相同的材料形成。
接著形成金屬化圖案118。金屬化圖案118包含位於介電層116的主表面上且沿著所述介電層116的主表面延伸的導電線。金屬化圖案118更包含延伸穿過介電層116的導通孔以實體連接且電性連接至金屬化圖案114。金屬化圖案118可以類似於金屬化圖案110的方式形成，且可由與金屬化圖案110相同的材料形成。金屬化圖案118的導通孔具有小於金屬化圖案110的導通孔的寬度。因此，當為了金屬化圖案114而使介電層116圖案化時，介電層116中的開口的寬度小於介電層108中的開口的寬度。
使介電層120沈積於金屬化圖案118及介電層116上。介電層120可以類似於介電層108的方式形成，且可由與介電層108相同的材料形成。
在圖3中，球下金屬（UBM）122形成於介電層120上且延伸穿過所述介電層120。作為形成UBM 122的實例，可使介電層120圖案化以形成暴露金屬化圖案118的部分的開口。可藉由可接受的製程來圖案化，諸如藉由當介電層120為感光性材料時使介電層120暴露於光或藉由使用例如非等向性蝕刻來蝕刻。若介電層120為感光性材料，則介電層120可在暴露之後顯影。在一些實施例中，針對UBM 122的開口可寬於針對金屬化圖案110、金屬化圖案114以及金屬化圖案118的導通孔部分的開口。在一些實施例中，針對UBM 122的開口可窄於針對金屬化圖案110、金屬化圖案114以及金屬化圖案118的導通孔部分的開口，或與針對金屬化圖案110、金屬化圖案114以及金屬化圖案118的導通孔部分的開口約為相同寬度。晶種層形成於介電層120上及開口中。在一些實施例中，晶種層為金屬層，所述金屬層可為單一層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及所述鈦層上方的銅層。晶種層可使用例如PVD或類似者來形成。接著在晶種層上形成且圖案化光阻。光阻可藉由旋轉塗佈或類似者來形成，且可暴露於光以用於圖案化。光阻的圖案對應於UBM 122。圖案化形成穿過光阻的開口以暴露晶種層。導電材料形成於光阻的開口中及晶種層的暴露部分上。導電材料可藉由鍍覆形成，所述鍍覆諸如電鍍或無電式鍍覆或類似者。導電材料可包括金屬，如銅、鎳、鈦、鎢、鋁或類似者。接著，移除其上未形成導電材料的光阻及晶種層的部分。可藉由可接受的灰化或剝除製程來移除光阻，諸如使用氧電漿或類似者。一旦移除光阻，則諸如藉由使用可接受的蝕刻製程（諸如藉由濕式或乾式蝕刻）來移除晶種層的暴露部分。晶種層的剩餘部分及導電材料形成UBM 122。在以不同方式形成UBM 122的實施例中，可利用更多光阻及圖案化步驟。
UBM 122可能不全部具有相同寬度。在一些實施例中，第一重佈線結構106的第一區105A中的第一子組UBM 122具有第一寬度W1 ，且第一重佈線結構106的第二區105B中的第二子組UBM 122具有第二寬度W2 。第一寬度W1 可不同於第二寬度W2 ，且在一些實施例中，第一寬度W1 大於第二寬度W2 。第一寬度W1 可在約100微米與約300微米之間，諸如約170微米，但預期可使用其他值。第二寬度W2 可在約25微米與約90微米之間，諸如約48微米，但預期可使用其他值。
在圖4中，根據一些實施例，第一區105A的UBM 122中的一些或全部可改為形成為導電柱122p。導電柱122p可藉由使用光阻持續鍍覆第一區105A的UBM 122直至導電柱122p達到所需高度H1 為止來形成，且所述高度H1 諸如在約10微米與約250微米之間，諸如約150微米，但預期可使用其他值。在一些實施例中，導電柱的寬度W3 可對應於介電層120中的開口，所述介電層120經圖案化以暴露金屬化圖案118的部分。在一些實施例中，寬度W3 可寬於或窄於介電層120中的開口。寬度W3 可在約50微米與約300微米之間，諸如約150微米，但預期可使用其他值。
在圖5中，根據一些實施例，第一區105A的UBM 122中的一些或全部可具有配置於其上的導電柱122p。在形成UBM 122之後，另一光阻可藉由旋轉塗佈或類似方式來形成且暴露於光以用於圖案化。光阻的圖案對應於導電柱122p的圖案。所述圖案化形成光阻中的開口以暴露UBM 122。導電柱122p的導電材料可藉由鍍覆形成，諸如電鍍或無電式鍍覆或類似者，直至導電柱122p達到所需高度H2 為止，所述高度H2 在約10微米與約250微米之間，諸如約150微米，但預期可使用其他值。導電柱的寬度W4 對應於光阻的圖案的開口的寬度。寬度W4 可在約50微米與約300微米之間，諸如約150微米，但預期可使用其他值。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。接著，移除光阻。可藉由可接受的灰化或剝除製程來移除光阻，諸如使用氧電漿或類似者。所得結構可具有包圍導電柱122p的基部的UBM 122的肩部122s。
儘管其餘圖式示出如關於圖5所描述而配置的導電柱122p，但應理解的是，可在適當時替換如關於圖4所描述而配置的導電柱122p（亦即，不具有UBM 122），除非另外指出。
在圖6中，將積體電路晶粒124置放於第一重佈線結構106上。積體電路晶粒124可使用例如取放工具（pick-and-place tool）來對準及置放。將積體電路晶粒124置放於第一重佈線結構106上，使得導電連接件128與第二區105B中的UBM 122對準。在置放積體電路晶粒124之後，回焊導電連接件128以形成UBM 122及晶粒連接件66中的對應者之間的接頭，從而將積體電路晶粒124實體連接且電性連接至第一重佈線結構106。
參考一下圖7，圖7示出根據一些實施例的積體電路晶粒124的剖面視圖。積體電路晶粒124將在後續處理中經封裝以形成積體電路封裝。積體電路晶粒124可為邏輯晶粒（例如，中央處理單元（central processing unit；CPU）、圖形處理單元（graphics processing unit；GPU）、系統晶片（system-on-a-chip；SoC）、應用程式處理器（application processor；AP）、微控制器等）、記憶體晶粒（例如，動態隨機存取記憶體（dynamic random access memory；DRAM）晶粒、靜態隨機存取記憶體（static random access memory；SRAM）晶粒等）、功率管理晶粒（例如，功率管理積體電路（power management integrated circuit；PMIC）晶粒）、射頻（radio frequency；RF）晶粒、感測器晶粒、微機電系統（micro-electro-mechanical-system；MEMS）晶粒、訊號處理晶粒（例如，數位訊號處理（digital signal processing；DSP）晶粒）、前端晶粒（例如，類比前端（analog front-end；AFE）晶粒）、類似者，或其組合。
積體電路晶粒124可形成於晶圓中，所述晶圓可包含在後續步驟中經單體化以形成多個積體電路晶粒的不同元件區。積體電路晶粒124可根據可適用的製造製程經處理以形成積體電路。舉例而言，積體電路晶粒124包含諸如摻雜矽或未摻雜矽的半導體基板52，或絕緣層上半導體（semiconductor-on-insulator；SOI）基板的主動層。半導體基板52可包含：其他半導體材料，諸如鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用其他基板，諸如多層或梯度基板。半導體基板52具有有時稱為前側的主動表面（例如，圖7中面向上方的表面）及有時稱為背側的非主動表面（例如，圖7中面向下方的表面）。
元件54可形成於半導體基板52的前表面處。元件54可為主動元件（例如，電晶體、二極體等）、電容器、電阻器等。層間介電質（inter-layer dielectric；ILD）56位於半導體基板52的前表面上。ILD 56包圍且可覆蓋元件54。ILD 56可包含由諸如磷矽酸鹽玻璃（Phospho-Silicate Glass；PSG）、硼矽酸鹽玻璃（Boro-Silicate Glass；BSG）、硼摻雜的磷矽酸鹽玻璃（Boron-Doped Phospho-Silicate Glass；BPSG）、未摻雜的矽酸鹽玻璃（undoped Silicate Glass；USG）或類似者所形成的一或多個介電層。
導電插塞58延伸穿過ILD 56以電性耦接且實體耦接元件54。舉例而言，當元件54為電晶體時，導電插塞58可耦接電晶體的閘極及源極/汲極區。導電插塞58可由鎢、鈷、鎳、銅、銀、金、鋁、類似者或其組合形成。內連線結構60位於ILD 56及導電插塞58上。內連線結構60使元件54內連以形成積體電路。內連線結構60可由例如ILD 56上的介電層中的金屬化圖案形成。金屬化圖案包含形成於一或多個低k介電層中的金屬線及通孔。內連線結構60的金屬化圖案藉由導電插塞58電性耦接至元件54。
積體電路晶粒124更包含進行外部連接的襯墊62，諸如鋁襯墊。襯墊62位於積體電路晶粒124的主動側上，諸如位於內連線結構60中及/或所述內連線結構60上。一或多個鈍化膜64位於積體電路晶粒124上，諸如位於內連線結構60及襯墊62的部分上。開口穿過鈍化膜64延伸至襯墊62。諸如導電柱（例如，由諸如銅的金屬形成）的晶粒連接件66延伸穿過鈍化膜64中的開口，且實體耦接且電性耦接至襯墊62的各別者。晶粒連接件66可藉由例如鍍覆或類似者來形成。晶粒連接件66電性耦接積體電路晶粒124的各別積體電路。
可選地，焊料區（例如，焊料球或焊料凸塊）可配置於襯墊62上。焊料球可用以對積體電路晶粒124進行晶片探針（chip probe；CP）測試。可對積體電路晶粒124進行CP測試以確認積體電路晶粒124是否為良裸晶粒（known good die；KGD）。因此，僅針對為KGD的積體電路晶粒124進行後續處理而封裝，且不封裝未通過CP測試的晶粒。在測試之後，可在後續處理步驟中移除焊料區。
介電層68可（或可能不）位於積體電路晶粒124的主動側上，諸如位於鈍化膜64及晶粒連接件66上。介電層68橫向地包封晶粒連接件66，且介電層68與積體電路晶粒124橫向地共端（laterally coterminous）。最初，介電層68可掩埋晶粒連接件66，使得介電層68的最頂部表面位於晶粒連接件66的最頂部表面上。在焊料區配置於晶粒連接件66上的一些實施例中，介電層68亦可掩埋焊料區。或者，可在形成介電層68之前移除焊料區。
介電層68可為：聚合物，諸如PBO、聚醯亞胺、BCB或類似者；氮化物，諸如氮化矽或類似者；氧化物，諸如氧化矽、PSG、BSG、BPSG或類似者；類似者，或其組合。介電層68可例如藉由旋轉塗佈、疊層、化學氣相沈積（chemical vapor deposition；CVD）或類似者來形成。在一些實施例中，晶粒連接件66在積體電路晶粒124的形成期間經由介電層68暴露。在一些實施例中，晶粒連接件66保持掩埋且在用於封裝積體電路晶粒124的後續製程期間暴露。暴露晶粒連接件66可移除可能存在於晶粒連接件66上的任何焊料區。
在一些實施例中，積體電路晶粒124為包含多個半導體基板52的堆疊元件。舉例而言，積體電路晶粒124可為記憶體元件，諸如混合記憶體立方體（hybrid memory cube；HMC）模組、高頻寬記憶體（high bandwidth memory；HBM）模組，或包含多個記憶體晶粒的類似者。在此類實施例中，積體電路晶粒124包含藉由基板穿孔（through-substrate via；TSV）內連的多個半導體基板52。半導體基板52中的每一者可（或可能不）具有內連線結構60。
現在返回參考圖6，根據一些實施例，由於積體電路晶粒124的主動側面向第一重佈線結構106，故第一重佈線結構106亦可被稱為前側重佈線結構。且由於積體電路晶粒124的主動側面向下方且朝向第一重佈線結構106，故所得封裝可稱為底部扇出封裝。在其他實施例中，諸如在下文關於圖13、圖15、圖17、圖19、圖22、圖23、圖25以及圖27所示出，積體電路晶粒124的主動側可面向上方。導電連接件128可形成於晶粒連接件66上（參見圖7）。導電連接件128可由導電材料形成，所述導電材料諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者，或其組合。在一些實施例中，導電連接件128為焊料連接件。
底部填充膠130可形成於積體電路晶粒124與第一重佈線結構106之間，從而包圍導電連接件128。因此，可保護導電連接件128不受機械力損壞。底部填充膠130可在附接積體電路晶粒124之後藉由毛細流動製程（capillary flow process）形成，或可在附接積體電路晶粒124之前藉由合適的沈積方法形成。
在圖8中，根據一些實施例，使環或封蓋200對準至導電柱122p以將導電連接件226耦接至導電柱122p中的各別者。封蓋200可使用例如取放工具來對準及置放。將封蓋200置放於第一重佈線結構106上，使得導電連接件226與第一區105A中的UBM 122及/或導電柱122p對準。
封蓋200可為中介板（interposer）、散熱器（參見圖11）、重佈線結構或其組合。如圖8中所示出，封蓋200包含具有重佈線結構的中介板。封蓋200對準至封裝100。
在封蓋200為中介板的情況下，封蓋200可包含一或多個基板核心，統稱為基板核心210。基板核心210可由預浸漬複合纖維（「預浸體（prepreg）」）、絕緣膜或累積膜（build-up film）、紙、玻璃纖維、無紡玻璃織品、矽或類似者形成。在一些實施例中，基板核心210由包含玻璃纖維及樹脂的預浸體形成。在一些實施例中，基板核心210可為銅包覆環氧樹脂浸漬的玻璃布疊層物、銅包覆聚醯亞胺浸漬的玻璃布疊層物，或類似者。導電層206可為銅、鈦、鎳、鋁、其組成物或類似者的一或多個層，且可使用任何適當的製程來形成，諸如藉由金屬箔片疊層、化學氣相沈積（CVD）、物理氣相沈積（physical vapor deposition；PVD）等等來形成。在一些實施例中，導電層206可為經熱疊層至基板核心210的箔片。在一些實施例中，導電層206可為類似於關於第一重佈線結構106所描述的重佈線結構。導電連接件226可形成於導電層206上。可形成阻焊劑（solder resist）224以包圍及保護導電連接件226的側面。導通孔216可將來自導電層206的訊號提供至封蓋200的相對側。另一導電層213（其可類似於導電層206）可用以將來自導通孔216的訊號提供至待安裝於封蓋200頂上的另一元件。導通孔216、導電層206以及導電層213可由導電材料形成，諸如銅、鈦、鎢、鋁或類似者。另一阻焊劑224可用於封蓋200頂上，且開口可形成於所述阻焊劑224中以暴露導電層213的部分。
在圖9中，在置放封蓋200之後，回焊導電連接件226以形成導電柱122p與導電層206中的對應者之間的接頭，從而將封蓋200實體連接且電性連接至第一重佈線結構106。包封體134形成於各種組件上。包封體134可為模塑化合物、環氧樹脂或類似者，且可藉由壓縮模塑、轉移模塑或類似者來施加。包封體134可形成於第一重佈線結構106上，以使得積體電路晶粒124被掩埋或覆蓋且封蓋200與第一重佈線結構106之間的空間被填充。包封體134接著經固化。在一些實施例中，包封體134亦形成於第一重佈線結構106與積體電路晶粒124之間，例如在省略底部填充膠130的實施例中。在一些實施例中，包封體134在置放封蓋200之前形成以有助於支撐導電柱122p。
在圖10中，根據一些實施例，示出省略導電柱122p的實施例。在此類實施例中，導電連接件226可自封蓋200延伸至第一重佈線結構106的UBM 122。在一些實施例中，包封體134在置放封蓋200之前形成，且其中形成有孔洞以用於置放導電連接件226。應理解的是，省略導電柱122p的實施例未按比例繪示，且導電連接件226可能比如所示出的更為球形。
在圖11中，在封蓋200為散熱器250的實施例中，可省略導電柱122p以及UBM 122。散熱器250可包含上部封蓋252及環254，且可藉由熱黏著劑255安裝至第一重佈線結構106。此外，熱黏著劑260可用於積體電路晶粒124的背表面上。散熱器250可由金屬或金屬合金製成，諸如鋁、銅、氮化鋁等等。熱黏著劑255及熱黏著劑260可為任何合適的黏著劑、環氧樹脂、底部填充膠、晶粒貼合膜（die attach film；DAF）、熱界面材料或類似者。可將熱黏著劑255及熱黏著劑260施加於積體電路晶粒124的背側，或可將熱黏著劑255及熱黏著劑260施加至上部封蓋252的區域。
將在封蓋200為散熱器250的情況下示出其餘中間步驟，然而，應理解的是，可使用諸如上文所論述的另一封蓋類型。
在圖12中，移除載板102。載板102可自第一重佈線結構106脫離（或「剝離」）。在一些實施例中，剝離包含將諸如雷射光或UV光的光投射於釋放層104上，使得釋放層104在光的熱量下分解而可移除載板102。接著翻轉結構且將其置放於膠帶上。所述剝離暴露第一重佈線結構106的金屬化圖案110。
圖13至圖17示出根據一些實施例的用於使用球安裝間隔物（ball mount spacer）的各種組態。在圖13中，可將諸如表面安裝元件（surface mount device；SMD）（諸如電容器、電阻器、調節器、功率控制器等等）的可選元件140安裝至第一重佈線結構106的表面且電性耦接至金屬化圖案110中的一或多者。元件140可藉由取放製程來置放。在一些實施例中，在置放元件140之前，鈍化層可用於金屬化圖案110上方且經圖案化以暴露金屬化圖案110的一部分。在一些實施例中，UBM可形成於金屬化圖案110的暴露部分上。在此類實施例中，UBM可使用類似於UBM 122的製程及材料來形成。在一些實施例中，焊料膏可沈積於金屬化圖案110上，諸如金屬化圖案110附接有元件140的部分上。在一些實施例中，可進行回焊以將元件140實體耦接且電性耦接至金屬化圖案110。
在圖14A、圖14B以及圖14C中，示出用於球型間隔物150A、球型間隔物150B或球型間隔物150C（或總體而言，間隔物150（參見圖15））的不同組態以用於維持封裝100與另一元件之間的間距，同時藉由含有間隔物150的連接件將封裝100同時電性附接且實體附接至所述另一元件。在圖14A中，提供間隔物150A，其為實心球體。間隔物150A的核心材料可包含任何合適的材料，諸如金屬（例如，銅、銀、鋁、金、鎳、鉛、鉍、銦等）、金屬合金（例如，焊料）、化合物、塑膠、陶瓷等等。選擇間隔物150A的材料，使得其具有高於其他標準連接件（例如，包括焊料或類似者且不含間隔物150A）的回焊溫度的更高熔點溫度。此將在下文更詳細地描述。間隔物150A可具有在約30微米與約760微米之間的直徑，但預期可使用其他尺寸。
在圖14B中，提供具有實心中心核心152的間隔物150B，所述實心中心核心152塗佈有第一層154，所述第一層154塗佈有第二層156。在一些實施例中，可省略第一層154。實心中心核心152可為上文關於間隔物150A所論述的材料中的任一者，且可具有在約30微米與約760微米之間的直徑。第一層154可為阻障層以防止實心中心核心152的材料滲入（leech）至包圍材料中。第一層154可在約0.5微米厚與約30微米厚之間，且可由任何合適的材料製成，諸如經鍍覆至實心中心核心152上且包圍實心中心核心152的鎳、氮化鈦、氮化鉭等等。第二層156可包含諸如焊料材料的共晶材料（eutectic material），其經鍍覆至第一層154上或在省略第一層154的情況下鍍覆至實心中心核心152上，且包圍實心中心核心152及第一層154（若使用所述第一層154）。在一些實施例中，第二層156可在約0.5微米厚與約30微米厚之間。選擇實心中心核心152的材料，使得其具有高於其他標準連接件（例如，包括焊料或類似者且不含間隔物150B）的回焊溫度的更高熔點溫度。第二層156的材料可具有類似於其他標準連接件的回焊溫度的回焊溫度，使得第二層156可回焊。因此，第二層156的材料不同於實心中心核心152的材料。
在圖14C中，根據一些實施例，示出諸多層的間隔物150C。在圖14C中，實心中心核心158可塗佈有若干額外層。在一些實施例中，實心中心核心158可藉由第一阻障層160、接著導電層162、隨後第二阻障層164來塗佈，以使得導電層162包夾於兩個阻障層之間。在形成第二阻障層164之後，可將焊料層166塗佈於第二阻障層164上。在一些實施例中，焊料層166可摻雜有另一材料以形成焊料層166的經摻雜子層168。在一些實施例中，實心中心核心158可為塑膠核心，但可使用其他候選材料中的任一者，所述其他候選材料諸如上文關於間隔物150A所論述的彼等材料。第一阻障層160及第二阻障層164可由相同材料或不同材料製成，且可為任何合適的阻障材料，諸如鎳、氮化鈦、氮化鉭等等。導電層162可包含任何合適的導電材料，諸如銅、鋁、銀或其組合，或類似者。焊料層166可為任何合適的焊料材料，諸如錫銀複合物。經摻雜子層168可包含鎳或另一合適的材料作為摻雜劑以減少間隔物150C的外層的氧化。選擇實心中心核心158及/或導電層162的材料，使得其具有高於其他標準連接件（例如，包括焊料或類似者且不含間隔物150C）的回焊溫度的更高熔點溫度。
間隔物150A、間隔物150B或間隔物150C包含具有更高熔點溫度的核心材料。在一些實施例中，核心材料可為焊料材料，只要其他連接件（例如，圖15的導電連接件170）具有小於核心材料的熔點的熔點即可。舉例而言，若連接件為矽鉍焊料球，則回焊溫度為約170℃。具有約217℃回焊溫度的錫、銀及銅的焊料合金（例如，分別為96.5%、3%以及0.5%）可供用於間隔物150A、間隔物150B或間隔物150C的核心材料。因此，可加熱焊料連接件以回焊，以在不回焊間隔物150A、間隔物150B或間隔物150C的核心材料的情況下進行連接。一般而言，核心材料的熔點應至少高於其他導電連接件170（參見圖15）的材料的熔點約30℃至50℃。類似而言，在使用包含外焊料層的間隔物150B或間隔物150C（諸如間隔物150B的第二層156或間隔物150C的焊料層166）的情況下，核心材料的熔點應至少高於外焊料層（例如，間隔物150B的第二層156或間隔物150C的焊料層166）的熔點約30℃至50℃。
在圖15中，導電連接件170形成於第一重佈線結構106上。導電連接件170接觸金屬化圖案110的暴露部分。在一些實施例中，如上文所提及，在形成導電連接件170之前，鈍化層142可用於金屬化圖案110上且經圖案化以暴露金屬化圖案110的一部分。亦如上文所提及，在一些實施例中，UBM可形成於金屬化圖案110的暴露部分上方。
在一些實施例中，諸如焊料膏或焊料襯墊的焊料材料（例如，圖30的焊料部分151）可經沈積或鍍覆於金屬化圖案110上，尤其在使用間隔物150A（其為實心球）的實施例中。焊料材料可在球安裝期間回焊以附接間隔物150。可使用球柵陣列封裝（ball grid array；BGA）製程來沈積導電連接件170及間隔物150。導電連接件170可包含導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者，或其組合。在一些實施例中，導電連接件170為藉由經由諸如蒸鍍、電鍍、列印、焊料轉移、植球或類似者的此類常用方法最初形成焊料層來形成的焊料連接件。在一個實施例中，可將間隔物150及用於導電連接件170的焊料以一形式按壓至金屬化圖案110（或UBM）的表面，且可進行回焊以便使材料成形為用於導電連接件170的所需凸塊形狀且將導電連接件170及間隔物150附接至金屬化圖案110。
附接導電連接件170的回焊亦可回焊安置於金屬化圖案110（或UBM）上的焊料材料，以用於諸如在間隔物150包含間隔物150A的情況下附接未包含任何焊料材料的間隔物150。在其他實施例中，回焊可使間隔物150的外焊料層（例如，間隔物150B的第二層156或間隔物150C的焊料層166）熔化以將間隔物150附接至金屬化圖案110（或UBM）。
在一些實施例中，若未已進行，則回焊亦可將元件140實體耦接且電性耦接至金屬化圖案110。亦可使用其他合適的製程。在一些實施例中，在形成導電連接件170且置放間隔物150之後，結構可經翻轉且置放於膠帶上或藉由間隔物150及導電連接件170固定，並單體化成晶粒。在其他實施例中，可在未將結構翻轉過來的情況下直接在膠帶上對封裝100進行單體化。
如圖15中所繪示，可將間隔物150置放於封裝100的角落處。將導電連接件170置放於其餘連接位置處。圖16示出圖15的封裝100的自上而下視圖，且示出具有間隔物150的連接件定位於角落處且導電連接件170定位於其他連接件處。
亦在圖15中所示出，在置放導電連接件170及具有間隔物150的連接件之後，可使封裝100自任何相鄰封裝單體化。因此，可同時形成對應於封裝100的若干封裝。藉由沿著例如對應於封裝100的區與第二封裝區（所述第二封裝區與封裝100相鄰）之間的切割道區鋸割來進行單體化製程275。所述鋸割使封裝100自相鄰第二封裝單體化。在一些實施例中，在將封裝基板300耦接至封裝100之後進行單體化製程275（下文論述）。
圖17類似於圖15，其中除根據一些實施例將間隔物150示出為置放於封裝100的邊緣的中心處之外，相似附圖標號標示使用相似製程形成的相似部件。在其他實施例中，間隔物150位於封裝的中心處且圖15中的視圖為封裝100的中間的剖面。圖18A示出圖17的封裝100的自上而下視圖。在圖18A中，間隔物150定位於列的中間處且定位於封裝100的相對側上。在一些實施例中，間隔物150可定位於全部四個邊緣上。在圖18B中，間隔物150定位於封裝100的中心處且未沿著封裝100的邊緣中的任一者。亦可對圖18A及圖18B的間隔物150的置放的佈局進行組合。可在形成具有間隔物150的連接件及導電連接件170之後進行諸如上文關於圖15所描述的單體化製程275。
圖19類似於圖15，其中除將間隔物150示出為置放於列中的全部連接件位置處之外，相似附圖標號標示使用相似製程形成的相似部件。圖20A示出間隔物150可置放於全部連接件位置處以用於封裝100的每一連接件。圖20B示出間隔物150可置放於封裝100的邊緣周圍的全部連接件位置處。應理解的是，可對間隔物150的此等佈局進行組合。可在形成具有間隔物150的連接件及導電連接件170之後進行諸如上文關於圖15所描述的單體化製程275。
圖21A、圖21B以及圖21C示出根據其他實施例的間隔物塊180A、間隔物塊180B以及間隔物塊180C（統稱為間隔物塊180，參見圖22）。間隔物塊180可以不同形狀形成。舉例而言，在圖21A中，間隔物塊180A為圓柱體（column）；在圖21B中，間隔物塊180B為經壓擠圓柱體或經擴展圓柱體；且在圖21C中，間隔物塊180C為立方體或長方體稜柱（rectangular prism）。預期可使用其他稜柱及形狀。間隔物塊180具有平坦上表面及平坦下表面，使得可使用取放製程來置放所述間隔物塊180。間隔物塊180A、間隔物塊180B或間隔物塊180C的尺寸可變化。圖21A、圖21B以及圖21C中所示出的尺寸中的每一者可為任何合適的尺寸。尺寸D1為間隔物塊180A的直徑，且尺寸D2為間隔物塊180A的高度。尺寸D3為間隔物塊180B的上表面處的間隔物塊180B的直徑。尺寸D4為間隔物塊180B的中心或最寬部分處的間隔物塊180B的直徑。尺寸D5為間隔物塊180B的高度。尺寸D6及尺寸D7分別為間隔物塊180C的深度及寬度，且尺寸D8為間隔物塊180C的高度。在一些實施例中，尺寸D1、尺寸D2、尺寸D3、尺寸D4、尺寸D5、尺寸D6、尺寸D7以及尺寸D8中的每一者可在約80微米與約1.5毫米的範圍內，諸如約200微米。尺寸D1、尺寸D2、尺寸D3或尺寸D4、尺寸D5、尺寸D6、尺寸D7以及尺寸D8中的每一者可各自彼此不同或可為相同的，或可為不同尺寸與相同尺寸的組合。然而，如圖21B中所示出，尺寸D4大於尺寸D3。在另一實施例中，尺寸D4可小於尺寸D3且所得形狀為變窄的圓柱體或沙漏形狀。在一個實施例中，間隔物塊180B可與間隔物塊180C組合以提供在中間處凸起的間隔物塊180。
間隔物塊180的材料可包含任何合適的材料，諸如金屬（例如，銅、銀、鋁等）、金屬合金、化合物、塑膠、陶瓷等等。類似於間隔物150，應選擇間隔物塊180的材料，使得其具有高於其他標準導電連接件的回焊溫度的更高熔點溫度。在一些實施例中，間隔物塊180可包含配置於間隔物塊180的核心材料上方及/或下方及/或周圍的焊料材料層。在一些實施例中，間隔物塊180可包含包圍間隔物塊180的核心材料的額外阻障層，所述阻障層類似於上文分別關於圖14B及圖14C的間隔物150B及/或間隔物150C所描述的阻障層。
在圖22中，使用取放製程在置放元件140（諸如上文關於圖13所描述）的同時定位間隔物塊180。亦如上文所提及，一些實施例可在金屬化圖案110的部分上使用經圖案化鈍化層142或UBM。諸如焊料膏或焊料襯墊的焊料材料（例如，圖37的上部焊料部分182）可經沈積或鍍覆於金屬化圖案110上，且可用於金屬化圖案110的待附接間隔物塊180及元件140（若存在）的部分上。在置放間隔物塊180及元件140之後，可進行焊料材料的回焊以將間隔物塊180及元件140實體耦接且電性耦接至金屬化圖案110。
在圖23中，導電連接件170可形成於金屬化圖案110的其餘部分上。導電連接件170可使用類似於上文關於圖15的導電連接件170所描述的製程及材料的製程及材料來形成。
如圖23中所繪示，可將間隔物塊180置放於封裝100的角落處。將導電連接件170置放於其餘連接位置中。可在形成具有間隔物塊180的連接件及導電連接件170之後進行諸如上文關於圖15所描述的單體化製程275。圖24示出圖23的封裝100的自上而下視圖，且示出定位於封裝100的角落處的具有間隔物塊180的連接件及定位於其他連接件中的導電連接件170。
圖25類似於圖23，其中除根據一些實施例將間隔物塊180示出為置放於封裝100的邊緣的中心處之外，相似附圖標號標示使用相似製程形成的相似部件。在其他實施例中，間隔物塊180位於封裝的中心處且圖25中的視圖為封裝100的中間的剖面。圖26A示出圖25的封裝100的自上而下視圖。在圖26A中，間隔物塊180定位於連接件列的中間處且定位於封裝100的相對側上。在一些實施例中，間隔物塊180可定位於全部四個邊緣上。在圖26B中，間隔物塊180定位於封裝100的中心處且未沿著封裝100的邊緣中的任一者。亦可對圖26A及圖26B的間隔物塊180的置放的佈局進行組合。可在形成具有間隔物塊180的連接件及導電連接件170之後進行諸如上文關於圖15所描述的單體化製程275。
圖27類似於圖23，其中除將間隔物塊180示出為置放於列中的全部連接件位置處之外，相似附圖標號標示使用相似製程形成的相似部件。圖28A示出間隔物塊180可置放於全部連接件位置處以用於封裝100的每一連接件。圖28B示出間隔物塊180可置放於封裝100的邊緣周圍的全部連接件位置處。應理解的是，可對間隔物塊180的此等佈局進行組合。可在形成具有間隔物塊180的連接件及導電連接件170之後進行諸如上文關於圖15所描述的單體化製程275。
在圖29中，可使用導電連接件170及使用間隔物150的連接件來將封裝100安裝至封裝基板300，以形成3D封裝400。如圖29中所示出，封裝100具有呈哭泣或皺眉形狀的翹曲。當將封裝100附接至封裝基板300時，定位於封裝100的角落處的間隔物150提供封裝100與封裝基板300之間的最小距離，使得導電連接件170未朝著彼此擴展過多從而導致橋接錯誤。
封裝基板300可為中介板、印刷電路板（printed circuit board；PCB）、另一封裝等等。封裝基板300可包含主動元件及被動元件（未繪示）。如所屬技術領域中具有通常知識者將認識到，可使用各種各樣元件（諸如電晶體、電容器、電阻器、此等的組合，以及類似者）來產生針對封裝基板300的設計的結構要求及功能要求。元件可使用任何合適的方法來形成。
封裝基板300亦可包含金屬化層及通孔（未繪示），以及金屬化層及通孔上方的接觸襯墊305。金屬化層可形成於主動元件及被動元件上方，且經設計以連接各種元件以形成功能電路。金屬化層可由介電質（例如，低k介電材料）與導電材料（例如，銅）的交替層形成，其中通孔內連導電材料層，且可經由任何合適的製程（諸如沈積、金屬鑲嵌、雙金屬鑲嵌，或類似者）來形成。在一些實施例中，封裝基板300實質上不含主動元件及被動元件。
導電連接件170經回焊以將封裝100附接至封裝基板300的接觸襯墊305。導電連接件170將封裝基板300（包含封裝基板300中的金屬化層）電性耦接及/或實體耦接至封裝100的第一重佈線結構106。當導電連接件170經回焊時，選擇回焊溫度以使得間隔物150的核心材料未經熔化。然而，亦附接間隔物150作為封裝100與封裝基板300之間的導電連接件。在圖30及圖31中放大且更詳細地示出圖29中的虛線框。
在一些實施例中，底部填充膠（未繪示）可形成於封裝100與封裝基板300之間且包圍導電連接件170及使用間隔物150的連接件。底部填充膠可在附接封裝100之後藉由毛細流動過程形成，或可在附接封裝100之前藉由合適的沈積方法形成。
亦可包含其他特徵及製程。舉例而言，可包含測試結構以輔助對3D封裝或3DIC元件的驗證測試。測試結構可包含例如形成於重佈線層中或基板上的測試襯墊，所述基板允許測試3D封裝或3DIC、使用探針及/或探針卡，以及類似者。可對中間結構以及最終結構進行驗證測試。另外，本文中所揭露的結構及方法可結合併入有對已知良好晶粒的中間驗證的測試方法來使用，以提高良率及降低成本。
在圖30至圖32中，根據一些實施例，示出具有間隔物150的連接的特寫（參見圖29的虛線框）。間隔物150可為間隔物150A、間隔物150B或間隔物150C（參見圖14A、圖14B以及圖14C）中的任一者。間隔物150可插入於兩個焊料部分151之間，所述焊料部分151將金屬化圖案110實體耦接且電性耦接至封裝基板300的接觸襯墊305。如圖30中所示出，焊料部分151可包圍間隔物150的一部分。因此，在一些實施例中，間隔物150的側壁可在不含焊料部分151的情況下暴露。在一些實施例中，兩個焊料部分151可接合在一起且完全包封間隔物150。
間隔物150可離金屬化圖案110與接觸襯墊305同樣遠，或可垂直地更靠近金屬化圖案110或垂直地更靠近接觸襯墊305。在一些實施例中，間隔物150與金屬化圖案110之間的距離D9可在約0微米與約400微米之間，且間隔物150與接觸襯墊305之間的距離D10可在約0微米與約400微米之間，但預期可使用其他距離。圖31示出距離D9及距離D10均為0微米的實施例。金屬化圖案110與接觸襯墊305之間的距離D11由間隔物150的直徑以及距離D9及距離D10來判定。D11的最小距離約與間隔物150的直徑相同。在一些實施例中，取決於間隔物150的材料，間隔物150可為可變形的，使得其的變形在0%與約50%之間（諸如約5%）。在此類實施例中，D11的最小距離為間隔物150的直徑的約50%至約100%。
在一些實施例中，用於焊料部分151的焊料材料可例如藉由經電鍍的焊料材料、印刷焊料膏、焊料襯墊等等來提供於接觸襯墊305及/或金屬化圖案110上。在一些實施例中，用於焊料部分151的焊料材料可來自於間隔物150。舉例而言，在間隔物150具有多個層（諸如上文關於間隔物150B及間隔物150C所描述）的情況下，間隔物150的外層可包含焊料材料。在一些實施例中，當在回焊導電連接件170的同時回焊間隔物150的外層的焊料材料時，可形成焊料部分151。在其他實施例中，可在將封裝100耦接至封裝基板300之前回焊間隔物150的外層的焊料材料，以將間隔物150耦接至金屬化圖案110。在此類實施例中，可首先形成間隔物150與金屬化圖案110之間的焊料部分151，隨後在回焊導電連接件170時形成間隔物150與接觸襯墊305之間的焊料部分151。
在圖32中，間隔物150被示出為焊料部分151自金屬化圖案110延伸至接觸襯墊305且包封間隔物150。圖32中的焊料部分151的組態可用於針對間隔物150的實施例中的任一者。特定而言，在間隔物150為非導電時使用圖32中的焊料部分151的組態，使得焊料部分151提供自金屬化圖案110至接觸襯墊305的導電。距離D9、距離D10以及距離D11可如上文關於圖30所描述。
在圖33中，可使用導電連接件170及使用間隔物150的連接件來將封裝100安裝至封裝基板300，以形成3D封裝400。如圖33中所示出，封裝100具有呈微笑形狀的翹曲。當將封裝100附接至封裝基板300時，定位於封裝100的邊緣的中間處（參見圖18A）或封裝100的中間處（參見圖18B）的間隔物150提供封裝100與封裝基板300之間的最小距離，使得導電連接件170未朝著彼此擴展過多從而導致橋接錯誤。
在圖34中，可使用具有間隔物150的連接件（在一些實施例中，及導電連接件170）來將封裝100安裝至封裝基板300，以形成3D封裝400。如圖34中所示出，封裝100具有呈哭泣或皺眉形狀的翹曲，但封裝100也可為具有微笑形狀。當將封裝100附接至封裝基板300時，定位於封裝100的連接件位置中的每一者處（參見圖20A）或沿著封裝100的每一邊緣（參見圖20B）的間隔物150提供封裝100與封裝基板300之間的最小距離。在與圖20B中所示出的實施例一致的實施例的情況下，最小距離防止導電連接件170朝著彼此擴展過多，所述擴展過多將導致橋接錯誤。
圖35示出根據一些實施例的具有間隔物150（其位於圖34的虛線框中）的連接件的放大視圖。在將間隔物150用於位於遠離封裝基板300翹曲的封裝100的區域中的連接件中的情況下，間隔物150可能不接觸封裝100及封裝基板300兩者。換言之，距離D11大於間隔物150的直徑。距離D9及距離D10可各自在約0微米與約400微米之間的範圍內，但其可不都為0微米。預期可使用其他尺寸。
在圖36中，可使用導電連接件170及使用間隔物塊180的連接件來將封裝100安裝至封裝基板300，以形成3D封裝400。如圖36中所示出，封裝100具有呈哭泣或皺眉形狀的翹曲。當將封裝100附接至封裝基板300時，定位於封裝100的角落處的間隔物塊180提供封裝100與封裝基板300之間的最小距離，使得導電連接件170未朝著彼此擴展過多從而導致橋接錯誤。
在圖37至圖38中，根據一些實施例，示出具有間隔物塊180的連接的特寫（參見圖36的虛線框）。儘管示出間隔物塊180B（參見圖21B），但間隔物塊180可為間隔物塊180A、間隔物塊180B或間隔物塊180C（參見圖21、圖21B以及圖21C）中的任一者。在圖37中，間隔物塊180可插入於上部焊料部分182與下部焊料部分184之間，所述上部焊料部分182及下部焊料部分184將金屬化圖案110實體耦接且電性耦接至封裝基板300的接觸襯墊305。在一些實施例中，例如藉由經電鍍的焊料材料、印刷焊料膏、焊料襯墊等等，用於上部焊料部分182的材料可提供於金屬化圖案110上，且用於下部焊料部分184的材料可提供於接觸襯墊305上。在其他實施例中，在將間隔物塊180置放於金屬化圖案110上（參見圖22）之前，可將用於上部焊料部分182或用於下部焊料部分184的材料提供於間隔物塊180上。距離D9、距離D10以及距離D11類似於圖30的距離9、距離D10以及距離D11。
在圖38中，示出類似於間隔物塊180A或間隔物塊180B（分別參見圖21A及圖21C）的具有筆直側壁的間隔物塊180。
在圖39A及圖39B中，示出沿著圖38的平面A-A的間隔物塊180的剖面視圖。在圖39A中，所示出的間隔物塊180與圖21C的間隔物塊180C一致。在圖39B中，所示出的間隔物塊180與圖21A的間隔物塊180A或圖21B的間隔物塊180B一致。在圖39A中，虛線輪廓表示上部焊料部分182及/或下部焊料部分184的輪廓的投影。如圖39A中所見，上部焊料部分182及/或下部焊料部分184的輪廓可具有圓形側面（rounded sides）。如圖39B中所見，上部焊料部分182及/或下部焊料部分184的輪廓為圓形。
在圖40中，可使用導電連接件170及使用間隔物塊180的連接件來將封裝100安裝至封裝基板300，以形成3D封裝400。如圖36中所示出，封裝100具有呈微笑形狀的翹曲。當將封裝100附接至封裝基板300時，定位於封裝100的邊緣的中間處（參見圖26A）或封裝100的中間處（參見圖26B）的間隔物塊180提供封裝100與封裝基板300之間的最小距離，使得導電連接件170未朝著彼此擴展過多從而導致橋接錯誤。
在圖41中，可使用具有間隔物塊180的連接件（在一些實施例中，及導電連接件170）來將封裝100安裝至封裝基板300，以形成3D封裝400。如圖41中所示出，封裝100具有呈哭泣或皺眉形狀的翹曲，但封裝100也可為具有微笑形狀。當將封裝100附接至封裝基板300時，定位於封裝100的連接件位置中的每一者處（參見圖28A）或沿著封裝100的每一邊緣（參見圖28B）的間隔物塊180提供封裝100與封裝基板300之間的最小距離。在與圖28B中所示出的實施例一致的實施例的情況下，最小距離防止導電連接件170朝著彼此擴展過多，所述擴展過多將導致橋接錯誤。
圖42示出根據一些實施例的具有間隔物塊180（其位於圖41的虛線框中）的連接件的放大視圖。在將間隔物塊180用於位於遠離封裝基板300翹曲的封裝100的區域中的連接件中的情況下，距離D9及/或距離D10可比位於朝向封裝基板300翹曲的封裝100的區域中的連接件中更大。在將封裝100按壓至封裝基板300且回焊上部焊料部分182及下部焊料部分184之後，上部焊料部分182及/或下部焊料部分184的寬度可往側邊內縮，形成沙漏形狀。
實施例在封裝與另一基板之間的某些連接件中設置間隔物球或間隔物塊。此等間隔物維持封裝與基板之間的最小距離，使得封裝中的翹曲不導致連接件中的連接件橋接，在所述橋接中，翹曲導致封裝與基板之間的距離過小，使得連接件因擠壓及過寬變形而與另一連接件橋接。此等間隔物可由若干不同類型的材料製成且為導電或非導電的。間隔物球可藉由焊料整個或部分地包圍。間隔物塊可使用焊料來附接。間隔物塊可使用取放製程來定位於封裝上。間隔物球可使用球柵陣列形成製程來定位於封裝上。因此，封裝接合更不易出錯且接合製程可使用翹曲封裝，所述翹曲封裝的翹曲大於通常將允許的容許度。
在一個實施例中一種封裝包括第一封裝，所述第一封裝包含嵌入式晶粒及重佈線結構。第一連接件附接至重佈線結構，所述第一連接件包括嵌入於所述第一連接件中的間隔物。第二連接件附接至所述重佈線結構，所述第二連接件不含所述間隔物。所述間隔物的材料具有第一回焊溫度，所述第二連接件具有第二回焊溫度，且所述第一回焊溫度大於所述第二回焊溫度。所述封裝亦包括第二封裝，所述第一連接件及所述第二連接件將所述第一封裝電性耦接且實體耦接至所述第二封裝。在實施例中，所述第一連接件配置於所述第一封裝的角落處。在實施例中，所述間隔物為球形。在實施例中，所述間隔物具有平坦上表面及平坦下表面。在實施例中，所述間隔物包括由一或多個額外層包圍的核心材料。在實施例中，所述第一連接件更包括：第一焊料材料，配置於所述間隔物與所述第一封裝的第一接觸件之間；以及第二焊料材料，配置於所述間隔物與所述第二封裝的第二接觸件之間，其中所述間隔物的一部分不含所述第一焊料材料且不含所述第二焊料材料。在實施例中，所述第一連接件處的所述第一封裝與所述第二封裝之間的第一距離小於所述第二連接件處的所述第一封裝與所述第二封裝之間的第二距離。在實施例中，所述第一封裝為翹曲的。
在另一實施例中一種封裝包括第一封裝，所述第一封裝包括插入於第一重佈線結構與封裝封蓋之間的嵌入式晶粒，所述第一重佈線結構具有位於所述第一重佈線結構的前側處的第一接觸件區及第二接觸件區。第一連接件配置於所述第一封裝的第一接觸件區上，所述第一連接件各自包含嵌入於焊料材料中的間隔物。第二連接件配置於所述第一封裝的第二接觸件區上，所述第二連接件各自包含所述焊料材料。所述焊料材料具有低於所述間隔物的材料的回焊溫度的回焊溫度。在實施例中，所述第一連接件配置於一列第一連接件及第二連接件的中間處。在實施例中，所述間隔物包封於所述焊料材料內。在實施例中，所述間隔物具有平坦上表面及平坦下表面。在實施例中，所述間隔物包含：球形塑膠核心；以及導電材料層，包圍所述球形塑膠核心，所述導電材料層具有高於所述焊料材料的所述回焊溫度的回焊溫度。在實施例中，所述第一連接件的最上表面及所述第二連接件的最上表面歸因於所述第一封裝中的翹曲而不在同個水平（not level）。在實施例中，所述第一封裝更包括配置於所述第一封裝的表面處的表面安裝元件（surface mount device），且所述表面安裝元件配置於所述第一連接件及所述第二連接件之間。
在另一實施例中，一種形成封裝的方法包括：將第一連接件配置於第一封裝的前側上，所述第一連接件包含間隔物；以及將第二連接件配置於所述第一封裝的所述前側上，所述第二連接件不含所述間隔物。使所述第一封裝對準至封裝基板。回焊所述第一連接件及所述第二連接件以將所述第一封裝實體耦接且電性耦接至所述封裝基板，所述間隔物在所述回焊期間維持其形狀，所述間隔物在所述回焊期間提供所述第一連接件處的所述第一封裝與所述封裝基板之間的最小距離，其中所述最小距離對應於所述間隔物的高度。在實施例中，配置所述第一連接件包含：使用取放製程（pick and place process）來將所述間隔物定位於所述第一封裝的接觸件上；以及回焊焊料材料以將所述間隔物附接至所述第一封裝。在實施例中，配置所述第二連接件包含：進行球柵形成製程（ball grid formation process）以將焊料球定位於所述第一封裝的接觸件上；以及回焊所述焊料球以將所述焊料球附接至所述第一封裝，其中配置所述第一連接件與配置所述第二連接件同時發生。在實施例中，所述間隔物為球形。在實施例中，所述間隔物的第一材料包含金屬、金屬合金、塑膠或陶瓷，且其中所述間隔物的所述第一材料具有高於所述第二連接件的第二材料的熔點。
前文概述若干實施例的特徵，使得所屬技術領域中具有通常知識者可更好地理解本揭露內容的態樣。所屬技術領域中具有通常知識者應瞭解，其可易於使用本揭露內容作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。所屬技術領域中具有通常知識者亦應認識到，此類等效構造並不脫離本揭露內容的精神及範圍，且所屬技術領域中具有通常知識者可在不脫離本揭露內容的精神及範圍的情況下在本文中作出各種改變、替代以及更改。
52:半導體基板 54、140:元件 56:層間介電質 58:導電插塞 60:內連線結構 62:襯墊 64:鈍化膜 66:晶粒連接件 68:介電層 100:積體扇出封裝 102:載板 104:釋放層 105A:第一區 105B:第二區 106:第一重佈線結構 108、112、116、120:介電層 110、114、118:金屬化圖案 12:球下金屬 122p:導電柱 122s:肩部 124:積體電路晶粒 128、170、226:導電連接件 130:底部填充膠 134:包封體 142:鈍化層 150、150A、150B、150C:間隔物 151:焊料部分 152、158:實心中心核心 154:第一層 156:第二層 160:第一阻障層 162、206、213:導電層 164:第二阻障層 166:焊料層 168:經摻雜子層 180、180A、180B、180C:間隔物塊 182:上部焊料部分 184:下部焊料部分 200:封蓋 210:基板核心 216:導通孔 224:阻焊劑 250:散熱器 252:上部封蓋 254:環 255、260:熱黏著劑 275:單體化製程 300:封裝基板 305:接觸襯墊 400:3D封裝 A-A:平面 D1、D2、D3、D4、D5、D6、D7、D8:尺寸 H1 、H2 :高度 W1 、W2 、W3 、W4 :寬度 D9、D10、D11:距離
結合隨附圖式閱讀以下實施方式時會最佳地理解本揭露內容的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，為論述清楚起見，可任意增大或減小各種特徵的尺寸。 圖1至圖28A以及圖28B示出根據一些實施例的在形成積體扇出封裝的製程中的各種中間步驟。 圖29至圖42示出在使用嵌入於一些連接件中的間隔物來將積體扇出封裝附接至封裝基板的製程中的各種中間步驟。
66:晶粒連接件
100:積體扇出封裝
105A:第一區
105B:第二區
106:第一重佈線結構
122:球下金屬
124:積體電路晶粒
128、170:導電連接件
130:底部填充膠
140:元件
150:間隔物
250:散熱器
252:上部封蓋
254:環
255、260:熱黏著劑
300:封裝基板
305:接觸襯墊
400:3D封裝

Claims (20)

  1. 一種封裝，包括： 第一封裝，所述第一封裝包括嵌入式晶粒及重佈線結構； 第一連接件，附接至所述重佈線結構，所述第一連接件包括嵌入於所述第一連接件中的間隔物； 第二連接件，附接至所述重佈線結構，所述第二連接件不含所述間隔物，其中所述間隔物的材料具有第一回焊溫度，所述第二連接件具有第二回焊溫度，且所述第一回焊溫度大於所述第二回焊溫度；以及 第二封裝，所述第一連接件及所述第二連接件將所述第一封裝電性耦接且實體耦接至所述第二封裝。
  2. 如請求項1所述的封裝，其中所述第一連接件配置於所述第一封裝的角落處。
  3. 如請求項1所述的封裝，其中所述間隔物為球形。
  4. 如請求項1所述的封裝，其中所述間隔物具有平坦上表面及平坦下表面。
  5. 如請求項1所述的封裝，其中所述間隔物包括由一或多個額外層包圍的核心材料。
  6. 如請求項1所述的封裝，其中所述第一連接件更包括：第一焊料材料，配置於所述間隔物與所述第一封裝的第一接觸件之間；以及第二焊料材料，配置於所述間隔物與所述第二封裝的第二接觸件之間，其中所述間隔物的一部分不含所述第一焊料材料且不含所述第二焊料材料。
  7. 如請求項1所述的封裝，其中所述第一連接件處的所述第一封裝與所述第二封裝之間的第一距離小於所述第二連接件處的所述第一封裝與所述第二封裝之間的第二距離。
  8. 如請求項1所述的封裝，其中所述第一封裝為翹曲的。
  9. 一種封裝，包括： 第一封裝，所述第一封裝包括插入於第一重佈線結構與封裝封蓋之間的嵌入式晶粒，所述第一重佈線結構具有位於所述第一重佈線結構的前側處的第一接觸件區及第二接觸件區； 第一連接件，配置於所述第一封裝的第一接觸件區上，所述第一連接件各自包含嵌入於焊料材料中的間隔物；以及 第二連接件，配置於所述第一封裝的第二接觸件區上，所述第二連接件各自包含所述焊料材料，所述焊料材料具有低於所述間隔物的材料的回焊溫度的回焊溫度。
  10. 如請求項9所述的封裝，其中所述第一連接件配置於一列第一連接件及第二連接件的中間處。
  11. 如請求項9所述的封裝，其中所述間隔物包封於所述焊料材料內。
  12. 如請求項9所述的封裝，其中所述間隔物具有平坦上表面及平坦下表面。
  13. 如請求項9所述的封裝，其中所述間隔物包括： 球形塑膠核心；以及 導電材料層，包圍所述球形塑膠核心，所述導電材料層具有高於所述焊料材料的所述回焊溫度的回焊溫度。
  14. 如請求項9所述的封裝，其中所述第一連接件的最上表面及所述第二連接件的最上表面歸因於所述第一封裝中的翹曲而不在同個水平（not level）。
  15. 如請求項9所述的封裝，其中所述第一封裝更包括配置於所述第一封裝元件的表面處的表面安裝元件（surface mount device），且所述表面安裝元件配置於所述第一連接件及所述第二連接件之間。
  16. 一種形成封裝的方法，包括： 將第一連接件配置於第一封裝的前側上，所述第一連接件包括間隔物； 將第二連接件配置於所述第一封裝的所述前側上，所述第二連接件不含所述間隔物； 使所述第一封裝對準至封裝基板；以及 回焊所述第一連接件及所述第二連接件以將所述第一封裝實體耦接且電性耦接至所述封裝基板，所述間隔物在所述回焊期間維持其形狀，所述間隔物在所述回焊期間提供所述第一連接件處的所述第一封裝與所述封裝基板之間的最小距離，其中所述最小距離對應於所述間隔物的高度。
  17. 如請求項16所述形成封裝的方法，其中配置所述第一連接件包括：使用取放製程（pick and place process）來將所述間隔物定位於所述第一封裝的接觸件上；以及回焊焊料材料以將所述間隔物附接至所述第一封裝。
  18. 如請求項16所述形成封裝的方法，其中配置所述第二連接件包括：進行球柵形成製程（ball grid formation process）以將焊料球定位於所述第一封裝的接觸件上；以及回焊所述焊料球以將所述焊料球附接至所述第一封裝，其中配置所述第一連接件與配置所述第二連接件同時發生。
  19. 如請求項16所述形成封裝的方法，其中所述間隔物為球形。
  20. 如請求項16所述形成封裝的方法，其中所述間隔物的第一材料包括金屬、金屬合金、塑膠或陶瓷，且其中所述間隔物的所述第一材料具有高於所述第二連接件的第二材料的熔點。
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