CN112397475A - 具有微细间距硅穿孔封装的扇出型封装晶片结构及单元 - Google Patents

具有微细间距硅穿孔封装的扇出型封装晶片结构及单元 Download PDF

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CN112397475A
CN112397475A CN201910875550.0A CN201910875550A CN112397475A CN 112397475 A CN112397475 A CN 112397475A CN 201910875550 A CN201910875550 A CN 201910875550A CN 112397475 A CN112397475 A CN 112397475A
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fan
package
silicon
unit
substrate
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蔡佩君
徐宏欣
张简上煜
林南君
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Powertech Technology Inc
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Powertech Technology Inc
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Abstract

本发明提供一种具有微细间距硅穿孔封装的扇出型封装晶片结构及单元。该具有微细间距硅穿孔封装的扇出型封装晶片结构将硅工艺的硅中介层设置于下层的封装单元内，作为上层的封装单元与底层的基板之间的电连接。依据上层封装单元的扇出接点的设计分布，以一个或多个局部配置硅中介层于下层封装单元的半导体晶粒侧边，可满足对于高阶晶片更不受限制的设计需求。

Description

具有微细间距硅穿孔封装的扇出型封装晶片结构及单元
技术领域
本发明有关一种封装结构，尤指一种具有微细间距硅穿孔封装的扇出型封装晶片结构及单元。
背景技术
目前因应高阶晶片的需求量大增，与其对小面积、高输出(I/O)、高散热、低噪声等特性的产品需求，后段封装工艺不断朝向缩小晶片体积或在同等晶片面积内整合更多功能以提高I/O数量的方向发展。随着功能增强、尺寸小型化的需求，高I/O脚数及缩小晶粒焊垫尺寸与间距(pitch)的设计，已成为IC发展的趋势。
对于常见的多层封装架构，目前使用铜柱(copper pillar)作为下层封装结构与上层封装结构之间的连接。由于连接铜柱的高度与晶片封装结构的厚度直接相关，在考虑高阶晶片的散热、噪声控制等条件限制下，晶片封装结构必须维持在一定的厚度以上，因此铜柱也具有一定的高度。目前普遍的封装工艺先长出铜柱再进行封胶，当铜柱较高时，在设计上也需加大铜柱的直径，以维持铜柱结构的稳定性。然而铜柱直径加大直接影响到I/O脚的间距、I/O脚数，使上层封装结构的能力遭到限制。
简言之，晶片的厚度决定了铜柱的高度，也限制了间距有其极限无法无止境缩小，也使得扇出型封装架构的扇出接点、I/O数量以及上层封装架构的工艺与设计都受到限制。
发明内容
为了解决上述问题，本发明的实施例中提供了具有微细间距硅穿孔封装的扇出型封装晶片结构以及扇出型封装单元。
根据本发明的一实施例，具有微细间距硅穿孔封装的扇出型封装晶片结构设置于一基板上，该扇出型封装晶片结构包含了一第一封装单元以及一第二封装单元。该第一封装单元具有一半导体晶粒以及一硅中介层，该半导体晶粒以及该硅中介层嵌入封装于一封胶体中，该第一封装单元具有彼此相对的一下表面以及一上表面。该第二封装单元设置于该第一封装单元的该上表面上。该第一封装单元以该下表面设置于该基板上，其中该半导体晶粒的多个接点电连接于该基板上，该第二封装单元的多个接点通过该硅中介层电连接于该基板上。
根据本发明的另一实施例，具有微细间距硅穿孔封装的扇出型封装单元设置于一基板上，该扇出型封装单元具有一半导体晶粒以及一硅中介层，该半导体晶粒以及该硅中介层嵌入封装于一封胶体中，该扇出型封装单元具有彼此相对的一下表面以及一上表面，该扇出型封装单元以该下表面设置于该基板上，且该半导体晶粒的多个接点电连接于该基板上。
于本发明实施例所提供的扇出型封装晶片结构中，其中该硅中介层以硅穿孔封装贯穿该第一封装单元，电连接该基板与该第二封装单元。
于本发明实施例所提供的扇出型封装晶片结构中，其中该硅中介层局部设置于该半导体晶粒一侧。
于本发明实施例所提供的扇出型封装晶片结构中，其中该半导体晶粒以及该硅中介层彼此相邻且位于同一封装层中。
于本发明实施例所提供的扇出型封装晶片结构中，其中该硅中介层包含一条或多条连接线路，通过一个或多个对应的接触垫连接该第二封装单元与该基板。
于本发明实施例所提供的扇出型封装晶片结构中，其中该硅中介层于封胶前以硅工艺形成。
于本发明实施例中，该扇出型封装晶片结构中另包含至少一重布线层，设置于该第一封装单元的该下表面与该基板之间，该至少一重布线层包含多个接触垫，该半导体晶粒的该多个接点以及该第二封装单元的多个接点通过该硅中介层由该多个接触垫电连接于该基板上。
通过本发明的扇出型封装晶片结构，以具有微细间距的硅中介层进行硅穿孔封装，使上层封装结构的单位面积积集度以及可设计I/O数大幅增加，因此在相同单位晶片面积中涵括的功能能够大幅提升。
附图说明
图1为本发明封装晶片结构中第一封装单元的一实施例的示意图。
图2为封装晶片结构中第一封装单元以及第二封装单元的一实施例的示意图。
图3为本发明具有微细间距硅穿孔封装的扇出型封装晶片结构设置于一基板上的示意图。
附图标号
1 扇出型封装晶片结构
10 第一封装单元
11 半导体晶粒
12 硅中介层
13 封胶体
14、15 焊球
18 下表面
19 上表面
20 第二封装单元
21、111 接点
30 重布线层
100 基板
121 连接线路
122、123、31 接触垫
具体实施方式
在说明书及后续的申请专利范围当中使用了某些词汇来指称特定的元件。所属领域中相关技术人员应可理解，制造商可能会用不同的名词来称呼同一个元件。本说明书及后续的申请专利范围并不以名称的差异来作为区分元件的方式，而是以元件在功能上的差异来作为区分的准则。在通篇说明书及后续的权利要求当中所提及的“包含”为一开放式的用语，故应解释成“包含但不限定于”。此外，“耦接”或“连接”一词在此包含任何直接及间接的电气或结构连接手段。因此，若文中描述一第一装置耦接/连接于一第二装置，则代表该第一装置可直接电气/结构连接于该第二装置，或通过其他装置或连接手段间接地电气/结构连接至该第二装置。
请参考图1以及图2，图1为本发明的封装晶片结构中第一封装单元的一实施例的示意图，图2为封装晶片结构中第一封装单元以及第二封装单元的一实施例的示意图。本发明所提供的具有微细间距硅穿孔封装的扇出型封装晶片结构1在扇出型(fan out)的封装架构中，针对双层或多层层叠的立体架构，以硅工艺的硅中介层取代层间封装的部分或全部铜柱连结。于图1中，第一封装单元10具有至少一半导体晶粒11以及至少一硅中介层12(Si interposer)。于本发明的其他实施例中，第一封装单元10也可包含一个或多个同质或异质的半导体晶粒11，以及一个或多个局部设置于半导体晶粒11一侧或外围的硅中介层12，并且于接续的封胶(molding)工艺中，半导体晶粒11以及硅中介层12嵌入封装于同一封胶体13中。换言之，本发明的硅中介层12与半导体晶粒11彼此相邻并且位于同一封装层中。
封胶后的第一封装单元10具有彼此相对的一下表面18以及一上表面19，第二封装单元20(或上层封装单元)则层叠设置于第一封装单元10(自身为扇出型封装单元)的上表面19上。于其他实施例中，也可在第二封装单元20上另外层叠设置其他的封装单元，并且同样通过硅中介层作层间的局部或全部连结，本发明并不以图示以及说明中的实施例为限。硅中介层12以硅穿孔(through silicion via,TSV)封装贯穿第一封装单元10。
请一并参考图3，图3为本发明具有微细间距硅穿孔封装的扇出型封装晶片结构设置于一基板上的示意图。第一封装单元10以下表面18设置于基板100上。设置于半导体晶粒11同一层一侧的硅中介层12则用来电连接第二封装单元20与基板100。以硅工艺形成的硅中介层12可具有极小间距以及线宽的一条或多条连接线路121，并且通过一个或多个对应的接触垫123、122以及焊球14、15分别连接上层的第二封装单元20以及下层的基板100，使层叠设置于第一封装单元10上的第二封装单元20的多个接点21通过硅中介层12电连接于基板100上。另外，第一封装单元10的半导体晶粒11的多个接点111亦电连接于基板100上。
由于第二封装单元20以硅中介层12与基板100连接，因此在第二封装单元20的扇出区的接点间距、I/O数量，以及连带其所可承担的封装架构工艺与设计可突破传统铜柱连接的限制，也就是说，第二封装单元20的多个扇出接点21可以依据第二封装单元20中的晶粒(亦可包含一个或多个同质或异质半导体晶粒)设计需求，进行极微细间距(例如小于150um，较佳地小于75um的间距)的设计。
请继续参考图3。扇出型封装晶片结构1另可包含一个或多个重布线层30(RDL)，设置于第一封装单元10的下表面18与基板100之间。一个或多个重布线层30包含多个接触垫31，而第一封装单元10的半导体晶粒11的多个接点111以及第二封装单元20的多个接点21通过硅中介层12由多个接触垫31电连接于基板100上。
本发明的实施例所揭露的扇出型封装晶片结构以及扇出型封装单元，将硅工艺的硅中介层设置于下层的封装单元内，作为上层的封装单元与底层的基板之间的电连接。依据上层封装单元的扇出接点的设计分布，以一个或多个局部配置硅中介层于下层封装单元的半导体晶粒侧边，可满足对于高阶晶片更不受限制的设计需求。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (15)

1.一种具有微细间距硅穿孔封装的扇出型封装晶片结构，设置于一基板上，其特征在于，该扇出型封装晶片结构包含有：
一第一封装单元，具有一半导体晶粒以及一硅中介层，该半导体晶粒以及该硅中介层嵌入封装于一封胶体中，该第一封装单元具有彼此相对的一下表面以及一上表面；以及
一第二封装单元，设置于该第一封装单元的该上表面上；
其中该第一封装单元以该下表面设置于该基板上，其中该半导体晶粒的多个接点电连接于该基板上，该第二封装单元的多个接点通过该硅中介层电连接于该基板上。
2.如权利要求1所述的扇出型封装晶片结构，其特征在于，该硅中介层以硅穿孔封装贯穿该第一封装单元，电连接该基板与该第二封装单元。
3.如权利要求1所述的扇出型封装晶片结构，其特征在于，该硅中介层局部设置于该半导体晶粒一侧。
4.如权利要求1所述的扇出型封装晶片结构，其特征在于，该半导体晶粒以及该硅中介层彼此相邻且位于同一封装层中。
5.如权利要求1所述的扇出型封装晶片结构，其特征在于，该硅中介层包含一条或多条连接线路，通过一个或多个对应的接触垫连接该第二封装单元与该基板。
6.如权利要求1所述的扇出型封装晶片结构，其特征在于，该硅中介层于封胶前以硅工艺形成。
7.如权利要求1所述的扇出型封装晶片结构，其特征在于，另包含至少一重布线层，设置于该第一封装单元的该下表面与该基板之间，该至少一重布线层包含多个接触垫，该半导体晶粒的该多个接点以及该第二封装单元的多个接点通过该硅中介层由该多个接触垫电连接于该基板上。
8.一种具有微细间距硅穿孔封装的扇出型封装单元，设置于一基板上，其特征在于，该扇出型封装单元具有一半导体晶粒以及一硅中介层，该半导体晶粒以及该硅中介层嵌入封装于一封胶体中，该扇出型封装单元具有彼此相对的一下表面以及一上表面，该扇出型封装单元以该下表面设置于该基板上，且该半导体晶粒的多个接点电连接于该基板上。
9.如权利要求8所述的扇出型封装单元，其特征在于，一上层封装单元设置于该扇出型封装单元的该上表面上，该上层封装单元的多个接点通过该硅中介层电连接于该基板上。
10.如权利要求9所述的扇出型封装单元，其特征在于，该硅中介层以硅穿孔封装贯穿该扇出型封装单元，电连接该基板与该上层封装单元。
11.如权利要求8所述的扇出型封装单元，其特征在于，该硅中介层局部设置于该半导体晶粒一侧。
12.如权利要求8所述的扇出型封装单元，其特征在于，该半导体晶粒以及该硅中介层彼此相邻且位于同一封装层中。
13.如权利要求8所述的扇出型封装单元，其特征在于，该硅中介层包含一条或多条连接线路。
14.如权利要求8所述的扇出型封装单元，其特征在于，该硅中介层于封胶前以硅工艺形成。
15.如权利要求8所述的扇出型封装单元，其特征在于，另包含至少一重布线层，设置于该下表面与该基板之间，该至少一重布线层包含多个接触垫，该半导体晶粒的该多个接点由该多个接触垫电连接于该基板上。
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