CN212342601U - 一种多芯片超薄扇出型封装结构 - Google Patents

一种多芯片超薄扇出型封装结构 Download PDF

Info

Publication number
CN212342601U
CN212342601U CN202022259453.XU CN202022259453U CN212342601U CN 212342601 U CN212342601 U CN 212342601U CN 202022259453 U CN202022259453 U CN 202022259453U CN 212342601 U CN212342601 U CN 212342601U
Authority
CN
China
Prior art keywords
chip
metal
layer
rewiring
circuit layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202022259453.XU
Other languages
English (en)
Inventor
胡正勋
梁新夫
郭洪岩
刘爽
夏剑
张朝云
徐东平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changdian Integrated Circuit Shaoxing Co ltd
Original Assignee
Changdian Integrated Circuit Shaoxing Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changdian Integrated Circuit Shaoxing Co ltd filed Critical Changdian Integrated Circuit Shaoxing Co ltd
Priority to CN202022259453.XU priority Critical patent/CN212342601U/zh
Application granted granted Critical
Publication of CN212342601U publication Critical patent/CN212342601U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本实用新型公开了一种多芯片超薄扇出型封装结构,属于半导体封装技术领域。其再布线金属线路层(3)的上表面设置上层金属焊盘(31)、下表面设置底层金属焊盘(33),芯片(8)通过金属微凸块(73)与再布线金属线路层(3)的上层金属焊盘(31)固连,底填胶(83)填充同一封装体的芯片(8)的底部和芯片间隙,所述塑封料(86)于再布线金属层(3)上方塑封芯片(8),并露出芯片(8)的背面;所述加强散热保护层(63)通过导热粘合层(61)设置在芯片(8)的背面。本实用新型实现了减薄产品厚度、提高了产品可靠性并实现了多芯片封装结构。

Description

一种多芯片超薄扇出型封装结构
技术领域
本实用新型涉及一种多芯片超薄扇出型封装结构,属于半导体封装技术领域。
背景技术
伴随电子产业发展,藉由芯片内晶体管特征尺寸的缩小,芯片内晶体管数量呈几何级增长的背景下,高性能芯片越来越向高I/O数发展。
传统的倒装芯片封装方案中,I/O连接端子散布在芯片表面面积之内,从而限制了I/O连接数目。
扇出型封装通过再布线技术,将I/O从芯片内引到芯片外,将高密度的I/O扇出为低密度的封装引脚,解决了封装芯片与印刷线路板能够形成互连的问题,同时封装厚度可以大幅降低,有利于集成在空间日益紧张的移动终端等应用场景中,因其高集成度与互联性能好等优点,因此正在迅速成为超薄多芯片封装的选择。
扇出型封装通常将裸芯片的背面先嵌入在环氧树脂中,然后在裸芯片的正面形成介电层和重布线层,并在裸芯片正面的焊盘与重布线层之间形成电连接,重布线层可重新规划从裸芯片上的I/O连接到外围环氧树脂区域的路线,再在重布线层的焊盘上形成焊球突起结构,由此形成扇出型封装结构。该方法存在着一定的缺陷,因注塑封装材料收缩引起的滑移也很难得到控制;且采用注塑工艺的扇出型封装在翘曲控制方面非常困难,随着封装体厚度的减少,翘曲增加后在封装体转接到基板后,加装散热模块时,多芯片之间区域线条因此产生形变,大大影响了芯片互联精度,最终影响产品封装的可靠性,降低了产品性能;增加封装体厚度,又丧失了薄型封装的优点。
发明内容
本实用新型的目的在于克服当前超薄型扇出型芯片封装结构强度的不足,提供一种提高产品可靠性、实现多芯片封装的、带有加强结构的集成散热结构的多芯片超薄扇出型封装结构。
本实用新型的目的是这样实现的:
本实用新型提供了一种多芯片超薄扇出型封装结构,其包括若干个芯片、再布线金属线路层、加强散热保护层、底填胶和塑封料,所述再布线金属线路层的上表面设置上层金属焊盘、下表面设置底层金属焊盘,所述芯片的芯片焊盘带有金属微凸块,所述芯片通过金属微凸块、焊锡料与再布线金属线路层的上层金属焊盘固连,
所述底填胶填充芯片的底部和芯片间隙,所述塑封料于再布线金属线路层上方塑封芯片,并露出芯片的背面;
所述加强散热保护层通过导热粘合层设置在芯片的背面,所述加强散热保护层为硅片、玻璃片或金属片中的一种或几种组合;
所述再布线金属线路层的底层金属焊盘设置金属连接件。
进一步地,所述金属微凸块的顶端还包括镍层和金层,所述金层覆盖镍层之上。
进一步地,所述再布线金属线路层的上层金属焊盘的顶端还包括铜层和镍层,所述镍层覆盖铜层之上。
进一步地,所述金属连接件为铜柱、金属扩散层或锡球。
进一步地,所述金属片为金属硒散热片或金属薄铜片。
有益效果
1、本实用新型通过圆片级再布线金属线路层技术和芯片倒装技术实现单层或多层的扇出封装结构,以确保待封装芯片尤其是高引脚数的小芯片或超小芯片与印刷线路板能够实现高密度的I/O扇出为低密度的封装引脚,不需要基板、插入件或底部填充,减薄了整个封装结构;
2、本实用新型采用塑封材料将待封装芯片嵌入在其中,使待封装芯片的前后左右四个面及背面均得到物理和电气保护,提高了封装产品的可靠性;
3、本实用新型利用封装体背面散热结构,同时作为加强结构的加强板不仅进一步加强了包封体的强度,减小了整个封装结构的翘曲度,而且加强了芯片单体的散热性能,有助于提高封装产品的可靠性;
4、本实用新型提供一种提高产品可靠性、实现多芯片封装的、带有加强结构的集成散热结构的多芯片超薄扇出型封装结构,可以直接焊接在印刷电路板(PCB)上,无需再转接到基板(Substrate)上。
附图说明
图1为本实用新型一种多芯片超薄扇出型封装结构的实施例的剖面示意图;
主要元件符号说明
再布线金属线路层3
上层金属焊盘31
底层金属焊盘33
导热粘合层61
加强散热保护层63
焊锡料71
金属微凸块73
芯片焊盘75
芯片8
底填胶83
塑封料86
金属连接件91。
具体实施方式
现在将在下文中参照附图更加充分地描述本实用新型,在附图中示出了本实用新型的示例性实施例,从而本公开将本实用新型的范围充分地传达给本领域的技术人员。然而,本实用新型可以以许多不同的形式实现,并且不应被解释为限制于这里阐述的实施例。
实施例
本实用新型一种多芯片超薄扇出型封装结构,如图1所示,为多芯片超薄扇出型封装结构的实施例的剖面示意图。本实用新型一种多芯片超薄扇出型封装结构包括若干个独立的芯片8、再布线金属线路层3、加强散热保护层63、底填胶83和塑封料86。所述再布线金属线路层3为三层或三层以上金属层和绝缘层的复合层,其金属层的材质包括铝Al、铜Cu、镍Ni、金Au、其组合或合金,其绝缘层采用聚合物,包括聚苯并恶唑(polybenzoxazole,PBO)、聚酰亚胺(polyimide,PI)、苯并环丁烯(benzocyclobutene,BCB)、其组合或其类似物;其线宽/线距小于8um/8um。优选地,再布线金属线路层3为线宽/线距小至1.5um/1.5um的高密度再布线扇出层。
所述再布线金属线路层3的上表面设置上层金属焊盘31、下表面设置底层金属焊盘33,所述再布线金属线路层3的上层金属焊盘31的顶端还包括铜层和镍层,所述镍层覆盖铜层之上。所述芯片8的芯片焊盘75带有金属微凸块73,金属微凸块73通常为微铜柱凸块。所述金属微凸块73的顶端还包括镍层和金层,所述金层覆盖镍层之上,增强芯片8与再布线金属线路层3的连接。芯片8通常为采用先进芯片制程的不同功能的逻辑芯片,比如应用处理器等,芯片8上的金属微凸块73节距通常在40um至70um,采用倒装芯片互连的方式通过金属微凸块73、焊锡料71焊接在再布线金属线路层3的上层金属焊盘31上。芯片8通过再布线金属线路层3作为互联线路层实现选择性地电信连通。
所述底填胶83填充芯片8的底部和芯片间隙,所述塑封料86于再布线金属线路层3上方塑封芯片8,并露出芯片8的背面,使封装芯片的前后左右四个面得到双重保护,提高了封装产品的可靠性。
所述加强散热保护层63通过导热粘合层61设置在芯片8的背面,不仅进一步加强了包封体的强度,使封装芯片的前后左右四个面及背面均得到物理和电气保护,同时减小了整个封装结构的翘曲度,而且加强了芯片8单体的散热性能,有助于提高封装产品的可靠性。所述加强散热保护层63为硅片、玻璃片或金属片中的一种或几种组合;所述金属片为金属硒散热片或金属薄铜片。
所述再布线金属线路层3的底层金属焊盘33设置金属连接件91。所述金属连接件91为铜柱、金属扩散层或锡球,用于与印刷电路板相连。
以上所述的具体实施方式,对本实用新型的目的、技术方案和有益效果进行了进一步地详细说明,所应理解的是,以上所述仅为本实用新型的具体实施方式而已,并不用于限定本实用新型的保护范围,在本实用新型的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本实用新型的保护范围之内。

Claims (5)

1.一种多芯片超薄扇出型封装结构,其特征在于,其包括若干个芯片(8)、再布线金属线路层(3)、加强散热保护层(63)、底填胶(83)和塑封料(86),所述再布线金属线路层(3)的上表面设置上层金属焊盘(31)、下表面设置底层金属焊盘(33),所述芯片(8)的芯片焊盘(75)带有金属微凸块(73),所述芯片(8)通过金属微凸块(73)、焊锡料(71)与再布线金属线路层(3)的上层金属焊盘(31)固连,
所述底填胶(83)填充芯片(8)的底部和芯片间隙,所述塑封料(86)于再布线金属线路层(3)上方塑封芯片(8),并露出芯片(8)的背面;
所述加强散热保护层(63)通过导热粘合层(61)设置在芯片(8)的背面,所述加强散热保护层(63)为硅片、玻璃片或金属片中的一种或几种组合;
所述再布线金属线路层(3)的底层金属焊盘(33)设置金属连接件(91)。
2.如权利要求1所述的多芯片超薄扇出型封装结构,其特征在于,所述金属微凸块(73)的顶端还包括镍层和金层,所述金层覆盖镍层之上。
3.如权利要求1所述的多芯片超薄扇出型封装结构,其特征在于,所述再布线金属线路层(3)的上层金属焊盘(31)的顶端还包括铜层和镍层,所述镍层覆盖铜层之上。
4.如权利要求1所述的多芯片超薄扇出型封装结构,其特征在于,所述金属连接件(91)为铜柱、金属扩散层或锡球。
5.如权利要求1所述的多芯片超薄扇出型封装结构,其特征在于,所述金属片为金属硒散热片或金属薄铜片。
CN202022259453.XU 2020-10-12 2020-10-12 一种多芯片超薄扇出型封装结构 Active CN212342601U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202022259453.XU CN212342601U (zh) 2020-10-12 2020-10-12 一种多芯片超薄扇出型封装结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202022259453.XU CN212342601U (zh) 2020-10-12 2020-10-12 一种多芯片超薄扇出型封装结构

Publications (1)

Publication Number Publication Date
CN212342601U true CN212342601U (zh) 2021-01-12

Family

ID=74070942

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202022259453.XU Active CN212342601U (zh) 2020-10-12 2020-10-12 一种多芯片超薄扇出型封装结构

Country Status (1)

Country Link
CN (1) CN212342601U (zh)

Similar Documents

Publication Publication Date Title
KR102569791B1 (ko) 고라우팅 밀도 패치를 갖는 반도체 패키지
US20210384120A1 (en) Semiconductor packages and methods of forming same
US6958537B2 (en) Multiple chip semiconductor package
US9263364B2 (en) Thermal interface material with support structure
US9953907B2 (en) PoP device
US7799608B2 (en) Die stacking apparatus and method
US20070254406A1 (en) Method for manufacturing stacked package structure
US11515290B2 (en) Semiconductor package
US11088109B2 (en) Packages with multi-thermal interface materials and methods of fabricating the same
CN102376668A (zh) 覆晶封装结构以及半导体芯片
TWI737054B (zh) 半導體結構、封裝結構及形成半導體結構的方法
US9548283B2 (en) Package redistribution layer structure and method of forming same
CN112038305A (zh) 一种多芯片超薄扇出型封装结构及其封装方法
US20130256915A1 (en) Packaging substrate, semiconductor package and fabrication method thereof
TW202220151A (zh) 電子封裝件及其製法
CN109411418B (zh) 电子封装件及其制法
CN212342601U (zh) 一种多芯片超薄扇出型封装结构
US11817424B2 (en) Semiconductor package
CN112310010A (zh) 半导体封装体及其制造方法
CN112397475A (zh) 具有微细间距硅穿孔封装的扇出型封装晶片结构及单元
US12002784B2 (en) Semiconductor package
US11978729B2 (en) Semiconductor device package having warpage control and method of forming the same
US20240153855A1 (en) Semiconductor package
TWI793962B (zh) 半導體封裝件和半導體元件
US20240145360A1 (en) Semiconductor package and method of manufacturing the semiconductor package

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant