TWI673840B - Double-sided fan-out system in package - Google Patents

Double-sided fan-out system in package Download PDF

Info

Publication number
TWI673840B
TWI673840B TW107136429A TW107136429A TWI673840B TW I673840 B TWI673840 B TW I673840B TW 107136429 A TW107136429 A TW 107136429A TW 107136429 A TW107136429 A TW 107136429A TW I673840 B TWI673840 B TW I673840B
Authority
TW
Taiwan
Prior art keywords
chip
redistribution layer
memory
memory chip
package structure
Prior art date
Application number
TW107136429A
Other languages
Chinese (zh)
Other versions
TW202017124A (en
Inventor
潘吉良
李念庭
Original Assignee
力成科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 力成科技股份有限公司 filed Critical 力成科技股份有限公司
Priority to TW107136429A priority Critical patent/TWI673840B/en
Priority to CN201811228748.1A priority patent/CN111063663B/en
Application granted granted Critical
Publication of TWI673840B publication Critical patent/TWI673840B/en
Publication of TW202017124A publication Critical patent/TW202017124A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本發明係關於一雙面扇出型系統級封裝結構，係包含一第一重佈線層、一第二重佈線層與設置在該第一及第二重佈線層之間之一晶片及一晶片組；其中該晶片電性連接該第一重佈線層並形成有矽穿孔，該第二重佈線層電性連接至該晶片的矽穿孔與該晶片組，該晶片組可透過該第二重佈線層及矽穿孔與該晶片及第一重佈線電性連接；如此，該晶片及晶片組之間的電性連接即可不必透過堆疊設置或使用矽中介板或其他封裝載板，進而能有效減低封裝結構的高度；此外，包覆該晶片及晶片組之封膠體使得第一重佈線層與第二重佈線層相互隔離，可有效避免晶片及晶片組之高速訊號彼此相互干擾。The invention relates to a double-sided fan-out system-level package structure, which includes a first redistribution layer, a second redistribution layer, and a wafer and a wafer disposed between the first and second redistribution layers. Wherein the chip is electrically connected to the first redistribution layer and is formed with a through-silicon via, the second redistribution layer is electrically connected to the through-silicon via of the wafer and the chipset, and the chipset can pass through the second redistribution. Layer and through-silicon via are electrically connected to the chip and the first rewiring; in this way, the electrical connection between the chip and the chipset can be avoided by stacking or using a silicon interposer or other package carrier, thereby effectively reducing The height of the package structure; in addition, the sealing compound covering the chip and the chipset isolates the first redistribution layer and the second redistribution layer from each other, which can effectively prevent the high-speed signals of the chip and the chipset from interfering with each other.

Description

雙面扇出型系統級封裝結構Double-sided fan-out system-level packaging structure

本發明係關於一種系統封裝結構，尤指一種雙面扇出型系統級封裝結構。 The invention relates to a system packaging structure, in particular to a double-sided fan-out system-level packaging structure.

隨著電子裝置需要儲存及處理的資料量愈來愈大，其要求相關電子元件規格提升、數量也隨之增加，且必須設置在有限的空間內；為符合此要求，一種系統級封裝(System in Package,SiP)結構被提出，將相關功能的晶片整合於單一封裝結構，該系統級封裝結構包含有以下數種形式。 With the increasing amount of data that electronic devices need to store and process, the requirements for the specifications and quantity of related electronic components have increased, and they must be set in a limited space. To meet this requirement, a system-level package In Package (SiP) structure is proposed to integrate related function chips into a single package structure. The system-level package structure includes the following forms.

請參閱圖3所示，係為一種堆疊式封裝結構50(Package on Package；PoP)，於一下重佈線層51上電性連接有一邏輯晶片52，接著以第一封膠體53包覆該邏輯晶片52；之後，於該第一封膠體53及該邏輯晶片52上形成一上重佈線層54，將至少一記憶晶片55打線電性連接在該上重佈線層54之金屬接點541，再以第二封膠體56包覆該記憶晶片55；其中該上、下重佈線層54、51之間透過金屬柱57相互電性連接；若因應更大儲存空間需求，如圖4所示，則進一步於該記憶晶片55上再疊設其它記憶晶片55，惟該堆疊式封裝結構50’的高度會增加。 Please refer to FIG. 3, which is a stacked package structure 50 (Package on Package; PoP). A logic chip 52 is electrically connected to the lower redistribution layer 51, and then the logic chip is covered with a first sealing compound 53. 52; After that, an upper rewiring layer 54 is formed on the first sealing compound 53 and the logic chip 52, and at least one memory chip 55 is electrically connected to the metal contact 541 of the upper rewiring layer 54. The second encapsulant 56 covers the memory chip 55; the upper and lower heavy wiring layers 54 and 51 are electrically connected to each other through a metal pillar 57; if a larger storage space is required, as shown in FIG. 4, further Other memory chips 55 are stacked on the memory chip 55, but the height of the stacked package structure 50 'will increase.

請參閱圖5所示，係為一種多晶片封裝結構60(Multi-Chip Package；MCP)係將一邏輯晶片61及至少一記憶晶片組62電性連接在一矽中介板63上，由於該矽中介板63之相鄰外接墊631間距過小，通常會進一步電性連接至一封裝用載板64上，該封裝用載板64的相鄰外接墊641的間距即符合電子元件之 相鄰外接墊的間距；如此，即可將該邏輯晶片61及該至少一記憶晶片組62同時封裝成單一電子元件。 Please refer to FIG. 5, which is a multi-chip package structure 60 (Multi-Chip Package; MCP). A logic chip 61 and at least one memory chip group 62 are electrically connected to a silicon interposer 63. The distance between the adjacent external pads 631 of the interposer 63 is too small, and it is usually further electrically connected to a packaging carrier board 64. The distance between the adjacent external pads 641 of the packaging carrier board 64 is consistent with that of electronic components. The distance between adjacent external pads; in this way, the logic chip 61 and the at least one memory chip group 62 can be packaged into a single electronic component at the same time.

上述無論是堆疊式封裝結構或多晶片封裝結構的高度都較高，對於輕薄電子裝置來說，電子元件設置空間的高度仍有限制，故而有必要進一步提出改良。 The height of the above-mentioned stacked package structure or multi-chip package structure is relatively high. For light and thin electronic devices, the height of the space for installing electronic components is still limited, so it is necessary to further propose improvements.

有鑑於前揭多晶片封裝結構的高度過高，本發明的主要發明目的係提供一種薄化之雙面扇出型多晶片封裝結構。 In view of the fact that the height of the previously disclosed multi-chip package structure is too high, the main object of the present invention is to provide a thin double-sided fan-out multi-chip package structure.

欲達上述目的所使用的主要技術手段係令該雙面扇出型多晶片封裝結構包含有：一第一重佈線層，係於一第一介電本體內形成有複數第一連接線，該第一介電本體的一側形成有複數內接點，另一相對側係形成有複數外接墊，並透過該些第一連接線與該些內接點電性連接；一邏輯晶片，係包含一第一主動面及一相對該第一主動面之一第一背面，該第一主動面係包含有複數接點；其中該些接點分別電性連接於該第一重佈線層的對應內接點，且該邏輯晶片形成有複數第一矽穿孔，各該第一矽穿孔的第一端係與對應的該接點電性連接，而各該第一矽穿孔的第二端係外露於該第一背面；至少一記憶晶片組，各該記憶晶片組係包含有：一控制晶片，係包含有一第二背面，該第二背面係固定在該第一重佈線層；以及複數記憶晶片，係堆疊設置於該控制晶片上，各該記憶晶片包含有複數第二矽穿孔，以與相鄰記憶晶片及該控制晶片電性連接；其中遠離該控制晶片的記憶晶片係包含有一第二主動面； 一封膠層，係形成於該第一重佈線層上並包覆該邏輯晶片及各該記憶晶片組；其中該邏輯晶片的各該第一矽穿孔的第二端及各該記憶晶片組中之該記憶晶片的第二主動面外露於該封膠體；以及一第二重佈線層，係共同形成於該封膠層、該邏輯晶片的第一背面及各該記憶晶片組中之該記憶晶片的第二主動面上，以與該邏輯晶片之各該第一矽穿孔的第二端及各該記憶晶片組中之該記憶晶片的第二主動面電性連接。 The main technical means used to achieve the above purpose is to make the double-sided fan-out multi-chip package structure include: a first redistribution layer, formed of a plurality of first connection lines in a first dielectric body, the A plurality of internal contacts are formed on one side of the first dielectric body, and a plurality of external pads are formed on the other opposite side, and are electrically connected to the internal contacts through the first connection lines; a logic chip includes A first active surface and a first back surface opposite to the first active surface, the first active surface includes a plurality of contacts; wherein the contacts are electrically connected to corresponding ones of the first redistribution layer; Contacts, and the logic chip is formed with a plurality of first silicon vias, a first end of each first silicon via is electrically connected to a corresponding contact, and a second end of each first silicon via is exposed on The first back surface; at least one memory chip set, each of which includes: a control chip including a second back surface, the second back surface being fixed to the first redistribution layer; and a plurality of memory chips, The stacks are arranged on the control chip, each A second plurality of memory chips includes a through-silicon via to connect an adjacent memory chip and the control chip is electrically; wherein the remote control of the memory chip is a wafer comprises a second active surface; An adhesive layer is formed on the first redistribution layer and covers the logic chip and each of the memory chip groups; wherein the second end of each first TSV of the logic chip and each of the memory chip groups The second active surface of the memory chip is exposed from the sealing compound; and a second rewiring layer is formed together on the sealing layer, the first back surface of the logic chip, and the memory chip in each memory chip group. The second active surface of the logic chip is electrically connected to the second end of each of the first TSVs of the logic chip and the second active surface of the memory chip in the memory chip group.

由上述說明可知，本發明的雙面扇出型多晶片封裝結構主要將不同功能的邏輯晶片的第一主動面及記憶晶片組中之該記憶晶片的第二主動面分別電性連接在不同位置的第一及第二重佈線層，再配合該邏輯晶片的矽穿孔，仍可將各該記憶晶片組中之該記憶晶片的第二主動面與該邏輯晶片及第一重佈線的對應內接點電性連接；如此，該邏輯晶片及記憶晶片組即可不必堆疊設置或使用矽中介板或其他封裝載板，能有效減低封裝結構的高度；此外，由於該邏輯晶片的第一主動面及記憶晶片組中之該記憶晶片的第二主動面分別電性連接在不同位置的第一及第二重佈線層，而封膠體使得第一重佈線層與第二重佈線層相互隔離，可有效避免邏輯晶片及記憶晶片組之高速訊號彼此相互干擾。 It can be known from the above description that the double-sided fan-out multi-chip package structure of the present invention mainly electrically connects the first active surface of a logic chip with different functions and the second active surface of the memory chip in a memory chip group at different positions, respectively. The first and second redistribution layers of the CMOS and the TSV of the logic chip can still connect the second active surface of the memory chip in each memory chip group with the corresponding logic chip and the first rewiring. Point electrical connection; in this way, the logic chip and the memory chip set can be stacked without using or using a silicon interposer or other packaging carrier board, which can effectively reduce the height of the packaging structure; in addition, because the first active surface of the logic chip and the The second active surface of the memory chip in the memory chip group is electrically connected to the first and second redistribution layers at different positions respectively, and the sealing compound makes the first redistribution layer and the second redistribution layer isolated from each other, which is effective. Avoid high-speed signals of logic chip and memory chipset from interfering with each other.

10、10a、10b‧‧‧系統級封裝結構 10, 10a, 10b ‧‧‧ system level package structure

11‧‧‧第一重佈線層 11‧‧‧First Redistribution Layer

111‧‧‧第一介電本體 111‧‧‧The first dielectric body

112‧‧‧第一連接線 112‧‧‧First connecting line

113‧‧‧外接墊 113‧‧‧External pad

114‧‧‧內接點 114‧‧‧Internal contact

12‧‧‧封膠體 12‧‧‧ Sealing Colloid

13‧‧‧第二重佈線層 13‧‧‧ Second wiring layer

131‧‧‧第二介電本體 131‧‧‧Second dielectric body

132‧‧‧第二連接線 132‧‧‧Second connection line

14‧‧‧黏著層 14‧‧‧ Adhesive layer

20‧‧‧晶片 20‧‧‧Chip

21‧‧‧第一主動面 21‧‧‧ the first active face

211‧‧‧第一接點 211‧‧‧First contact

212‧‧‧第二接點 212‧‧‧Second Contact

22‧‧‧第一背面 22‧‧‧First back

23‧‧‧第一矽穿孔 23‧‧‧First Silicon Via

231‧‧‧第一端 231‧‧‧ the first end

232‧‧‧第二端 232‧‧‧second end

30‧‧‧晶片組 30‧‧‧ Chipset

301‧‧‧控制晶片 301‧‧‧control chip

302‧‧‧記憶晶片 302‧‧‧Memory Chip

31‧‧‧第二主動面 31‧‧‧Second Active Face

32‧‧‧第二背面 32‧‧‧ Second back

33‧‧‧第二矽穿孔 33‧‧‧Second Silicon Via

40‧‧‧被動元件、去耦合電容元件 40‧‧‧Passive element, decoupling capacitor element

41‧‧‧金屬接點 41‧‧‧Metal contacts

42‧‧‧第三背面 42‧‧‧ Third back

50、50’‧‧‧堆疊式封裝結構 50, 50’‧‧‧‧ stacked package structure

51‧‧‧下重佈線層 51‧‧‧ Lower redistribution layer

52‧‧‧邏輯晶片 52‧‧‧Logic Chip

53‧‧‧第一封膠體 53‧‧‧ First Colloid

54‧‧‧上重佈線層 54‧‧‧Upper wiring layer

541‧‧‧金屬接點 541‧‧‧metal contacts

55‧‧‧記憶晶片 55‧‧‧Memory Chip

56‧‧‧第二封膠體 56‧‧‧Second Sealing Colloid

57‧‧‧金屬柱 57‧‧‧metal pillar

60‧‧‧多晶片封裝結構 60‧‧‧Multi-chip package structure

61‧‧‧邏輯晶片 61‧‧‧Logic Chip

62‧‧‧記憶晶片組 62‧‧‧Memory Chipset

63‧‧‧矽中介板 63‧‧‧ Silicon Interposer

631‧‧‧外接墊 631‧‧‧External pad

64‧‧‧封裝用載板 64‧‧‧Packaging carrier board

641‧‧‧外接墊 641‧‧‧External pad

圖1：係本發明堆疊式封裝結構的第一較佳實施例的剖面圖。 FIG. 1 is a cross-sectional view of a first preferred embodiment of a stacked package structure of the present invention.

圖2A：係本發明堆疊式封裝結構的第二較佳實施例的剖面圖。 FIG. 2A is a cross-sectional view of a second preferred embodiment of the stacked package structure of the present invention.

圖2B：係本發明堆疊式封裝結構的第三較佳實施例的剖面圖。 FIG. 2B is a cross-sectional view of a third preferred embodiment of the stacked package structure of the present invention.

圖3：係既有一種堆疊式封裝結構的剖面圖。 Figure 3: A cross-sectional view of an existing stacked package structure.

圖4：係既有另一種堆疊式封裝結構的剖面圖。 Figure 4: A cross-sectional view of another stacked package structure.

圖5：係既有一種多晶片封裝結構的剖面圖。 FIG. 5 is a cross-sectional view of a conventional multi-chip package structure.

本發明係針對系統級封裝結構提出改良，使其封裝結構的高度得以減縮，也可進一步改善高速訊號干擾的問題，以下謹以複數實施例配合圖式詳加說明本發明的技術內容。 The present invention proposes improvements to the system-level packaging structure, so that the height of the packaging structure can be reduced, and the problem of high-speed signal interference can be further improved. The following is a detailed description of the technical content of the present invention with multiple embodiments and drawings.

首先請參閱圖1所示，係為本發明雙面扇出型系統級封裝結構10的第一較佳實施例，其包含有一第一重佈線層11、一晶片20、至少一晶片組30、一封膠層12以及一第二重佈線層13；其中該晶片20及各該晶片組30係共同設置在該第一及第二重佈線層11、13之間。 First, please refer to FIG. 1, which is a first preferred embodiment of a double-sided fan-out system-in-package structure 10 according to the present invention, which includes a first redistribution layer 11, a chip 20, at least one chip group 30, An adhesive layer 12 and a second redistribution layer 13; wherein the wafer 20 and each of the wafer groups 30 are collectively disposed between the first and second redistribution layers 11 and 13.

上述第一重佈線層11係於一第一介電本體111內形成有複數第一連接線112，並於一側形成與該些第一連接線112電性連接的複數外接墊113，於另一相對側形成與該些第一連接線112電性連接的複數內接點114；於本實施例，該些外接墊113為錫球，亦可為金屬凸塊，均不以此為限。 The first redistribution layer 11 includes a plurality of first connection lines 112 formed in a first dielectric body 111, and a plurality of external pads 113 electrically connected to the first connection lines 112 are formed on one side. A plurality of internal contacts 114 electrically connected to the first connection lines 112 are formed on an opposite side. In this embodiment, the external pads 113 are solder balls or metal bumps, which are not limited thereto.

上述晶片20包含有一第一主動面21及一相對該第一主動面21之第一背面22；其中該第一主動面21係包含有複數第一接點211及複數第二接點212；其中該些第一接點211及第二接點212係分別電性連接於該第一重佈線層11的對應內接點114，且該晶片20形成有複數第一矽穿孔23，各該第一矽穿孔23的第一端231係與該第一主動面21的對應第二接點212電性連接，各該第一矽穿孔23的第二端232則外露於該第一背面22；於本實施例中，該晶片20為一邏輯晶片(如：中央處理器CPU、繪圖處理器GPU等)。 The chip 20 includes a first active surface 21 and a first back surface 22 opposite to the first active surface 21. The first active surface 21 includes a plurality of first contacts 211 and a plurality of second contacts 212. The first contacts 211 and the second contacts 212 are respectively electrically connected to the corresponding internal contacts 114 of the first redistribution layer 11, and the chip 20 is formed with a plurality of first through-silicon vias 23. The first end 231 of the TSV 23 is electrically connected to the corresponding second contact 212 of the first active surface 21, and the second end 232 of each of the TSVs 23 is exposed on the first back surface 22; In the embodiment, the chip 20 is a logic chip (such as a central processing unit CPU, a graphics processing unit GPU, and the like).

上述各該晶片組30係包含有一第二主動面31及一相對該第二主動面31之一第二背面32；其中各該晶片組30之該第二背面32係固定於該第一重佈線層11上；於本實施例，該第二背面32係以一黏著層14固定在該第一重佈線層11，且各該晶片組30為一記憶晶片組，其包含有一控制晶片301及至少一記憶晶 片302，該控制晶片301及該至少一記憶晶片302係堆疊設置，且各該記憶晶片302形成有第二矽穿孔33，以與相鄰的記憶晶片302及該控制晶片301電性連接，且該控制晶片301的背面係固定於該第一重佈線層11上，而相對位在最外的記憶晶片302的主動面即是該晶片組30的第二主動面31。 Each of the chip sets 30 includes a second active surface 31 and a second back surface 32 opposite to the second active surface 31. The second back surface 32 of each chip group 30 is fixed to the first redistribution. Layer 11; in this embodiment, the second back surface 32 is fixed to the first redistribution layer 11 with an adhesive layer 14, and each chip group 30 is a memory chip group, which includes a control chip 301 and at least A memory crystal Piece 302, the control chip 301 and the at least one memory chip 302 are arranged in a stack, and each of the memory chips 302 is formed with a second silicon through-hole 33 to be electrically connected to the adjacent memory chip 302 and the control chip 301, and The back surface of the control chip 301 is fixed on the first redistribution layer 11, and the active surface of the memory chip 302 located at the outermost side is the second active surface 31 of the chip group 30.

上述封膠層12係形成在該第一重佈線層11上並包覆該晶片20及各該晶片組30，惟該晶片20的各該第一矽穿孔23的第二端232及各該晶片組30的第二主動面31係外露於該封膠體12，即該晶片20的第一背面22與各該晶片組30的該第二主動面31齊平。 The above-mentioned sealant layer 12 is formed on the first redistribution layer 11 and covers the wafer 20 and each of the wafer groups 30, but the second ends 232 of the first TSVs 23 of the wafer 20 and the wafers The second active surface 31 of the group 30 is exposed from the sealing body 12, that is, the first back surface 22 of the wafer 20 is flush with the second active surface 31 of each of the wafer groups 30.

上述第二重佈線層13係共同形成於該封膠層12、該晶片20及各該晶片組30上，並與該晶片20之各該第一矽穿孔23的第二端232與各該晶片組30的第二主動面31電性連接。該第二重佈線層13係於一第二介電本體131內形成有複數第二連接線132，用以電性連接該晶片20之各該第一矽穿孔23的第二端232與各該晶片組30的第二主動面31；如此，各該晶片組30的第二主動面31係透過該第二連接線132、該第一矽穿孔23及第二接點212，以與該晶片20及第一重佈線層11電性連接。 The second redistribution layer 13 is formed on the sealant layer 12, the wafer 20, and each of the wafer groups 30 together with the second ends 232 of the first TSVs 23 of the wafer 20 and the wafers. The second active surfaces 31 of the group 30 are electrically connected. The second redistribution layer 13 is formed in a second dielectric body 131 with a plurality of second connecting lines 132 for electrically connecting the second ends 232 of the first TSVs 23 and the The second active surface 31 of the chip group 30; thus, the second active surface 31 of each chip group 30 passes through the second connection line 132, the first through-silicon via 23, and the second contact point 212 to communicate with the chip 20 And the first redistribution layer 11 is electrically connected.

由上述說明可知，本發明之雙面扇出型系統級封裝結構10係包含有雙層的第一及第二重佈線層11、13，不同功能的晶片及晶片組20、30係設置在該第一及第二重佈線層11、13之間，並分別與對應的第一或第二重佈線層11、13電性連接，以隔離該晶片及晶片組20、30傳送訊號相互干擾；又第二重佈線層13再透過該晶片20的第一矽穿孔23及該晶片20的第二接點212電性連接至該第一重佈線層11，且該晶片20的高度可與該晶片組30的高度實質相同。 From the above description, it can be seen that the double-sided fan-out system-level package structure 10 of the present invention includes the first and second redistribution layers 11 and 13 with two layers, and the chips and chip sets 20 and 30 with different functions are disposed there. The first and second redistribution layers 11 and 13 are respectively electrically connected to the corresponding first or second redistribution layers 11 and 13 to isolate the transmission signals of the chip and the chipset 20 and 30 from each other; The second redistribution layer 13 is electrically connected to the first redistribution layer 11 through the first TSV 23 of the chip 20 and the second contact 212 of the chip 20, and the height of the chip 20 can be the same as that of the chipset. The height of 30 is essentially the same.

再請參閱圖2A所示，本發明之雙面扇出型系統級封裝結構10a的第二較佳實施例，其大多結構與圖1所示之第一較佳實施例相同，惟進一步包含有一被動元件40，該被動元件40係包含有金屬接點41；於本實施例中，該被動元 件40可為一去耦合電容元件40，其主要用以提供一穩定且低雜訊之電源給予晶片20及晶片組30，故其金屬接點41係對應電性連接至該些第二連接線132，即該晶片20的該第一背面22、各該晶片組30的第二主動面31及該去耦合電容40的金屬接點41齊平，且去耦合電容元件40的第三背面42設置在該第一重佈線層11上；於本實施例，該第三背面42係以一黏著層14固定在該第一重佈線層11上；又該去耦合電容元件40係與該第二重佈線層13之第二連接線132的系統電源及接地電源電性連接。於本實施例中，該被動元件40可為一貼片式元件(Surface mount device)或內藏基板式元件(Embedded substrate device)的一例，並不以此為限。於本實施例中，該去耦合電容元件40僅為被動元件的一例，並不以此為限。 Please refer to FIG. 2A again. The second preferred embodiment of the double-sided fan-out system-level packaging structure 10a of the present invention has most of the same structure as the first preferred embodiment shown in FIG. 1, but further includes a The passive element 40 includes a metal contact 41. In this embodiment, the passive element 40 The component 40 can be a decoupling capacitor element 40, which is mainly used to provide a stable and low noise power to the chip 20 and the chip group 30. Therefore, the metal contact 41 is correspondingly electrically connected to the second connection lines. 132, that is, the first back surface 22 of the chip 20, the second active surface 31 of each chip group 30, and the metal contact 41 of the decoupling capacitor 40 are flush, and the third back surface 42 of the decoupling capacitor element 40 is disposed On the first redistribution layer 11; in this embodiment, the third back surface 42 is fixed on the first redistribution layer 11 with an adhesive layer 14; and the decoupling capacitor element 40 is connected to the second redistribution layer. The system power and ground power of the second connection line 132 of the wiring layer 13 are electrically connected. In this embodiment, the passive component 40 may be an example of a surface mount device or an embedded substrate device, and is not limited thereto. In this embodiment, the decoupling capacitor element 40 is only an example of a passive element, and is not limited thereto.

再如圖2B所示，本發明之雙面扇出型系統級封裝結構10b的第三較佳實施例，其結構與圖2A所示之第二較佳實施例相同，且該去耦合電容元件40主要用以提供一穩定且低雜訊之電源給予晶片20及晶片組30，惟該去耦合電容元件40的金屬接點41係對應電性連接至該些第一連接線112，其第三背面42設置在該第二重佈線層13內側面，即該晶片20的第一背面22、各該晶片組30的第二主動面31與該去耦合電容元件40的第三背面43齊平；又該去耦合電容元件40係與該第一重佈線層11之第一連接線112的系統電源及接地電源電性連接。 As shown in FIG. 2B, the third preferred embodiment of the double-sided fan-out system-level package structure 10b of the present invention has the same structure as the second preferred embodiment shown in FIG. 2A, and the decoupling capacitor element 40 is mainly used to provide a stable and low noise power to the chip 20 and the chip group 30, but the metal contact 41 of the decoupling capacitor element 40 is electrically connected to the first connection lines 112, and the third The back surface 42 is disposed on the inner side of the second redistribution layer 13, that is, the first back surface 22 of the wafer 20 and the second active surface 31 of each of the chip groups 30 are flush with the third back surface 43 of the decoupling capacitor element 40; The decoupling capacitor element 40 is electrically connected to a system power source and a ground power source of the first connection line 112 of the first redistribution layer 11.

此外，前揭該晶片20的高度、各該晶片組30的高度與該被動元件40的高度係可實質相同，故該被動元件40與該晶片20及各該晶片組30共平面。 In addition, the height of the wafer 20 and the height of each of the chip groups 30 and the height of the passive components 40 may be substantially the same, so the passive component 40 is coplanar with the wafer 20 and each of the wafer groups 30.

綜上所述，本發明的雙面扇出型多晶片封裝結構主要將不同功能的晶片的第一主動面及晶片組的第二主動面分別電性連接在不同位置的第一及第二重佈線層，再配合該晶片的矽穿孔，仍可將各該晶片組的第二主動面與該晶片及第一重佈線的對應內接點電性連接；如此，該晶片及晶片組即可不必堆疊設置或使用矽中介板或其他封裝載板，能有效減低封裝結構的高度；此外，由於該晶片及晶片組分別電性連接在不同位置的第一及第二重佈線層，而封膠體使得 第一重佈線層與第二重佈線層相互隔離，，可有效避免晶片及晶片組之高速訊號彼此相互干擾。 In summary, the double-sided fan-out type multi-chip packaging structure of the present invention mainly electrically connects the first active surface of a chip with different functions and the second active surface of a chip group at first and second positions of different positions, respectively. The wiring layer, together with the TSV of the chip, can still electrically connect the second active surface of each chip group with the corresponding internal contacts of the chip and the first rewiring; in this way, the chip and chip group can be eliminated. Stacking or using a silicon interposer or other package carrier can effectively reduce the height of the package structure. In addition, because the chip and the chipset are electrically connected to the first and second redistribution layers at different positions, the sealing compound makes The first rewiring layer and the second rewiring layer are isolated from each other, which can effectively prevent the high-speed signals of the chip and the chipset from interfering with each other.

以上所述僅是本發明的實施例而已，並非對本發明做任何形式上的限制，雖然本發明已以實施例揭露如上，然而並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明技術方案的範圍內，當可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例，但凡是未脫離本發明技術方案的內容，依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾，均仍屬於本發明技術方案的範圍內。 The above description is only an embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed by the embodiments as above, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field of the art, Within the scope not departing from the technical solution of the present invention, when the above disclosed technical content can be used to make a few changes or modifications to equivalent equivalent embodiments, as long as it does not depart from the technical solution of the present invention, it is in accordance with the technical essence of the present invention. Any simple modifications, equivalent changes, and modifications made to the above embodiments still fall within the scope of the technical solution of the present invention.

Claims (9)

一種雙面扇出型多晶片封裝結構，包括：一第一重佈線層，係於一第一介電本體內形成有複數第一連接線，該第一介電本體的一側形成有複數內接點，另一相對側係形成有複數外接墊，並透過該些第一連接線與該些內接點電性連接；一邏輯晶片，係包含一第一主動面及一相對該第一主動面之一第一背面，該第一主動面係包含有複數接點；其中該些接點分別電性連接於該第一重佈線層的對應內接點，且該邏輯晶片形成有複數第一矽穿孔，各該第一矽穿孔的第一端係與對應的該接點電性連接，而各該第一矽穿孔的第二端係外露於該第一背面；至少一記憶晶片組，各該記憶晶片組係包含有：一控制晶片，係包含有一第二背面，該第二背面係固定在該第一重佈線層；以及複數記憶晶片，係堆疊設置於該控制晶片上，各該記憶晶片包含有複數第二矽穿孔，以與相鄰記憶晶片及該控制晶片電性連接；其中遠離該控制晶片的記憶晶片係包含有一第二主動面；一封膠層，係形成於該第一重佈線層上並包覆該邏輯晶片及各該記憶晶片組；其中該邏輯晶片的各該第一矽穿孔的第二端及各該記憶晶片組中之該記憶晶片的第二主動面外露於該封膠體；以及一第二重佈線層，係共同形成於該封膠層、該邏輯晶片的第一背面及各該記憶晶片組中之該記憶晶片的第二主動面上，以與該邏輯晶片之各該第一矽穿孔的第二端及各該記憶晶片組中之該記憶晶片的第二主動面電性連接。A double-sided fan-out type multi-chip package structure includes: a first redistribution layer formed in a first dielectric body with a plurality of first connection lines formed on one side of the first dielectric body A plurality of external pads are formed on the other opposite side of the contact, and are electrically connected to the internal contacts through the first connection lines; a logic chip includes a first active surface and a first active surface A first back surface of the surface, the first active surface includes a plurality of contacts; wherein the contacts are electrically connected to corresponding internal contacts of the first redistribution layer, respectively, and the logic chip is formed with a plurality of first contacts Through silicon vias, the first end of each first through silicon via is electrically connected to the corresponding contact, and the second end of each first through silicon via is exposed on the first back surface; at least one memory chip set, each The memory chip group includes: a control chip including a second back surface, the second back surface is fixed on the first rewiring layer; and a plurality of memory chips are stacked on the control chip, each memory The chip contains a plurality of second through silicon vias to The adjacent memory chip and the control chip are electrically connected; wherein the memory chip remote from the control chip includes a second active surface; an adhesive layer is formed on the first redistribution layer and covers the logic chip and Each of the memory chip sets; wherein the second ends of the first through silicon vias of the logic chip and the second active surface of the memory chips in each of the memory chip sets are exposed to the encapsulant; and a second redistribution layer Is formed on the sealant layer, the first back surface of the logic chip, and the second active surface of the memory chip in each memory chip group together with the second of the first silicon through hole of the logic chip And the second active surface of each memory chip in each memory chip group is electrically connected. 如請求項1所述之雙面扇出型多晶片封裝結構，各該記憶晶片組中之該控制晶片的第二背面係以一黏著層固定於該第一重佈線層上。According to the double-sided fan-out type multi-chip package structure of claim 1, the second back surface of the control chip in each memory chip group is fixed on the first redistribution layer with an adhesive layer. 如請求項1所述之雙面扇出型多晶片封裝結構，係進一步包含有：一被動元件，其第三背面係固定於該第一重佈線層上，且其複數金屬接點係與該第二重佈線層電性連接，或該第三背面係固定於該第二重佈線層內側面，且其複數金屬接點係與該第一重佈線層電性連接。The double-sided fan-out type multi-chip package structure as described in claim 1, further comprising: a passive element, a third back surface of which is fixed on the first redistribution layer, and a plurality of metal contacts are connected to the The second redistribution layer is electrically connected, or the third back surface is fixed to the inner surface of the second redistribution layer, and a plurality of metal contacts are electrically connected to the first redistribution layer. 如請求項1或2所述之雙面扇出型多晶片封裝結構，該邏輯晶片的該第一背面與各該記憶晶片組中之該記憶晶片的該第二主動面齊平。According to the double-sided fan-out type multi-chip package structure of claim 1 or 2, the first back surface of the logic chip is flush with the second active surface of the memory chip in each memory chip group. 如請求項1所述之雙面扇出型多晶片封裝結構，該邏輯晶片的高度與各該記憶晶片組的高度實質相同。According to the double-sided fan-out type multi-chip package structure described in claim 1, the height of the logic chip is substantially the same as the height of each memory chip group. 如請求項3所述之雙面扇出型多晶片封裝結構，該被動元件係與該邏輯晶片與各該記憶晶片組共平面。According to the double-sided fan-out type multi-chip package structure of claim 3, the passive element is coplanar with the logic chip and each memory chip group. 如請求項3所述之雙面扇出型多晶片封裝結構，該邏輯晶片的高度、各該記憶晶片組的高度與該被動元件的高度實質相同。According to the double-sided fan-out type multi-chip package structure of claim 3, the height of the logic chip and the height of each memory chip set are substantially the same as the height of the passive device. 如請求項1所述之雙面扇出型多晶片封裝結構，該第二重佈層係包含有一第二介電本體，該第二介電本體內形成有複數第二連接線，以電性連接該邏輯晶片之各該第一矽穿孔的第二端與各該記憶晶片組中之該記憶晶片的第二主動面。The double-sided fan-out type multi-chip package structure as described in claim 1, the second redistribution layer includes a second dielectric body, and a plurality of second connection lines are formed in the second dielectric body to electrically The second end of each first through-silicon via of the logic chip is connected to the second active surface of the memory chip in each memory chip set. 如請求項3、6或7所述之雙面扇出型多晶片封裝結構，該被動元件為一去耦合電容元件。In the double-sided fan-out type multi-chip package structure as described in claim 3, 6 or 7, the passive element is a decoupling capacitor element.
TW107136429A 2018-10-16 2018-10-16 Double-sided fan-out system in package TWI673840B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW107136429A TWI673840B (en) 2018-10-16 2018-10-16 Double-sided fan-out system in package
CN201811228748.1A CN111063663B (en) 2018-10-16 2018-10-22 Double-sided fan-out type system-in-package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW107136429A TWI673840B (en) 2018-10-16 2018-10-16 Double-sided fan-out system in package

Publications (2)

Publication Number Publication Date
TWI673840B true TWI673840B (en) 2019-10-01
TW202017124A TW202017124A (en) 2020-05-01

Family

ID=69023463

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107136429A TWI673840B (en) 2018-10-16 2018-10-16 Double-sided fan-out system in package

Country Status (2)

Country Link
CN (1) CN111063663B (en)
TW (1) TWI673840B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022247294A1 (en) * 2021-05-27 2022-12-01 荣耀终端有限公司 Chip package structure and manufacturing method, and electronic device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112151470B (en) * 2020-09-28 2022-07-22 青岛歌尔微电子研究院有限公司 Chip packaging structure, preparation method thereof and electronic device
US20220223512A1 (en) * 2021-01-08 2022-07-14 Mediatek Inc. Semiconductor package structure
CN114975415A (en) * 2022-04-29 2022-08-30 盛合晶微半导体(江阴)有限公司 Fan-out stacked semiconductor packaging structure and packaging method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201614778A (en) * 2014-10-03 2016-04-16 Powertech Technology Inc Semiconductor packaging structure
US20160118333A1 (en) * 2014-10-24 2016-04-28 Stats Chippac, Ltd. Semiconductor Device and Method of Fabricating 3D Package with Short Cycle Time and High Yield
TW201729360A (en) * 2016-02-05 2017-08-16 力成科技股份有限公司 Fan-out back-to-back chip stacked package and the method for manufacturing the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9373527B2 (en) * 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US20160049383A1 (en) * 2014-08-12 2016-02-18 Invensas Corporation Device and method for an integrated ultra-high-density device
US9583472B2 (en) * 2015-03-03 2017-02-28 Apple Inc. Fan out system in package and method for forming the same
US9831148B2 (en) * 2016-03-11 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
US10535632B2 (en) * 2016-09-02 2020-01-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and method of manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201614778A (en) * 2014-10-03 2016-04-16 Powertech Technology Inc Semiconductor packaging structure
US20160118333A1 (en) * 2014-10-24 2016-04-28 Stats Chippac, Ltd. Semiconductor Device and Method of Fabricating 3D Package with Short Cycle Time and High Yield
TW201729360A (en) * 2016-02-05 2017-08-16 力成科技股份有限公司 Fan-out back-to-back chip stacked package and the method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022247294A1 (en) * 2021-05-27 2022-12-01 荣耀终端有限公司 Chip package structure and manufacturing method, and electronic device

Also Published As

Publication number Publication date
CN111063663B (en) 2021-08-24
TW202017124A (en) 2020-05-01
CN111063663A (en) 2020-04-24

Similar Documents

Publication Publication Date Title
TWI673840B (en) Double-sided fan-out system in package
US11088080B2 (en) Chip package structure using silicon interposer as interconnection bridge
US9607947B2 (en) Reliable microstrip routing for electronics components
US9502335B2 (en) Package structure and method for fabricating the same
US8143710B2 (en) Wafer-level chip-on-chip package, package on package, and methods of manufacturing the same
US7888785B2 (en) Semiconductor package embedded in substrate, system including the same and associated methods
US20210249382A1 (en) Semiconductor package and method of manufacturing semiconductor package
KR20130007049A (en) Package on package using through silicon via technique
US9299685B2 (en) Multi-chip package having a logic chip disposed in a package substrate opening and connecting to an interposer
TW201810600A (en) Semiconductor package
US10756076B2 (en) Semiconductor package
US20140246781A1 (en) Semiconductor device, method of forming a packaged chip device and chip package
US20230116326A1 (en) Semiconductor package with tsv die
US11257741B2 (en) Semiconductor package
US11145627B2 (en) Semiconductor package and manufacturing method thereof
US20230378072A1 (en) Electronic package and manufacturing method thereof
US20230050400A1 (en) Semiconductor package with reduced connection length
US20230230902A1 (en) Semiconductor package structure and manufacturing method thereof
US10204885B2 (en) Semiconductor package including stacked semiconductor chips electrically connected to redistribution layers
TW201719841A (en) Electronic package and method of manufacture
TW202318612A (en) Electronic device
TWI715486B (en) Semiconductor package
CN112397475A (en) Fan-out type packaging chip structure and unit with fine-pitch through-silicon-via packaging
US11227854B2 (en) Semiconductor package
CN113555351B (en) Semiconductor package