CN107978532A - 形成堆叠式封装结构的方法 - Google Patents

形成堆叠式封装结构的方法 Download PDF

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Publication number
CN107978532A
CN107978532A CN201710594258.2A CN201710594258A CN107978532A CN 107978532 A CN107978532 A CN 107978532A CN 201710594258 A CN201710594258 A CN 201710594258A CN 107978532 A CN107978532 A CN 107978532A
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semiconductor package
package body
molding compound
substrate
conductive
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徐宏欣
王启安
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Powertech Technology Inc
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Powertech Technology Inc
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Abstract

本发明揭露一种形成堆叠式封装结构的方法。对第一半导体封装体的模封复合物进行激光钻孔，以在模封复合物内形成多个贯穿孔。导电层形成于模封复合物上，以使模封复合物被导电物质所覆盖，且使上述的多个贯穿孔被导电物质所填充。导电层被研磨后，会暴露出模封复合物。第二半导体封装体堆叠在第一半导体封装体上，以使第二半导体封装体的多个金属凸块与填充于多个贯穿孔内的导电物质接触。本发明可减少堆叠式封装结构的厚度。

Description

形成堆叠式封装结构的方法
技术领域
本发明有关于一种封装的方法，尤指一种形成堆叠式封装(package-on-package；POP)结构的方法。
背景技术
堆叠式封装(POP)是目前成长最快速的半导体封装技术，这是因为对于整合在单一封装体中的高密度系统来说，堆叠式封装是个具有高度成本效益的方案。在堆叠式封装结构中，多种的封装体被整合在单一封装体中，以减少其尺寸。背景技术中的堆叠式封装结构通常使用焊球、焊柱或铜柱，并通过表面粘着技术(surface mounttechnology；SMT)或回焊工艺(reflow process)，以连接第一封装体与第二封装体。多个封装体可因此被整合成单一封装体，以缩小这些封装体的尺寸并降低其电路的复杂度。然而，减少封装体的厚度仍旧是困难的。由于堆叠式封装结构至少包含了两个彼此堆叠的封装体，故共通的问题是堆叠式封装结构的厚度会因此而太厚而难以被薄化。对于诸如行动装置的应用，尺寸太大的堆叠式封装结构将会难以嵌入到一个小装置内。因此，对本领域来说，亟需一种可减少封装结构的厚度的方案。
发明内容
本发明的一实施例提供一种形成一堆叠式封装(package-on-package；POP)结构的方法。上述的方法包含对第一半导体封装体的模封复合物(mold compound)进行激光钻孔，以在模封复合物内形成多个贯穿孔(through hole)；在模封复合物上形成导电层，以使模封复合物被导电物质所覆盖，并使导电物质填充于上述多个贯穿孔内；研磨导电层，以暴露模封复合物；以及将一第二半导体封装体堆叠在第一半导体封装体，以使第二半导体封装体的多个金属凸块与填充于上述多个贯穿孔内的导电物质接触。
本发明可减少堆叠式封装结构的厚度。
附图说明
图1至图6是依据本发明的第一实施例而绘示的一种形成堆叠式封装结构的方法的对应步骤的元件截面示意图。
图7至图12是依据本发明的第二实施例而绘示的一种形成堆叠式封装结构的方法的对应步骤的元件截面示意图。
附图标号
100、400 第一半导体封装体
110 第一芯片
112、212 柱状凸块
114 接合接线
120、220 模封复合物
122 贯穿孔
130 垫遮罩层
132 导电垫
140、240 基板
142、242 导电柱
150、250 金属凸块
160 导电层
160A 贯穿导孔
200 第二半导体封装体
210 第二芯片
300、500 堆叠式封装结构
D 距离
H 高度
具体实施方式
以下将配合所附图示详细说明本发明的实施例，然应注意的是，该些图示均为简化的示意图，仅以示意方法来说明本发明的基本架构或实施方法，故仅显示与本案有关的元件与组合关系，图中所显示的元件并非以实际实施的数目、形状、尺寸做等比例绘制，某些尺寸比例与其他相关尺寸比例或已夸张或是简化处理，以提供更清楚的描述。实际实施的数目、形状及尺寸比例为一种选置性的设计，详细的元件布局可能更为复杂。
依据本发明的第一实施例，一种形成堆叠式封装结构的方法举例说明于图1至图6的元件截面示意图。
如图1所示，提供了第一半导体封装体100。第一半导体封装体100包含第一芯片(die)110、模封复合物(mold compound)120、多个导电垫(conductive pad)132、基板140以及多个金属凸块(metal bump)150。第一芯片110与导电垫132设置于基板140上且被模封复合物120所包覆。金属凸块150形成于基板140之下。在此实施例中，第一半导体封装体100是一个覆晶封装体(flip-chip package)，然而本发明并不以此为限。第一芯片110可具有多个柱状凸块(pillar bump)112，柱状凸块112设置于基板140上并电连接到部分的金属凸块150。柱状凸块112作为第一芯片110的输入/输出介面。基板140可包含垫遮罩层(pad masklayer)130以及多个导电柱142。导电柱142形成在基板140内并贯穿基板140。部分的金属凸块150通过导电柱142电连接到导电垫132。在此实施例中，第一半导体封装体100也可以是一个扇出型封装体(fan-out package)。
如图2所示，可对模封复合物120进行激光钻孔，以在模封复合物120内形成多个贯穿孔(through hole)122，进而使导电垫132暴露在贯穿孔122的底部。模封复合物120可以是环氧树脂模制化合物(epoxy molding compound)。
如图3所示，导电层160可形成在模封复合物120上，以使模封复合物120被一导电物质所覆盖，并使贯穿孔122被上述的导电物质所填充。上述的导电物质可以是铜、金或金铜合金。其中，可通过将上述导电物质溅射或电镀在模封复合物120上的方式，而在模封复合物120上形成导电层160。
如图4所示，可研磨导电层160，以暴露模封复合物120。藉此，填充于贯穿孔122内的导电物质形成了多个贯穿导孔(through hole via；THV)160A。贯穿导孔160A可与导电垫132接触，而每一贯穿导孔160A的高度H可介于200微米至300微米之间，且两相邻贯穿导孔160A的底部之间的距离D可小于300微米。在本发明另一实施例中，当研磨导电层160时，可同时地研磨模封复合物120。由于导电层160与模封复合物120可被研磨，故可减少第一半导体封装体100的厚度。在本发明另一实施例中，第一半导体封装体100的基板140可在贯穿导孔160A形成后被移除，而如此一来，可进一步地减少第一半导体封装体100的厚度。
如图5及图6所示，第二半导体封装体200堆叠在第一半导体封装体100上。当第二半导体封装体200堆叠在第一半导体封装体100上时，第二半导体封装体200的多个金属凸块250可与贯穿导孔160A接触。第二半导体封装体200的金属凸块250可通过执行一回焊程序(reflow soldering process)而接合于贯穿导孔160A的暴露表面。其结果，第一半导体封装体100与第二半导体封装体200可整合成堆叠式封装(POP)结构300。由于贯穿孔122可通过执行激光钻孔而形成，故堆叠式封装结构300可以是一个微间距的(fine pitch)封装体。
在本实施例中，第二半导体封装体200可以是一个扇出型封装体及/或覆晶封装体，然而本发明并不以此为限。第二半导体封装体200包含第二芯片210、模封复合物220、基板240以及多个金属凸块250。第二芯片210设置于基板240上并被模封复合物220所包覆。多个金属凸块250形成于基板240之下。第二芯片210通过第二半导体封装体200的金属凸块250、贯穿导孔160A以及基板140的导电电路，而电连接到第一半导体封装体100部分的金属凸块150。第二芯片210包含多个柱状凸块212。导电柱242设置于基板240内并电连接到金属凸块250。
依据本发明的第二实施例，另一种形成堆叠式封装结构的方法举例说明于图7至图12的元件截面示意图。其中，第一实施例与第二实施例中所使用的相同元件符号表示相同的元件。
如图7所示，依据本发明第二实施例，提供了第一半导体封装体400。两个第一半导体封装体100与400之间最大的不同点在于图7中的第一芯片110通过打线(wire bonding)的方式而耦接于基板140。其中，第一芯片110通过多条接合接线(bonding wire)114而电连接到形成在基板140中的电路。上述形成在基板140中的电路电连接到部分的金属凸块150。
如图8所示，可对模封复合物120进行激光钻孔，以在模封复合物120内形成多个贯穿孔122，进而使导电垫132暴露在贯穿孔122的底部。
如图9所示，导电层160可形成在模封复合物120上，以使模封复合物120被一导电物质所覆盖，并使贯穿孔122被上述的导电物质所填充。
如图10所示，可研磨导电层160，以暴露模封复合物120。藉此，填充于贯穿孔122内的导电物质形成了多个贯穿导孔160A。贯穿导孔160A可与导电垫132接触，而每一贯穿导孔160A的高度H可介于200微米至300微米之间，且两相邻贯穿导孔160A的底部之间的距离D可小于300微米。在本发明另一实施例中，当研磨导电层160时，可同时地研磨模封复合物120。由于导电层160与模封复合物120可被研磨，故可减少第一半导体封装体400的厚度。
如图11及图12所示，第二半导体封装体200堆叠在第一半导体封装体400上。当第二半导体封装体200堆叠在第一半导体封装体400上时，第二半导体封装体200的多个金属凸块250可与贯穿导孔160A接触。第二半导体封装体200的金属凸块250可通过执行一回焊程序而接合于第一半导体封装体40的贯穿导孔160A。其结果，第一半导体封装体400与第二半导体封装体200可整合成堆叠式封装结构500。
综上所述，通过进行激光钻孔，可以在模封复合物内形成多个贯穿孔，而贯穿孔可填充导电物质以形成多个贯穿导孔。两相邻贯穿导孔的底部之间的距离可小于300微米，而使所形成的堆叠式封装结构可以是一个微间距的封装体。此外，导电层与模封复合物可被研磨，且第一半导体封装体的基板可在贯穿导孔形成后被移除。因此，可减少堆叠式封装结构的厚度。
以上所述仅为本发明的较佳实施例，凡依本发明申请专利范围所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (10)

1.一种形成堆叠式封装结构的方法，其特征在于，包含：
对一第一半导体封装体的一模封复合物进行激光钻孔，以在该模封复合物内形成多个贯穿孔；
在该模封复合物上形成一导电层，以使该模封复合物被一导电物质所覆盖，并使该导电物质填充于该些贯穿孔内；
研磨该导电层，以暴露该模封复合物；以及
将一第二半导体封装体堆叠在该第一半导体封装体，以使该第二半导体封装体的多个金属凸块与填充于该些贯穿孔内的该导电物质接触。
2.如权利要求1所述的方法，其特征在于，在该模封复合物上形成该导电层包括以溅射或电镀的方式将该导电物质形成在该模封复合物上。
3.如权利要求1所述的方法，其特征在于，该第一半导体封装体包含一第一芯片以及一第一基板，一电路形成在该第一基板内，而该第一芯片通过多条接合接线电连接到该电路。
4.如权利要求1所述的方法，其特征在于，该第一半导体封装体包含一第一芯片、一第一基板以及多个导电垫，该第一芯片设置于该第一基板上且被该模封复合物所包覆，而在对该模封复合物进行完激光钻孔后，该多个导电垫暴露于该多个贯穿孔的底部。
5.如权利要求4所述的方法，其特征在于，该第一半导体封装体另包含形成在该第一基板内的多个导电柱以及形成在该第一基板之下的多个金属凸块，而该多个导电垫通过该多个导电柱电连接到该第一半导体封装体的该多个金属凸块中的部分的金属凸块。
6.如权利要求1所述的方法，其特征在于，该第二半导体封装体包含一第二芯片，第一半导体封装体包含一第一芯片、一第一基板、多个导电柱以及多个金属凸块，该第一芯片设置于该第一基板上且被该模封复合物所包覆，该多个导电柱形成于该第一基板内，该第一半导体封装体的该多个金属凸块形成于该第一基板之下，填充于该多个贯穿孔内的该导电物质形成多个贯穿导孔，而该第二芯片通过该第二半导体封装体的该多个金属凸块、该多个贯穿导孔以及该多个导电柱电连接到该第一半导体封装体的该多个金属凸块中的部分金属凸块。
7.如权利要求6所述的方法，其特征在于，该第二半导体封装体另包含多个柱状凸块，电连接到该第二半导体封装体的该多个金属凸块。
8.如权利要求6所述的方法，其特征在于，该第二半导体封装体另包含一第二基板，该第二芯片设置于该第二基板上，而该第二半导体封装体的该多个金属凸块形成于该第二基板之下。
9.如权利要求1所述的方法，其特征在于，该第一半导体封装体及/或该第二半导体封装体是覆晶封装体。
10.如权利要求1所述的方法，其特征在于，该第一半导体封装体及/或该第二半导体封装体是扇出型封装体。
CN201710594258.2A 2016-10-21 2017-07-20 形成堆叠式封装结构的方法 Pending CN107978532A (zh)

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