TWI643268B - 堆疊封裝結構的製造方法 - Google Patents

堆疊封裝結構的製造方法 Download PDF

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TWI643268B
TWI643268B TW106135874A TW106135874A TWI643268B TW I643268 B TWI643268 B TW I643268B TW 106135874 A TW106135874 A TW 106135874A TW 106135874 A TW106135874 A TW 106135874A TW I643268 B TWI643268 B TW I643268B
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conductive
package structure
spacer
sealing body
circuit carrier
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TW106135874A
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TW201828371A (zh
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王啓安
徐宏欣
藍源富
許獻文
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力成科技股份有限公司
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Abstract

本發明提供一種堆疊封裝結構的製造方法，其包含至少以下步驟。接合晶粒於第一電路載體上。設置間隔件在晶粒上。透過多個導電線連接間隔件和第一電路載體。形成密封體以密封晶粒、間隔件以及導電線。減少密封體的厚度直到移除導電線中的每一者的至少一部分以形成第一封裝結構。在第一封裝結構上堆疊第二封裝結構。第二封裝結構電性連接到導電線。

Description

堆疊封裝結構的製造方法
本發明是有關於一種封裝（package）結構的製造方法，且特別是有關於一種堆疊封裝（package-on-package，POP）結構的製造方法。
為了使電子產品設計實現輕、薄、短和小，半導體封裝技術持續發展，嘗試開發出體積較小、重量較輕、整合度較高且在市場中更有競爭性的產品。舉例來說，已經開發例如POP等3D堆疊（3D stacking）技術來滿足較高封裝密度的要求。因此，如何以較低製造成本實現更薄的POP結構已經變為本領域中的研究人員的挑戰。
本發明提供一種堆疊封裝（POP）結構的製造方法，其減少了結構的總體厚度和製造成本。
本發明提供一種POP結構的製造方法。所述方法至少包含以下步驟。接合晶粒於第一電路載體上。設置間隔件在晶粒上。透過多個導電線連接間隔件和第一電路載體。形成密封體以密封晶粒、間隔件以及導電線。減少密封體的厚度直到移除導電線中的每一者的至少一部分以形成第一封裝結構。在第一封裝結構上堆疊第二封裝結構。第二封裝結構電性連接到導電線。
在本發明的一實施例中，晶粒透過覆晶接合電性連接到第一電路載體。
在本發明的一實施例中，間隔件透過黏著層接合到晶粒。
在本發明的一實施例中，導電線是透過打線機形成。
在本發明的一實施例中，在減少密封體的厚度之前，導電線中的每一者的第一焊接區段與第一電路載體之間的角度大於導電線中的每一者的第二焊接區段與間隔件之間的角度。
在本發明的一實施例中，在減少密封體的厚度之後，密封體暴露出導電線的第一焊接區段中的每一者的一部分以及導電線的第二焊接區段中的每一者的一部分。
在本發明的一實施例中，間隔件透過熱黏著層接合到晶粒。
在本發明的一實施例中，在減少密封體的厚度之前，導電線中的每一者的焊接區段與第一電路載體之間的角度大於導電線中的每一者的犧牲區段與間隔件之間的角度。
在本發明的一實施例中，在減少密封體的厚度之後，密封體暴露出導電線的焊接區段中的每一者的一部分。
基於上述，設置於晶粒上的間隔件有利於形成導電線。另外，由於密封體的厚度減少且導電線中的每一者的至少一部分也被移除以形成第一封裝結構，因此在密封體中的導電線的剩餘部分可以作為第一封裝結構與第二封裝結構之間的電性連接路徑。換句話說，不必在第一封裝結構與第二封裝結構之間設置額外的中介層（interposer）用於電性連接。因此，可以減少POP結構的總體厚度且可以實現較低的製造成本。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A到圖1F是說明根據本發明的實施例的POP結構的製造方法的剖面示意圖。參考圖1A，提供第一電路載體（circuit carrier）110。第一電路載體110可具有頂部表面S1以及與頂部表面S1相對的底部表面S2。舉例來說，第一電路載體110可包含核心層（core layer）、設置於頂部表面S1上的頂部電路層114以及設置於第一電路載體110的底部表面S2上的底部電路層116。核心層112設置於頂部電路層114與底部電路層116之間且電性連接頂部電路層114和底部電路層116。在一些實施例中，頂部電路層114和底部電路層116可以分別包含用於進一步電性連接的多個導電接墊（conductive pad）114a和116a。此外，導電接墊114a和導電接墊116a可以由相同材料和相同製程形成，例如透過微影（photolithography）和蝕刻（etching）製程使用銅、焊料、金、鎳或類似物。在一些其它實施例中，導電接墊114a和導電接墊116a可以根據設計要求而由不同材料和/或不同製程形成。
核心層112可進一步包含多個嵌入電路層，其作為電性連接到頂部電路層114和底部電路層116的中間電路層。核心層112可包含基底層（base layer）以及穿過所述基底層的多個導電通孔（conductive vias）。核心層112的導電通孔的兩個相對末端可以電性連接到頂部電路層114的導電接墊114a和底部電路層116的導電接墊116a。在一些實施例中，第一封裝結構100可包含形成於第一封裝結構100的底部表面S2上的多個導電結構118。舉例來說，導電結構118的材料可以包含銅、錫、金、鎳或其它合適的導電材料。導電結構118可以例如為導電凸塊（conductive bump）、導電柱（conductive pillar）或者透過植球製程（ball placement process）和回焊製程（reflow process）形成的焊球（solder ball）。可以利用導電結構118的其它可能的形式和形狀用於進一步電性連接。在一些實施例中，導電結構118可以形成陣列，所述陣列被佈置成在第一電路載體110的底部表面S2上具有微間距以用於後續製程中的需求。
第一晶粒（die）120可以設置於第一電路載體110的頂部表面S1上。第一晶粒120可以透過覆晶接合（flip-chip bonding）電性連接到第一電路載體110。在一些實施例中，第一晶粒120的主動面（未示出）透過多個導電凸塊122耦合到第一電路載體110的頂部電路層114的導電接墊114a。導電凸塊122可以是銅凸塊（copper bumps）。在一些實施例中，焊料（未示出）可以施加到導電凸塊122的表面上以與導電接墊114a耦合。第一晶粒120可以是例如特殊應用積體電路（Application-Specific Integrated Circuit，ASIC）。在一些實施例中，第一晶粒120可用以執行邏輯應用（logic applications），但本發明並不以此為限。其它合適的主動裝置也可以用作第一晶粒120。
參考圖1B，間隔件（spacer）130設置於第一晶粒120上。另外，間隔件130透過黏著層（adhesive layer）140接合到第一晶粒120。在一些實施例中，黏著層140可以是晶粒附著膜（die attach film）或由包含環氧樹脂（epoxy resin）的黏合劑組合物形成。黏著層140可以透過例如旋塗（spin coating）、噴墨印刷（inject printing）等方法或用於提供結構支撐的其它合適方法而形成，而不需要第一晶粒120與間隔件130之間的機械夾持。
間隔件130可包含第二電路載體132，在與第一晶粒120相對的表面上具有導電接墊，以用於後續接合製程。可以利用其它合適形式的間隔件130，且在後續其它實施例中將描述細節。在一些實施例中，間隔件130可以作為虛設晶片（dummy chip），用於執行後續線接合製程和/或提供間隔件功能，以防止對第一晶粒120的損壞。間隔件130的大小和厚度可以不解釋為對第一晶粒120的單元大小和單元厚度的限制。在一些實施例中，間隔件130可以是具有與其中未形成有主動裝置的晶片相似的形狀或外觀的半導體載體。在一些其它實施例中，當整個製造過程完成時，間隔件130和第一晶粒120可以機械地耦合但彼此電性隔離（electrically isolated）。
參考圖1C，間隔件130和第一電路載體110透過多個導電線150連接。舉例來說，導電線150可以透過打線機（wire bonder）（未示出）形成。打線機的類型可包含根據設計要求的楔型接合（wedge bond）、球型接合（ball bond）或其它合適的打線機。此外，導電線150連接於間隔件130的第二電路載體132與第一電路載體110之間。導電線150的材料可以是金、銅或其它合適的材料，但不限於此。在一些實施例中，導電線150中的每一者可包含第一焊接區段152、犧牲區段（sacrificial segment）154以及第二焊接區段156。導電線150的第一焊接區段152中的每一者耦合到第一電路載體110，且導電線150的第二焊接區段156中的每一者耦合到間隔件130的第二電路載體132。導電線150是從第一電路載體110形成到間隔件130。此外，導電線150的犧牲區段154中的每一者形成於第一焊接區段152中的任一者與第二焊接區段156中的任一者之間。換句話說，導電線150中的每一者可以由第一焊接區段152、犧牲區段154以及第二焊接區段156的順序形成。
在一些實施例中，打線機可包含焊接導電線150的自動化裝置。舉例來說，透過例如瓷嘴（capillary）（未示出）等接合工具（bonding tool），其施加熱、超聲波能量、壓力或其組合饋送（feed）導電線150中的每一者，以將導電線150中的每一者接合於第一電路載體110與間隔件130之間。在一些實施例中，每條導電線150的第一焊接區段152可以包含接合到第一電路載體110的焊接部分152a以及耦合到焊接部分152a的線部分152b。舉例來說，每個第一焊接區段152中的焊接部分152a可以取決於設計要求，透過球型接合、楔型接合或其它合適的接合而形成。在將焊接部分152a接合到第一電路載體110的頂部表面S1之後，耦合到焊接部分152a的每個第一焊接區段152中的線部分152b可以透過打線機的接合工具而被遞送出（deliver out）。舉例來說，打線機的接合工具可以按垂直的方式從第一電路載體110向上移動，以形成線部分152b。
接著，接合工具可以在向上遠離第一電路載體110且朝向間隔件130的方向上移動，以形成犧牲區段154。每條導電線150中的犧牲區段154可以形成為弧形（arc shape）。另外，導電線150中的每一者的線弧（loop）高度H1可以是犧牲區段154的弧形的頂端（peak）與耦合到第一電路載體110的第一焊接區段152的焊接部分152a的底端之間的距離。線弧高度H1可以取決於打線機的類型和/或設計要求，但不限於此。隨後，打線機的接合工具可以定位在間隔件130的第二電路載體132的導電接墊處，且可以形成每條導電線150的第二焊接區段156中的尾部接合（tail bond），以接合第二電路載體132。因此，第一電路載體110和間隔件130的第二電路載體132上的線接合製程完成。
在一些實施例中，每條導電線150中的第一焊接區段152與第一電路載體110之間的角度θ1大於或等於每條導電線150中的第二焊接區段156與間隔件130之間的角度θ2。角度θ1可以取決於打線接合的類型和/或設計要求。舉例來說，球型打線機在第一電路載體110的導電接墊114a上焊接導電球（conductive ball）至引線，每條導電線150的引線以直角延伸遠離導電球。然而，對於楔型打線機，在一些實施例中，導電線150的引線側面被按壓抵靠著，因此導電線150的第一焊接區段152中的每一者與第一電路載體110的頂部表面S1之間的角度θ1可以小於90度，但實質上接近於90度。在一些其它實施例中，導電線150的第二焊接區段156中的每一者可以垂直於間隔件130。因此，角度θ2可以是90度或實質上接近於90度。
參考圖1D，密封體（encapsulant）160形成於第一電路載體110的頂部表面S1上，以密封第一晶粒120、間隔件130、黏著層140以及導電線150。在一些實施例中，密封體160的厚度T1大於導電線150中的每一者的線弧高度H1。密封體160可包含由模製製程（molding process）形成的模製化合物（molding compound）。在一些實施例中，密封體160可以透過例如環氧樹脂或其它合適的樹脂等絕緣材料形成。然而，其在本發明中並不解釋為限制。
參考圖1E，減少密封體160的厚度T1直到導電線150中的每一者的至少一部分被移除，以形成第一封裝結構100。舉例來說，密封體160的厚度T1減少到如圖1E中所示的厚度T2。當密封體160的厚度T1減少時，可以移除導電線150的犧牲區段154。另外，密封體160可以暴露出每條導電線150的第一焊接區段152中的一部分以及每條導電線150的第二焊接區段156中的一部分。換句話說，由於導電線150的犧牲區段154被移除，而第一焊接區段152的所述部分和第二焊接區段156的所述部分保留在密封體160中，因此導電線150不再是連續線。在此條件下，間隔件130不再透過導電線150耦合到第一電路載體110。因此，間隔件130不再電性連接到第一電路載體110。換句話說，在減少密封體160的厚度T1之後，間隔件130作為虛設間隔件。
在一些實施例中，密封體160可以透過研磨製程（grinding process）移除。此外，研磨製程可以是機械研磨、化學機械拋光（chemical mechanical polishing，CMP）、蝕刻或其它合適的方法，但不限於此。此外，在減少密封體160的厚度T1之後，密封體160暴露出每個第一焊接區段152中的線部分152b的頂部表面以及每個第二焊接部分156中的頂部表面。在一些實施例中，在減少密封體160的厚度T1之後，每個第一焊接區段152中的線部分152b的頂部表面、每個第二焊接部分156中的頂部表面以及密封體160的頂部表面可以是共面的。其中，密封體160的頂部表面可以是最遠離第一電路載體110的表面。換句話說，在減少密封體160的厚度T1之後，第一焊接區段152中的每一者的高度H2等於密封體160的厚度T2。
在一個實施例中，在減少密封體160的厚度T1之後，線部分152b的頂部表面可以用於與第一電路載體110的進一步電性連接。第二焊接部分156中的每一者的頂部表面可以是虛設路徑。在一些其它實施例中，在減少密封體160的厚度T1之後，每個第一焊接區段152中的線部分152b的頂部表面以及每個第二焊接部分156中的頂部表面可以作為導電路徑，以用於根據設計要求的進一步電性連接。另外，如圖1E中所示的厚度減少製程能夠幫助整體封裝結構中的總厚度減少，從而實現封裝小型化。
參考圖1F，第二封裝結構200堆疊於第一封裝結構100上以形成堆疊封裝（POP）結構10。舉例來說，第二封裝結構200電性連接到第一封裝結構100的導電線150。在一些實施例中，第二封裝結構200可包含第二晶粒202，例如動態隨機存取記憶體（DRAM）或NAND快閃記憶體。在一些其它實施例中，第二封裝結構200中也可以利用其它主動裝置。在一些實施例中，第二封裝結構200可包含多個導電端子204，作為第二封裝結構200與第一封裝結構100之間的電性連接路徑。此外，在一些實施例中，第二晶粒202和導電端子204可以透過類似連接於第一晶粒120與導電結構118之間的電路層而電性連接。
在一個實施例中，第二封裝結構200可包含中心區（central region）CR以及圍繞中心區CR的外圍區（peripheral region）PR。舉例來說，第二晶粒202可以位於中心區CR中，且導電端子204可以設置於外圍區PR中。此外，當第二封裝結構200堆疊於第一封裝結構100上時，第二封裝結構200的中心區CR中的第二晶粒202可以對應於第一封裝結構100的第一晶粒120而設置。另外，第二封裝結構200的外圍區PR中的導電端子204中的每一者可以分別設置於由第一封裝結構100的密封體160暴露的導電線150的第一焊接區段152中的任一者上。在一個實施例中，第二封裝結構200的中心區CR中的第二晶粒202可以交錯於第一封裝結構100的第一晶粒120。在另一實施例中，導電端子204可以設置於中心區CR和外圍區PR兩者中，以用於電性連接到第一封裝結構100。在一些實施例中，導熱層（thermal conductive layer）（未示出）可以被設置成熱接觸（thermal contact）或熱耦合（thermal coupled）於第二封裝結構200與第一封裝結構100之間，以用於增強散熱效率。因此，在後續可靠性測試期間施加到POP結構10上的應力可以由導熱層分擔，以用於增加POP結構10的可靠性。
由於第一焊接區段152可以作為第一封裝結構100與第二封裝結構200之間的電性連接路徑，因此可省略用於第一封裝結構100與第二封裝結構200之間的電性連接的額外中介層。從而可以減少POP結構10的總體厚度和製造成本。
圖2A到圖2F是說明根據本發明的另一實施例的POP結構的製造方法的剖面示意圖。參考圖2A，提供第一電路載體110且第一晶粒120接合於第一電路載體110上。圖2A的實施例類似於圖1A的實施例，因此在此省略詳細描述。
參考圖2B，間隔件330設置於第一電路載體110上且接合到第一晶粒120。舉例來說，間隔件330包含作為散熱金屬板的導電板332。另外，間隔件330的導電板332可適合於執行後續的打線接合製程。導電板332的材料可包含導熱及導電材料，例如鋁、銅或其合金。然而，導電板332的材料取決於設計要求，其在本發明中並不解釋為限制。
此外，熱黏著層（thermal adhesive layer）340可以設置於第一晶粒120與間隔件330之間。在一些實施例中，熱黏著層340可包含擁有高熱導率的晶粒附接組合物，例如銀、覆銀（silver coated）或鋁氮化物顆粒（aluminum nitride particles），其透過例如旋塗、噴墨印刷或其它合適的方法形成。然而，熱黏著層340的材料和形成製程在本發明中並不解釋為限制。熱黏著層340可以作為從第一晶粒120到間隔件330的直接熱傳導路徑，並且在從第一晶粒120產生熱的期間進一步增強散熱效率。此外，熱黏著層340可以提供結構支撐而不需要第一晶粒120與間隔件330之間的機械夾持。
參考圖2C，間隔件330和第一電路載體110透過多個導電線350連接。導電線350的材料和形成方法可以類似於圖1C中所示的導電線150的材料和形成方法。在此省略了詳細描述。在本實施例中，導電線350可以連接於間隔件330的導電板332與第一電路載體110之間。另外，導電線350中的每一者可包含連接到第一電路載體110的焊接區段352以及連接於焊接區段352與間隔件330之間的犧牲區段354。換句話說，導電線350透過焊接區段352從第一電路載體110透過犧牲區段354連接到間隔件330。
另外，導電線350的焊接區段352中的每一者可包含耦合到第一電路載體110的焊接部分352a以及耦接到焊接部分352a的線部分352b。舉例來說，每個焊接區段352中的的焊接部分352a可以取決於設計要求而透過球型接合、楔型接合或其它合適的接合而形成。焊接區段352的焊接部分352a和線部分352b的形成製程可以類似於圖1C中說明的第一焊接區段152的焊接部分152a和線部分152b的形成製程，在此省略了詳細描述。
導電線350的犧牲區段354中的每一者可包含弧形（arc-shape）部分354a以及尾部（tail）部分354b。犧牲區段354的形成製程可以類似於導電線150的犧牲區段154和第二焊接區段156的形成製程。這裡省略了詳細描述。另外，導電線350中的每一者的線弧高度H3可以是犧牲區段354的弧形部分354a的頂端與耦合到第一電路載體110的第一焊接區段352的焊接部分352a的底端之間的距離。線弧高度H3取決於打線機的類型和/或設計要求，但不限於此。
在一些實施例中，導電線350中的每一者的焊接區段352與第一電路載體110之間的角度θ3大於導電線350中的每一者的犧牲區段354與間隔件330之間的角度θ4。類似於圖1C中說明的實施例，在本實施例中，角度θ3（類似於角度θ1）和角度θ4（類似於角度θ2）可以取決於線接合的類型和/或設計要求。
參考圖2D，密封體160形成於第一電路載體110上，以密封第一晶粒120、間隔件330、黏著層340以及導電線350。圖2D中說明的實施例的製程類似於圖1D中說明的實施例的製程，在此省略了詳細描述。參考圖2E，減少密封體160的厚度T1直到移除導電線350中的每一者的至少一部分，以形成第一封裝結構300。圖2E中說明的實施例的減少方法類似於圖1E中說明的實施例的減少方法，在此省略了詳細描述。
在本實施例中，導電線350的犧牲區段354被移除。舉例來說，密封體160的厚度T1減少到如圖2E中所示的厚度T3。另外，在減少密封體160的厚度T1之後，密封體160暴露出間隔件330的導電板332的頂部表面332a。此外，密封體160暴露出每條導電線350的焊接區段352中的線部分352b的頂部表面。換句話說，導電線350的犧牲區段354被移除，而焊接區段352的一部分保留在密封體160中。在此條件下，間隔件330不連接到導電線350，並且不再透過導電線350電性連接到第一電路載體110。因此，間隔件330不再電性連接到第一電路載體110。在一些實施例中，在減少密封體160的厚度T1之後，每個焊接區段352中的線部分352b的頂部表面、間隔件330的導電板332的頂部表面332a以及密封體160的頂部表面是共面的。其中，密封體160的頂部表面可以是最遠離第一電路載體110的表面。換句話說，在減少密封體160的厚度T1之後，焊接區段352中的每一者的高度H4等於密封體160的厚度T3。另外，如圖2E中所示的厚度減少製程能夠輔助封裝結構整體的總厚度減少，從而實現封裝小型化。此外，包含導電板332的間隔件330可以首先作為用於形成導電線350的導電接合墊，如圖2D中所示。隨後，由於在減少密封體160的厚度T1之後移除了導電線350的犧牲區段354，因此，間隔件330是電性浮置的（electrically floated）。據此，包含導電板332的間隔件330可以用作第一封裝結構300中的散熱元件。
參考圖2F，第二封裝結構200堆疊於第一封裝結構300上，以形成POP 結構20。舉例來說，第二封裝結構200電性連接到第一封裝結構100的導電線350。在一些實施例中，當第二封裝結構200堆疊於第一封裝結構300上時，第二封裝結構200的中心區CR中的第二晶粒202可以對應於第一封裝結構300的第一晶粒120而設置。另外，第二封裝結構200的外圍區PR中的導電端子204中的每一者可以設置於被密封體160暴露出的第一封裝結構300的導電線350的焊接區段352中的任一者上。在一個實施例中，第二封裝結構200的中心區CR中的第二晶粒202可以交錯於第一封裝結構300的第一晶粒120。在另一實施例中，導電端子204可以設置於第二封裝結構200的中心區CR和外圍區PR兩者中，以電性連接到第一封裝結構300。
基於上述，設置於晶粒上的間隔件有利於導電線的形成製程。此外，由於在減少密封體的厚度期間移除導電線的至少一部分，因此，保留在密封體中的導電線的其餘部分可以作為第一封裝結構與第二封裝結構之間的電性連接路徑。因此，在第一封裝結構與第二封裝結構之間不必額外設置用於電性連接的中介層。因此，不僅可以減少POP結構的總體厚度，也可以減少製造成本。另外，密封體可以暴露出間隔件，因此在減少密封體的厚度之後，間隔件可以作為散熱元件。據此，可以開啟各種POP結構設計的可能性。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10、20‧‧‧堆疊封裝結構
100、300‧‧‧第一封裝結構
110‧‧‧第一電路載體
112‧‧‧核心層
114‧‧‧頂部電路層
114a、116a‧‧‧導電接墊
116‧‧‧底部電路層
118‧‧‧導電結構
120‧‧‧第一晶粒
122‧‧‧導電凸塊
130、330‧‧‧間隔件
132‧‧‧第二電路載體
140‧‧‧黏著層
150‧‧‧導電線
152‧‧‧第一焊接區段
152a‧‧‧焊接部分
152b、352b‧‧‧線部分
154、354‧‧‧犧牲區段
156‧‧‧第二焊接區段
160‧‧‧密封體
200‧‧‧第二封裝結構
202‧‧‧第二晶粒
204‧‧‧導電端子
332‧‧‧導電板
332a‧‧‧頂部表面
340‧‧‧熱黏著層
350‧‧‧導電線
352‧‧‧焊接區段
352a‧‧‧焊接部分
354a‧‧‧弧形部分
354b‧‧‧尾部部分
CR‧‧‧中心區
H1、H2、H3、H4‧‧‧高度
PR‧‧‧外圍區
S1‧‧‧頂部表面
S2‧‧‧底部表面
T1、T2‧‧‧厚度
θ1、θ2、θ3、θ4‧‧‧角度
圖1 A到圖1F是說明根據本發明的實施例的POP結構的製造方法的剖面示意圖。 圖2 A到圖2F是說明根據本發明的另一實施例的POP結構的製造方法的剖面示意圖。

Claims (9)

  1. 一種堆疊封裝結構的製造方法，包括：接合晶粒於第一電路載體上；設置間隔件在所述晶粒上，其中所述間隔件包括第二電路載體；通過多個導電線連接所述間隔件和所述第一電路載體；形成密封體以密封所述晶粒、所述間隔件以及所述導電線；減少所述密封體的厚度直到移除所述導電線中的每一者的至少一部分以形成第一封裝結構，其中在減少所述密封體的所述厚度之前，所述導電線連接於所述第二電路載體與所述第一電路載體之間；以及堆疊第二封裝結構在所述第一封裝結構上，其中所述第二封裝結構電性連接到所述導電線。
  2. 如申請專利範圍第1項所述的堆疊封裝結構的製造方法，其中在減少所述密封體的所述厚度之前，所述導電線中的每一者包括連接到所述第一電路載體的第一焊接區段以及連接到所述間隔件的第二焊接區段，所述導電線通過所述第一焊接區段從所述第一電路載體通過所述第二焊接區段連接到所述間隔件。
  3. 如申請專利範圍第2項所述的堆疊封裝結構的製造方法，其中在減少所述密封體的所述厚度之前，所述導電線中的每一者進一步包括連接於所述第一焊接區段與所述第二焊接區段之間的犧牲區段，當減少所述密封體的所述厚度時，所述導電線的所述犧牲區段被移除，在移除所述導電線的所述犧牲區段之後，所述間隔件是電性浮置的。
  4. 如申請專利範圍第3項所述的堆疊封裝結構的製造方法，其中所述第二封裝結構包括多個導電端子，所述第二封裝結構的所述導電端子中的每一者分別設置於由所述密封體暴露的所述導電線的所述第一焊接區段中的任一者上。
  5. 如申請專利範圍第1項所述的堆疊封裝結構的製造方法，其中所述間隔件包括導電板。
  6. 如申請專利範圍第5項所述的堆疊封裝結構的製造方法，其中在減少所述密封體的所述厚度之後，所述間隔件的表面從所述密封體暴露。
  7. 如申請專利範圍第5項所述的堆疊封裝結構的製造方法，其中在減少所述密封體的所述厚度之前，所述導電線中的每一者包括連接到所述第一電路載體的焊接區段以及連接於所述焊接區段與所述間隔件之間的犧牲區段，所述導電線通過所述焊接區段從所述第一電路載體通過所述犧牲區段連接到所述間隔件。
  8. 如申請專利範圍第7項所述的堆疊封裝結構的製造方法，其中當減少所述密封體的所述厚度時，所述導電線的所述犧牲區段被移除，在移除所述導電線的所述犧牲區段之後，所述間隔件是電性浮置的。
  9. 如申請專利範圍第6項所述的堆疊封裝結構的製造方法，其中所述第二封裝結構包括多個導電端子，所述第二封裝結構的所述導電端子中的每一者分別設置於由所述密封體暴露的所述焊接區段中的任一者上。
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