TWI635588B - 封裝中具有不同厚度的熱界面材料 - Google Patents

封裝中具有不同厚度的熱界面材料 Download PDF

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Publication number
TWI635588B
TWI635588B TW106128495A TW106128495A TWI635588B TW I635588 B TWI635588 B TW I635588B TW 106128495 A TW106128495 A TW 106128495A TW 106128495 A TW106128495 A TW 106128495A TW I635588 B TWI635588 B TW I635588B
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Taiwan
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package
device die
metal cover
thermal interface
interface material
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TW106128495A
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English (en)
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TW201903996A (zh
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黃松輝
余大全
李祥帆
黃冠育
李百淵
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台灣積體電路製造股份有限公司
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Publication of TWI635588B publication Critical patent/TWI635588B/zh
Publication of TW201903996A publication Critical patent/TW201903996A/zh

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Abstract

一種封裝包括：封裝組件；裝置晶粒，位於封裝組件上方且結合至封裝組件；金屬蓋體，具有位於裝置晶粒上方的頂部部分；以及熱界面材料，位於裝置晶粒與金屬蓋體之間且接觸裝置晶粒及金屬蓋體。所述熱界面材料包括位於裝置晶粒的內側部分正上方的第一部分及在裝置晶粒的隅角區正上方延伸的第二部分。第一部分具有第一厚度。第二部分具有較第一厚度大的第二厚度。

Description

封裝中具有不同厚度的熱界面材料
本發明是有關於一種封裝結構，特別是有關於一種具有不同厚度的熱界面材料的封裝結構。
在一些三維積體電路(Three-Dimensional Integrated Circuit，3DIC)中，裝置晶粒首先結合至中介層，所述中介層進一步結合至封裝基板以形成封裝。需要將裝置晶粒在其運作期間產生的熱量驅散。在傳統結構中，為了驅散熱量，將裝置晶粒的基板附裝至金屬蓋，所述金屬蓋幫助驅散熱量且亦充當加強材。因此，在裝置晶粒中產生的熱量會傳播至金屬蓋。可將散熱器(heat sink)附裝至金屬蓋以進一步驅散被傳導至金屬蓋的熱量。
藉由可包含環氧系材料的熱界面材料(Thermal Interface Material，TIM)將裝置晶粒附裝至金屬蓋。由於熱界面材料具有相對低的熱導率，因此較佳地，熱界面材料為薄的以使得熱界面材料不會在裝置晶粒與金屬蓋之間引入太多熱阻。
本發明實施例的一種封裝包括第一封裝組件、封裝晶粒、金屬蓋體、熱界面材料。裝置晶粒位於所述第一封裝組件上方且結合至所述第一封裝組件。金屬蓋體包括位於所述裝置晶粒上方的頂部部分。熱界面材料位於所述裝置晶粒與所述金屬蓋體之間且接觸所述裝置晶粒及所述金屬蓋體。所述熱界面材料包括第一部分與第二部分。第一部分位於所述裝置晶粒的內側部分正上方，其中所述第一部分具有第一厚度。第二部分在所述裝置晶粒的隅角區正上方延伸，其中所述第二部分具有較所述第一厚度大的第二厚度。
本發明實施例的一種封裝包括堆疊、金屬蓋體、黏合劑以及熱界面材料。堆疊包括中介層、第一裝置晶粒及第二裝置晶粒、封裝基板以及包封材料。第一裝置晶粒及第二裝置晶粒位於所述中介層上方且結合至所述中介層。封裝基板位於所述中介層之下且結合至所述中介層。包封材料環繞所述第一裝置晶粒與所述第二裝置晶粒中的每一者。金屬蓋體包括頂部部分以及邊緣部分。邊緣部分位於所述頂部部分之下且連接至所述頂部部分。黏合劑將所述邊緣部分黏合至所述封裝基板。熱界面材料包括平面部分與突起部分。平面部分具有實質上均勻的厚度。突起部分自所述平面部分向上或向下突起，其中所述突起部分與所述堆疊的隅角部分交疊。
本發明實施例的一種封裝包括封裝基板、中介層、裝置 晶粒、金屬蓋體以及熱界面材料。中介層位於所述封裝基板上方且結合至所述封裝基板。裝置晶粒位於所述中介層上方且結合至所述中介層。金屬蓋體包括頂部部分與邊緣部分。頂部部分位於所述裝置晶粒上方，其中所述頂部部分包括多個凹槽，所述多個凹槽中的每一者自所述頂部部分的底表面凹陷至所述頂部部分中。邊緣部分環繞所述裝置晶粒及所述中介層，其中所述邊緣部分黏合至所述封裝基板，且所述邊緣部分包括四個側部部分。熱界面材料位於所述裝置晶粒與所述金屬蓋體之間且接觸所述裝置晶粒及所述金屬蓋體，其中所述熱界面材料延伸至所述金屬蓋體的所述頂部部分的所述四個凹槽中。
20、60‧‧‧封裝組件
22‧‧‧基板
22A‧‧‧表面
44A、48A、70TS‧‧‧頂表面
24‧‧‧穿孔
25、27‧‧‧切割道
28‧‧‧互連結構
30、50‧‧‧介電層
32‧‧‧金屬線
34‧‧‧介層窗
38、54‧‧‧電連接器
40、44‧‧‧封裝組件
46、62‧‧‧底部填料
48‧‧‧包封材料
52‧‧‧重佈線層
58、100‧‧‧封裝
61‧‧‧複合晶圓
64‧‧‧金屬焊墊
66‧‧‧焊料區
70‧‧‧金屬蓋體
70A‧‧‧頂部部分
70B‧‧‧環形部分
70BS-1、70BS-2‧‧‧底表面
70BS-2’‧‧‧虛線
70C‧‧‧中心
72、72’、73、74、74’‧‧‧凹槽
75、82‧‧‧虛線
76‧‧‧黏合劑膜
78‧‧‧熱界面材料
78A‧‧‧主要部分
78B‧‧‧隅角部分
80‧‧‧箭頭
200‧‧‧製程流程
202、204、206、208、210、212、214、216‧‧‧步驟
C-C‧‧‧線
D1‧‧‧深度
T1、T2、T3、T4‧‧‧厚度
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1至圖7A及圖7B說明根據一些實施例的封裝的形成過程中的中間階段的剖視圖。
圖8A、圖8B、圖9A及圖9B說明根據一些實施例的封裝形成過程中的中間階段的剖視圖及俯視圖。
圖10A至圖10E說明根據一些實施例的一些封裝的俯視圖。
圖11說明根據一些實施例的形成封裝的製程流程。
以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及配置的具體實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「上方」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、以使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，但自身並不指示所論述的各種實施例及/或配置之間的關係。
另外，為易於說明，本文中可使用例如「在...之下」、「在...下面」、「下部」、「在...上方」、「上部」等空間相對性用語來闡述圖中所示一個元件或特徵與另一(其他)元件或特徵的關係。除了圖中所繪示的定向之外，所述空間相對性用語旨在涵蓋裝置在使用或操作中的不同定向。設備可被另外定向(旋轉90度或處於其他定向)，且本文所用的空間相對性描述詞可同樣相應地進行解釋。
根據各種示例性實施例提供一種包括金屬蓋體、裝置晶粒的封裝、及其形成方法。對形成所述封裝的中間階段進行說明。對一些實施例的變型進行論述。在各個視圖及說明性實施例通篇 中，相同參考編號用於標示相同的元件。
圖1至圖7A說明根據本發明一些實施例的封裝的形成過程中的中間階段的剖視圖。圖1至圖7A所示步驟亦示意性地反映在圖11所示製程流程中。
圖1說明封裝組件20的剖視圖，封裝組件20可為中介層晶圓、封裝基板條、裝置晶粒晶圓、或封裝。封裝組件20包括多個封裝組件40，所述多個封裝組件40可彼此相同。封裝組件40可為裝置晶片(當被鋸開時亦被稱為晶粒，所述裝置晶片可包括主動裝置及/或被動裝置，或可不包括主動裝置及/或被動裝置)、封裝基板、封裝等。在本說明通篇中，作為另一選擇，封裝組件40在下文中被稱為中介層，然而封裝組件40可為以上所述的其他類型的封裝組件。
根據本發明的一些實施例，封裝組件20包括基板22，基板22可為半導體基板，例如矽基板。基板22亦可由例如矽鍺、矽碳等另一半導體材料形成。根據一些實施例，在半導體基板22的表面22A處形成有例如電晶體等主動裝置(圖中未示出)。亦可在封裝組件20中形成例如電阻器及/或電容器等被動裝置(圖中未示出)。根據本發明的替代實施例，基板22可為半導體基板或介電基板，且在各個封裝組件中不包括主動裝置。根據該些實施例，封裝組件20可包括在封裝組件20中所形成的被動裝置或可不包括在封裝組件20中所形成的被動裝置。
可將穿孔(Through-Via，TV)24(作為另一選擇，穿孔 24被稱為金屬柱)形成以自基板22的頂表面22A延伸至基板22中。穿孔24有時亦被稱為基板穿孔或當基板22為矽基板時亦被稱為矽穿孔。在基板22上方形成有互連結構28，且互連結構28用於電性連接至積體電路裝置(若存在)及穿孔24。互連結構28可包括多個介電層30。在介電層30中形成有金屬線32。在上覆金屬線32與下伏金屬線32之間形成有介層窗34且介層窗34將上覆金屬線32與下伏金屬線32互連。根據本發明的一些實施例，介電層30是由氧化矽、氮化矽、碳化矽、氮氧化矽、其組合、及/或其多個層來形成。作為另一選擇，介電層30可包括具有低介電常數(k值)的一或多個低介電常數介電層。舉例而言，介電層30中的低介電常數介電材料的k值可低於約3.0或低於約2.5。
在封裝組件20的頂表面處形成有電連接器38。根據本發明的一些實施例，電連接器38包括金屬支柱，其中可在所述金屬支柱的頂表面上形成焊帽(solder cap)或可不在所述金屬支柱的頂表面上形成焊帽。根據本發明的替代實施例，電連接器38包括焊料區。根據再一些實施例，電連接器38可為銅支柱凸塊、包括銅柱、鎳層、焊帽、無電鍍鎳浸金(Electro-less Nickel Immersion Gold，ENIG)、無電鍍鎳無電鍍鈀浸金(Electro-less Nickel Electro-less Palladium Immersion Gold，ENEPIG)及/或類似物的銅柱凸塊、焊料凸塊或複合凸塊、及/或其組合。
經由例如是覆晶結合(flip-chip bonding)將封裝組件44結合至封裝組件20。相應步驟作為在圖11所示的製程流程200中 的步驟202進行說明。電連接器38因此將封裝組件44中的電路電性耦合至封裝組件20中的金屬線32及穿孔24。封裝組件44可為包括邏輯電路、記憶體電路等的裝置晶粒。因此，作為另一選擇，封裝組件44在下文中被稱為裝置晶粒。作為另一選擇，封裝組件44可為包括與相應中介層、封裝基板、及/或類似元件結合的晶粒的封裝。當電連接器38包括焊料區時執行回焊以將裝置晶粒(封裝組件44)結合至中介層(封裝組件40)。
在中介層(封裝組件40)中的每一者上，可存在結合在中介層(封裝組件40)中的每一者上的一個、兩個、三個或更多個裝置晶粒(封裝組件44)。舉例而言，如圖1所示，將兩個裝置晶粒(封裝組件44)結合至同一中介層(封裝組件40)。根據本發明的一些實施例，裝置晶粒(封裝組件44)包括半導體基板，根據本發明的一些實施例，所述半導體基板可為矽基板。因此，裝置晶粒(封裝組件44)的頂表面44A可為由半導體材料(例如矽)形成的表面。
接下來，由底部填料(underfill)46來填充裝置晶粒(封裝組件44)與封裝組件20之間的間隙。底部填料46可包含聚合物或環氧化物，所述聚合物或環氧化物用於保護電連接器38免遭應力。底部填料46亦可為模製底部填料(molding underfill)，當在圖2所示步驟中對裝置晶粒(封裝組件44)進行包封時分配所述模製底部填料，其中同一模製底部填料在圖2中用作底部填料46及包封材料48兩者。
參考圖2，例如利用壓縮模製、轉移模製等將包封材料48包封於裝置晶粒(封裝組件44)及封裝組件20上。相應步驟作為步驟204在圖11所示製程流程200中進行說明。根據本發明的一些實施例，包封材料48包含模製化合物，所述模製化合物包含基材及混合於基材中的填料。基材可包含聚合物、樹脂、環氧化物、及/或類似材料。填料可由二氧化矽、氧化鋁等的球形顆粒形成。執行固化步驟以將包封材料48固化並凝固，其中所述固化可為熱固化、紫外(Ultra-Violet，UV)固化等。根據一些實施例，將裝置晶粒(封裝組件44)埋置於包封材料48中。
在將包封材料48固化之後，執行例如化學機械拋光(Chemical Mechanical Polish，CMP)或機械研磨等平面化步驟，以移除包封材料48的多餘部分，所述多餘部分位於裝置晶粒(封裝組件44)的頂表面44A上方。相應步驟作為步驟206在圖11所示製程流程200中進行說明。所得結構示於圖3中。因此，裝置晶粒(封裝組件44)中的基板的頂表面44A被暴露出，且與包封材料48的頂表面48A處於同一平面上。
圖4說明封裝組件20的背面結構的形成。相應步驟作為步驟208在圖11所示製程流程200中進行說明。在所述背面結構的形成中，對基板22的背面執行背面研磨以使基板22薄化，直至暴露出穿孔24。在半導體基板22的背面上形成一個介電層(或多個介電層)50。可在介電層50中形成重佈線層(redistribution layer，RDL)52。亦在封裝組件20的背面上形成電連接器54，且 將電連接器54電性耦合至穿孔24。根據本發明的一些實施例，電連接器54為焊料區。根據其他實施例，電連接器54可包括金屬焊墊、金屬凸塊、焊帽等。在本說明通篇中，圖4所示封裝被稱為複合晶圓61。
接下來，沿切割道(scribe line)25/27對複合晶圓61執行單體化(切分)，以將圖4所示的封裝鋸成多個封裝58，所述多個封裝58中的每一者包括封裝組件的堆疊。相應步驟作為步驟208亦在圖11所示製程流程200中進行說明。所得封裝58中的每一者包括中介層(封裝組件40)及結合於中介層(封裝組件40)上的對應裝置晶粒(封裝組件44)中的一者。示例性封裝58的俯視圖示於圖10A中。在所述俯視圖中，包封材料48包括環繞裝置晶粒(封裝組件44)的部分以及位於相鄰的裝置晶粒(封裝組件44)之間的部分。
圖5說明例如經由電連接器54而將封裝58結合至封裝組件60。相應步驟作為步驟210在圖11所示製程流程200中進行說明。封裝組件60可為封裝基板、印刷電路板(Printed Circuit Board，PCB)等。封裝組件60可包括形成於封裝組件60的相對的兩側上的電連接器(例如金屬焊墊64及焊料區66)。封裝組件60的相對兩側上的電連接器經由在封裝組件60內部形成的金屬線及介層窗(圖中未示出)而在內部電性耦合。可將底部填料62分配至封裝58與封裝組件60之間的間隙中並進行固化。根據一些實施例，底部填料62亦具有位於間隙外部的一些外側部分，所 述部分接觸封裝58的外側壁。底部填料62的外側部分可接觸包封材料48或可不接觸包封材料48。
圖6及圖7說明將金屬蓋體70黏合至封裝組件60的頂表面上。參考圖6，金屬蓋體70是由具有高熱導率(例如，高於約100W/m*K)的金屬或金屬合金形成。金屬蓋體70的材料包含金屬或金屬合金。舉例而言，金屬蓋體70可由選自Al、Cu、Ni、Co、不銹鋼、及其合金中的金屬或金屬合金形成。根據本發明的一些實施例，整個金屬蓋體70是由相同的均質金屬材料形成的一體成形件。因此，可不存在將金屬蓋體70的不同部分分離的明顯的界面。
金屬蓋體70包括頂部部分70A及自頂部部分70A的底表面向下延伸的環形部分(邊緣部分)70B。應理解，在頂部部分70A與環形部分70B之間可不具有任何可區分的界面。當在金屬蓋體70的俯視圖中觀察時，環形部分70B可形成完整的環形(如10A至圖10E所示)，其中被環形部分70B環繞的區足夠大以容納封裝58。
頂部部分70A具有頂表面70TS，頂表面70TS可為延伸整個頂部部分70A的平面頂表面。頂部部分70A亦具有底表面70BS-1，根據一些實施例，底表面70BS-1可為最低表面。底表面70BS-1可平行於頂表面70TS，並且底表面70BS-1的俯視圖面積大於金屬蓋體70的俯視圖面積的50%，且可大於金屬蓋體70的俯視圖面積的約80%。
將凹槽72形成為自頂部部分70A的底表面70BS-1延伸至頂部部分70A中。相應步驟作為步驟212在圖11所示製程流程200中進行說明。可藉由磨削、壓印、切割、鋸開、研磨、蝕刻等來形成凹槽72。作為另一選擇，凹槽72是在金屬蓋體70形成時就已經，而非在金屬蓋體70形成之後才形成。因此，使用虛線框來說明圖11中的步驟212，以表示可能不需要執行此步驟。經由凹槽72亦暴露出頂部部分70A的底表面70BS-2。根據本發明的一些實施例，底表面70BS-2為平面的且平行於頂表面70TS。根據替代實施例，底表面70BS-2為筆直的但為傾斜的，如由虛線70BS-2’示意性所示，其中凹槽72的深度自較靠近環形部分70B的部分往較靠近金屬蓋體70的中心70C的部分越來越深。
根據本發明的一些實施例，進一步將凹槽74形成為自金屬蓋體70的底表面70BS-1延伸至金屬蓋體70中。圖10A說明自環形部分70B的一個側部部分延伸至相對的側部部分的示例性凹槽74。凹槽74的總數及位置與裝置晶粒(封裝組件44)的數目及其位置有關，此將在隨後段落中進行論述。根據本發明的替代實施例，不形成凹槽74，且除了凹槽72的形成位置外的金屬蓋體70的整個底表面處於同一平面上。因此，在圖10A至圖10E中凹槽74被標記為虛線，以指示可形成凹槽74或可不形成凹槽74。
返回參考圖6，凹槽72的深度D1可為實質上均勻的，或可端視凹槽72的量測位置而變化。根據本發明的一些實施例，凹槽72的深度D1大於約10微米或大於約20微米，且可介於約 30微米與約70微米之間的範圍內，其中在凹槽72的深度D1不均勻時，深度D1為凹槽72的最大深度。應理解，凹槽72的深度D1與頂部部分70A的厚度有關，且頂部部分70A的厚度越大，凹槽72可越深。在本發明的示例性實施例中，頂部部分70A的厚度T1介於約0.5毫米與約3毫米之間的範圍內。
將黏合劑膜76黏合至環形部分70B的底表面。在金屬蓋體70的仰視圖中，黏合劑膜76可具有完整的環形形狀。將熱界面材料(TIM)78分配在裝置晶粒(封裝組件44)的頂部及包封材料48的頂部上。相應步驟作為步驟214在圖11所示製程流程200中進行說明。熱界面材料78具有良好的熱導率，所述熱導率可大於約2W/m * K，且可等於或高於約10W/m * K或50W/m * K。熱界面材料78可包含聚合物、樹脂、或環氧化物作為基材，且包含填料以提高其熱導率。填料可包括例如氧化鋁、氧化鎂、氮化鋁、氮化硼、及金剛石粉末等介電填料。填料亦可為例如銀、銅、鋁等金屬填料。填料可為球形顆粒形式。
如由箭頭80表示，將金屬蓋體70推壓成抵靠封裝組件60，以經由黏合劑膜76將金屬蓋體70黏合至封裝組件60。相應步驟作為步驟216在圖11所示製程流程200中進行說明。所得封裝在下文中被稱為封裝100。亦將底表面70BS-1及底表面70BS-2推壓成抵靠熱界面材料78，以使得熱界面材料78的位於裝置晶粒(封裝組件44)及包封材料48正上方的部分具有與底表面70BS-1及70BS-2接觸的頂表面。所得結構示於圖7A中。接著例如在熱 固化製程中將熱界面材料78固化並凝固。
熱界面材料78包括具有厚度T2的主要部分78A(較薄的部分)以及具有較厚度T2大的厚度T3的隅角部分78B(較厚的部分)。熱界面材料部分(隅角部分78B)包括延伸至凹槽72中的部分及位於凹槽72正下方的部分。熱界面材料78因此亦可被設想成具有較薄的平面部分、以及突起部分，所述較薄的平面部分貫穿裝置晶粒(封裝組件44)及包封材料48擴展，所述突起部分自較薄的平面部分向上突起至凹槽72及凹槽74中。使熱界面材料78的主要部分78A薄化可減小金屬蓋體70與裝置晶粒(封裝組件44)之間的熱阻，且因此由裝置晶粒(封裝組件44)產生的熱量可被驅散至金屬蓋體70中而不會經受過量的熱阻。根據一些實施例，厚度T2小於約90微米，且可介於約50微米與約90微米之間的範圍內。厚度差(T3-T2)可大於約10微米或大於約20微米，且可介於約30微米與約70微米之間的範圍內。應理解，若不形成凹槽72及凹槽74，則熱界面材料78的位於裝置晶粒(封裝組件44)及包封材料48正上方的整個部分將具有小的厚度T2。在封裝製程中，封裝可經歷多個熱循環，從而導致金屬蓋體70、熱界面材料78、及封裝58彎曲。因此可能在熱界面材料78與下伏裝置晶粒(封裝組件44)之間發生分層及裂縫。分層及裂縫在封裝58的隅角處亦為嚴重的，乃因該些區中的應力高於其他區中的應力。藉由使熱界面材料78在隅角處的部分變得更厚，會提高熱界面材料78吸收應力的能力，且發生分層及裂縫的可能性亦會 降低。
圖10A說明根據各種實施例的封裝100的俯視圖，其中可自圖10A至圖10E所示包括線C-C的平面獲得圖7A所示剖視圖。參考圖10A作為實例，對凹槽72的相對位置及大小(相對於環形部分70B及封裝58)進行說明。根據一些實施例，凹槽72自金屬蓋體70的環形部分70B朝向金屬蓋體70的中心70C延伸。凹槽72覆蓋封裝58的至少隅角部分。根據一些實施例，凹槽72覆蓋裝置晶粒(封裝組件44)及包封材料48兩者的隅角部分。根據替代實施例，凹槽72覆蓋包封材料48的隅角部分，但不在裝置晶粒(封裝組件44)的隅角部分正上方延伸，其中虛線82示意性地說明相應凹槽72的內邊緣。
亦如圖10A所示，在相鄰的裝置晶粒(封裝組件44)之間的間隙正上方形成有凹槽74。凹槽74可一直延伸至環形部分70B的相對的兩個側部部分(所示的頂側部分及底側部分)。凹槽74的寬度可等於、小於、或大於裝置晶粒(封裝組件44)之間的間隙的寬度。因此，參考圖7A，凹槽74可被限制於位於裝置晶粒(封裝組件44)之間的間隙正上方的區中，或在橫向上擴展以覆蓋裝置晶粒(封裝組件44)的邊緣部分。由於凹槽74的形成，熱界面材料78亦具有位於裝置晶粒(封裝組件44)之間的間隙正上方的厚的部分，且因此提供更大體積的熱界面材料78以對此區中的應力進行緩衝。熱界面材料78的位於間隙正上方的部分的厚度T4可大於、等於、或小於厚度T3。
在圖7A中，凹槽72的內邊緣是彎曲的，此可幫助減輕應力。根據替代實施例，如圖7B所示，凹槽72的內邊緣是筆直的及垂直的。
圖8A、圖8B、圖9A、及圖9B說明根據本發明一些實施例的封裝100形成過程中的中間階段的剖視圖。除了凹槽被形成為延伸至封裝58中而非延伸至金屬蓋體70的頂部部分70A中以外，該些實施例類似於圖1至圖7A/7B所示實施例。除非另外指明，否則該些實施例中的組件的材料及形成方法本質上相同於圖1至圖7A/7B所示實施例中的由相同參考編號指出的相同組件。因此關於圖8A、圖8B、圖9A、及圖9B所示組件的形成過程及材料的細節可見於對圖1至圖7A/7B所示實施例的論述中。
該些實施例的初始步驟本質上相同於圖1至圖4所示者。接下來，如圖8A所示，形成延伸至複合晶圓61中的凹槽72’及凹槽74’。可藉由(利用刀片)切割、磨削、研磨等來形成凹槽72’及凹槽74’，其中裝置晶粒(封裝組件44)的頂部隅角部分及包封材料48的頂部隅角部分被移除。因此，可在晶圓層面上執行凹槽72’及凹槽74’的形成，且凹槽72’延伸至相鄰的封裝58中。
圖8B說明複合晶圓61的俯視圖，複合晶圓61包括藉由切割道25及切割道27而彼此分離的未單體化封裝58。如圖8B所示，凹槽72’可被形成為分離的凹槽，凹槽72’中的每一者位於四個封裝58的接點處。凹槽72’中的每一者可與切割道25中的一者及切割道27中的一者交叉，且可在裝置晶粒(封裝組件44，圖 8B中未示出，參考圖10A)的上方延伸。凹槽74’可被形成為長條形凹槽，凹槽74’中的每一者與封裝58的所有行交叉。
接下來，沿切割道25及切割道27將複合晶圓61單體化以產生封裝58，其中在圖9A中對封裝58中的一者進行說明。接著藉由熱界面材料78將金屬蓋體70附裝至封裝58。類似地，熱界面材料78包括分別具有厚度T2及厚度T3的較薄的部分(主要部分78A)及較厚的部分(隅角部分78B)。根據該些實施例，熱界面材料78可被視為具有平面部分及突起部分，所述平面部分在整個封裝58上方擴展，所述突起部分自平面部分向下突起至封裝58中的凹槽72’及凹槽74’中。如圖9A所示，熱界面材料78的突起部分的底表面可為平面的，且平行於金屬蓋體70的頂部部分70A的頂表面70TS。圖9B說明其中凹槽72’的底表面為傾斜的且可能為筆直的或彎曲的實施例。除了用於形成凹槽的工具可具有不同的形狀以外，可利用與圖8A及圖8B所示本質上相同的方法來形成圖9B所示封裝100。
圖10A至圖10E說明根據本發明一些實施例的凹槽72及凹槽74的俯視圖。應注意，圖10A至圖10E所示實施例當可應用時可與圖1至圖9B所示實施例中的任一者進行組合。可自圖10A至圖10E中包括線C-C的平面獲得圖1至圖9B所示剖視圖。儘管圖中未示出，但除了凹槽72’及凹槽74’將被限制於裝置晶粒(封裝組件44)的區及包封材料48的區中以外，凹槽72’及凹槽74’的俯視形狀可分別類似於凹槽72及74的俯視形狀。
參考圖10A，凹槽72自環形部分70B延伸至裝置晶粒(封裝組件44)上方。凹槽74亦延伸至環形部分70B的相對的側部部分。圖10B至圖10E說明根據替代實施例的封裝100的俯視圖。該些實施例類似於圖10A所示實施例。
已進行各種實驗來確定熱界面材料所遭受的應力。在一些實驗中，發現了高應力隅角區具有利用虛線75所示的形狀。根據本發明的一些實施例，凹槽72的內邊緣的形狀被選擇成模仿虛線75的形狀，以將應力減小效果最大化，且將凹槽72的大小最小化。藉由將凹槽72/凹槽74/凹槽72’/凹槽74’的大小最小化，熱界面材料78的熱阻的不良增大可得以最小化。根據一些實施例，由於高應力區具有彎曲的(有時接近四分之一個圓)內邊緣(具有虛線75的形狀)，因此凹槽72被設計成具有圖10A所示彎曲的內邊緣。
在圖10B所示實施例中，凹槽72與環形部分70B間隔開。圖10C說明凹槽72具有在裝置晶粒(封裝組件44)及包封材料48上方交叉的筆直的內邊緣，且凹槽72延伸至環形部分70B的側部部分。在圖10D所示實施例中，凹槽72具有在裝置晶粒(封裝組件44)及包封材料48上方交叉的筆直的內邊緣，且凹槽72與環形部分70B的側部部分間隔開。圖10E說明封裝100，其中形成附加凹槽73，附加凹槽73自金屬蓋體70的頂部部分70A的底表面延伸至頂部部分70A中。凹槽73與封裝58的邊緣部分交疊，其中凹槽73可連接至凹槽72或可不連接至凹槽72。因此， 凹槽73與凹槽74組合起來形成與封裝58的整個周邊區交疊的完整的環形。類似地，熱界面材料78(圖7A、圖7B、圖9A、及圖9B)的一些部分可延伸至凹槽73中。由於裝置晶粒(封裝組件44)的邊緣及包封材料48的邊緣處的應力亦為高的(儘管小於隅角區中的應力)，因此形成凹槽73亦幫助減輕該些區中的應力。
本發明的實施例具有一些有利特徵。藉由形成凹槽以使得熱界面材料的厚度在高應力區中增大，熱界面材料能夠在熱循環中吸收更高的應力，且因此減少熱界面材料與裝置晶粒及金屬蓋體的分層及裂縫。熱界面材料的厚度增大的區域受到限制，且熱界面材料的大部分不具有增大的厚度。因此，熱界面材料傳導熱量的能力不會受到顯著影響。
根據本發明的一些實施例，一種封裝包括：封裝組件；裝置晶粒，位於所述封裝組件上方且結合至所述封裝組件；金屬蓋體，具有位於所述裝置晶粒上方的頂部部分；以及熱界面材料，位於所述裝置晶粒與所述金屬蓋體之間且接觸所述裝置晶粒及所述金屬蓋體。所述熱界面材料包括位於所述裝置晶粒的內側部分正上方的第一部分及在所述裝置晶粒的隅角區正上方延伸的第二部分。第一部分具有第一厚度。第二部分具有較所述第一厚度大的第二厚度。
在本發明實施例中，所述金屬蓋體包括自所述金屬蓋體的所述頂部部分的底表面延伸至所述金屬蓋體的所述頂部部分中的凹槽，其中所述熱界面材料的所述第二部分的上部處於所述凹 槽中。
在本發明實施例中，所述金屬蓋體更包括位於所述頂部部分之下且連接在所述頂部部分的環形部分，其中所述凹槽在橫向上延伸至所述環形部分。
在本發明實施例中，所述金屬蓋體更包括位於所述頂部部分之下且連接在所述頂部部分的環形部分，其中所述凹槽在橫向上與所述環形部分間隔開。
在本發明實施例中，所述裝置晶粒包括基板，且所述基板的隅角區域被凹陷成凹槽，且其中所述熱界面材料的所述第二部分的下部處於所述凹槽中。
在本發明實施例中，封裝更包括環繞所述裝置晶粒的包封材料，其中所述熱界面材料的具有所述第二厚度的所述第二部分在所述包封材料的隅角部分的正上方延伸。
在本發明實施例中，封裝更包括結合至所述第一封裝組件的附加裝置晶粒，其中所述熱界面材料更包括與所述裝置晶粒和所述附加裝置晶粒之間的間隙交疊的第三部分，且其中所述熱界面材料的所述第三部分具有較所述第二厚度大的第三厚度。
在本發明實施例中，所述熱界面材料的具有所述第二厚度的所述第二部分具有連續彎曲的內邊緣。
在本發明實施例中，所述熱界面材料的所述第二部分的所述連續彎曲的內邊緣具有為四分之一個圓的形狀。
在本發明實施例中，所述第二部分具有連續變化的厚 度，所述熱界面材料的與所述金屬蓋體的所述頂部部分的中心靠近的部分薄於遠離所述中心的部分。
根據本發明的一些實施例，一種封裝包括堆疊及金屬蓋體。所述堆疊包括：中介層；第一裝置晶粒及第二裝置晶粒，位於所述中介層上方且結合至所述中介層；封裝基板，位於所述中介層之下且結合至所述中介層；以及包封材料，環繞所述第一裝置晶粒與所述第二裝置晶粒中的每一者。所述金屬蓋體包括頂部部分及位於所述頂部部分之下且連接至所述頂部部分的邊緣部分。黏合劑將所述邊緣部分黏合至所述封裝基板。熱界面材料具有平面部分及突起部分，所述平面部分具有實質上均勻的厚度，所述突起部分自所述平面部分向上或向下突起。所述突起部分與所述堆疊的隅角部分交疊。
在本發明實施例中，所述熱界面材料包括四個突起部分。所述四個突起部分中的每一者均與所述堆疊的隅角交疊，其中所述四個突起部分彼此分離。
在本發明實施例中，其中所述突起部分向上突起以延伸至所述金屬蓋體的所述頂部部分的凹槽中。
在本發明實施例中，所述突起部分向下突起以延伸至所述堆疊的凹槽中。
在本發明實施例中，所述突起部分與所述堆疊的周邊部分交疊，且所述周邊部分形成完整的環形。
在本發明實施例中，封裝更包括向上或向下突起的附加 突起部分，其中所述附加突起部分與所述第一裝置晶粒和所述第二裝置晶粒之間的間隙交疊。
根據本發明的一些實施例，一種封裝包括：封裝基板；中介層，位於所述封裝基板上方且結合至所述封裝基板；以及裝置晶粒，位於所述中介層上方且結合至所述中介層。金屬蓋體具有位於所述裝置晶粒上方的頂部部分。所述頂部部分具有多個凹槽，所述多個凹槽中的每一者自所述頂部部分的底表面凹陷至所述頂部部分中。所述金屬蓋體更包含邊緣部分，所述邊緣部分環繞所述裝置晶粒及所述中介層。所述邊緣部分黏合至所述封裝基板，且所述邊緣部分具有四個側部部分。熱界面材料位於所述裝置晶粒與所述金屬蓋體之間且接觸所述裝置晶粒及所述金屬蓋體。所述熱界面材料延伸至所述金屬蓋體的所述頂部部分的所述多個凹槽中。
在本發明實施例中，除所述多個凹槽外的所述金屬蓋體的所述頂部部分的實質上整個底表面是平面的。
在本發明實施例中，所述多個凹槽具有大於約10微米的深度。
在本發明實施例中，所述多個凹槽中的每一者具有與所述金屬蓋體的所述頂部部分的中心面對的內邊緣，且所述內邊緣是彎曲的。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本發明的各個態樣。熟習此項技術者應理解，其可容 易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，此類等效構造並不背離本發明的精神及範圍，且熟習此項技術者可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替、及變更。

Claims (14)

  1. 一種封裝，包括：第一封裝組件；裝置晶粒，位於所述第一封裝組件上方且結合至所述第一封裝組件；金屬蓋體，包括位於所述裝置晶粒上方的頂部部分；以及熱界面材料，位於所述裝置晶粒與所述金屬蓋體之間且接觸所述裝置晶粒及所述金屬蓋體，其中所述熱界面材料包括：第一部分，位於所述裝置晶粒的內側部分正上方，其中所述第一部分具有第一厚度；以及第二部分，在所述裝置晶粒的隅角區正上方延伸，其中所述第二部分具有較所述第一厚度大的第二厚度。
  2. 如申請專利範圍第1項所述的封裝，其中所述金屬蓋體包括自所述金屬蓋體的所述頂部部分的底表面延伸至所述金屬蓋體的所述頂部部分中的凹槽，其中所述熱界面材料的所述第二部分的上部處於所述凹槽中。
  3. 如申請專利範圍第2項所述的封裝，其中所述金屬蓋體更包括位於所述頂部部分之下且連接在所述頂部部分的環形部分，其中所述凹槽在橫向上延伸至所述環形部分，或所述凹槽在橫向上與所述環形部分間隔開。
  4. 如申請專利範圍第1項所述的封裝，其中所述裝置晶粒包括基板，且所述基板的隅角區域被凹陷成凹槽，且其中所述熱界面材料的所述第二部分的下部處於所述凹槽中。
  5. 如申請專利範圍第1項所述的封裝，更包括環繞所述裝置晶粒的包封材料，其中所述熱界面材料的具有所述第二厚度的所述第二部分在所述包封材料的隅角部分的正上方延伸。
  6. 如申請專利範圍第1項所述的封裝，更包括結合至所述第一封裝組件的附加裝置晶粒，其中所述熱界面材料更包括與所述裝置晶粒和所述附加裝置晶粒之間的間隙交疊的第三部分，且其中所述熱界面材料的所述第三部分具有較所述第二厚度大的第三厚度。
  7. 如申請專利範圍第1項所述的封裝，其中所述熱界面材料的具有所述第二厚度的所述第二部分具有連續彎曲的內邊緣。
  8. 如申請專利範圍第1項所述的封裝，其中所述第二部分具有連續變化的厚度，所述熱界面材料的與所述金屬蓋體的所述頂部部分的中心靠近的部分薄於遠離所述中心的部分。
  9. 一種封裝，包括：堆疊，包括：中介層；第一裝置晶粒及第二裝置晶粒，位於所述中介層上方且結合至所述中介層；封裝基板，位於所述中介層之下且結合至所述中介層；以及包封材料，環繞所述第一裝置晶粒與所述第二裝置晶粒中的每一者；金屬蓋體，包括：頂部部分；以及邊緣部分，位於所述頂部部分之下且連接至所述頂部部分；黏合劑，將所述邊緣部分黏合至所述封裝基板；以及熱界面材料，包括：平面部分，具有實質上均勻的厚度；以及突起部分，自所述平面部分向上或向下突起，其中所述突起部分與所述堆疊的隅角部分交疊。
  10. 如申請專利範圍第9項所述的封裝，其中所述突起部分向上突起以延伸至所述金屬蓋體的所述頂部部分的凹槽中；或所述突起部分向下突起以延伸至所述堆疊的凹槽中；或所述突起部分與所述堆疊的周邊部分交疊，且所述周邊部分形成完整的環形。
  11. 如申請專利範圍第9項所述的封裝，更包括向上或向下突起的附加突起部分，其中所述附加突起部分與所述第一裝置晶粒和所述第二裝置晶粒之間的間隙交疊。
  12. 一種封裝，包括：封裝基板；中介層，位於所述封裝基板上方且結合至所述封裝基板；裝置晶粒，位於所述中介層上方且結合至所述中介層；金屬蓋體，包括：頂部部分，位於所述裝置晶粒上方，其中所述頂部部分包括多個凹槽，所述多個凹槽中的每一者自所述頂部部分的底表面凹陷至所述頂部部分中，且所述裝置晶粒位於所述多個凹槽之外；以及邊緣部分，環繞所述裝置晶粒及所述中介層，其中所述邊緣部分黏合至所述封裝基板，且所述邊緣部分包括多個側部部分；以及熱界面材料，位於所述裝置晶粒與所述金屬蓋體之間且接觸所述裝置晶粒及所述金屬蓋體，其中所述熱界面材料從所述多個凹槽之外延伸至所述金屬蓋體的所述頂部部分的所述多個凹槽中。
  13. 如申請專利範圍第12項所述的封裝，其中除所述多個凹槽外的所述金屬蓋體的所述頂部部分的實質上整個底表面是平面的。
  14. 如申請專利範圍第12項所述的封裝，其中所述多個凹槽中的每一者具有與所述金屬蓋體的所述頂部部分的中心面對的內邊緣，且所述內邊緣是彎曲的。
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Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9899238B2 (en) * 2014-12-18 2018-02-20 Intel Corporation Low cost package warpage solution
JP6748501B2 (ja) * 2016-07-14 2020-09-02 ローム株式会社 電子部品およびその製造方法
DE102018106434B4 (de) 2017-06-30 2023-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleiter-Bauelement und Verfahren zu dessen Herstellung
US11121050B2 (en) * 2017-06-30 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of a semiconductor device
US11004803B2 (en) * 2018-07-02 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy dies for reducing warpage in packages
KR102566974B1 (ko) 2018-07-11 2023-08-16 삼성전자주식회사 반도체 패키지
US10804172B2 (en) * 2018-12-10 2020-10-13 Advanced Semiconductor Engineering, Inc. Semiconductor package device with thermal conducting material for heat dissipation
KR102654893B1 (ko) * 2019-01-17 2024-04-08 삼성전자주식회사 반도체 패키지 시스템
US11552019B2 (en) * 2019-03-12 2023-01-10 Intel Corporation Substrate patch reconstitution options
KR102661833B1 (ko) 2019-04-17 2024-05-02 삼성전자주식회사 반도체 패키지
US11164824B2 (en) * 2019-08-28 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
US11282759B2 (en) * 2019-09-09 2022-03-22 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure having warpage control and method of forming the same
US11145614B2 (en) * 2019-10-18 2021-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
TWI717155B (zh) * 2019-12-17 2021-01-21 財團法人工業技術研究院 晶片封裝結構
US11450580B2 (en) * 2019-12-24 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of fabricating the same
US11682626B2 (en) 2020-01-29 2023-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. Chamfered die of semiconductor package and method for forming the same
US11488887B1 (en) * 2020-03-05 2022-11-01 Xilinx, Inc. Thermal enablement of dies with impurity gettering
US11282825B2 (en) * 2020-05-19 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure
KR20210147453A (ko) * 2020-05-29 2021-12-07 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR20210148743A (ko) 2020-06-01 2021-12-08 삼성전자주식회사 반도체 패키지
TW202147539A (zh) * 2020-06-03 2021-12-16 南韓商三星電子股份有限公司 半導體封裝
KR20210150153A (ko) 2020-06-03 2021-12-10 삼성전자주식회사 패키지 신뢰성을 향상시킬 수 있는 반도체 패키지
US11552054B2 (en) * 2020-06-29 2023-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US11239136B1 (en) * 2020-07-28 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Adhesive and thermal interface material on a plurality of dies covered by a lid
US11830821B2 (en) * 2020-10-19 2023-11-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacture
US12002780B2 (en) * 2020-11-12 2024-06-04 Taiwan Semiconductor Manufacturing Company Ltd. Package structure including a base and a lid disposed over the base and method of forming the package structure
DE102020131849A1 (de) 2020-12-01 2022-06-02 Infineon Technologies Ag Chip-package, halbleiteranordnung, verfahren zum bilden eines chip-packages, und verfahren zum bilden einer halbleiteranordnung
US11682602B2 (en) 2021-02-04 2023-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacture
US11842935B2 (en) * 2021-02-18 2023-12-12 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a reconstructed package substrate comprising substrates blocks
US20220301970A1 (en) * 2021-03-19 2022-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of manufacturing semiconductor package
JP2022146048A (ja) * 2021-03-22 2022-10-05 キオクシア株式会社 半導体記憶装置および放熱用部品
US20220319954A1 (en) * 2021-03-31 2022-10-06 Texas Instruments Incorporated Package heat dissipation
US20220352099A1 (en) * 2021-05-03 2022-11-03 Nvidia Corporation Integrated circuit physical security device
US20220359465A1 (en) * 2021-05-07 2022-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and method for forming the same
US11742218B2 (en) 2021-05-07 2023-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device package having metal thermal interface material and method for forming the same
US11984381B2 (en) 2021-05-13 2024-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package structure and method for forming the same
US11705381B2 (en) * 2021-06-04 2023-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. High efficiency heat dissipation using thermal interface material film
KR20220164946A (ko) * 2021-06-07 2022-12-14 삼성전자주식회사 반도체 패키지
US11942448B2 (en) * 2021-07-16 2024-03-26 Texas Instruments Incorporated Integrated circuit die pad cavity
US11978722B2 (en) * 2021-08-27 2024-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method of package containing chip structure with inclined sidewalls
US12094792B2 (en) 2021-08-30 2024-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure having lid with protrusion and manufacturing method thereof
US20230290704A1 (en) * 2022-03-14 2023-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and manufacturing method thereof
US20240071847A1 (en) * 2022-08-26 2024-02-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100044856A1 (en) * 2008-08-19 2010-02-25 International Business Machines Corporation Electronic package with a thermal interposer and method of manufacturing the same
US20110044007A1 (en) * 2009-08-20 2011-02-24 Nec Electronics Corporation Heat sink, semiconductor device, and method of manufacturing heat sink
US20150035135A1 (en) * 2013-08-02 2015-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Packages with Heat Sinks Attached to Heat Dissipating Rings
US20150108628A1 (en) * 2013-08-02 2015-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Thermal Interface Material on the Sidewalls of Stacked Dies

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002314031A (ja) 2001-04-13 2002-10-25 Fujitsu Ltd マルチチップモジュール
JP4079604B2 (ja) 2001-05-30 2008-04-23 株式会社ルネサステクノロジ 半導体装置の製造方法
US6504723B1 (en) 2001-11-15 2003-01-07 Intel Corporation Electronic assembly having solder thermal interface between a die substrate and a heat spreader
US6790709B2 (en) 2001-11-30 2004-09-14 Intel Corporation Backside metallization on microelectronic dice having beveled sides for effective thermal contact with heat dissipation devices
US6812548B2 (en) 2001-11-30 2004-11-02 Intel Corporation Backside metallization on sides of microelectronic dice for effective thermal contact with heat dissipation devices
TWI228809B (en) * 2003-08-07 2005-03-01 Advanced Semiconductor Eng Flip chip package structure and substrate structure thereof
US7575955B2 (en) 2004-01-06 2009-08-18 Ismat Corporation Method for making electronic packages
JP4624775B2 (ja) * 2004-12-27 2011-02-02 富士通セミコンダクター株式会社 半導体装置
JP2007035688A (ja) 2005-07-22 2007-02-08 Fujitsu Ltd 半導体装置およびその製造方法
US8174114B2 (en) 2005-12-15 2012-05-08 Taiwan Semiconductor Manufacturing Go. Ltd. Semiconductor package structure with constraint stiffener for cleaning and underfilling efficiency
JP2007266150A (ja) 2006-03-28 2007-10-11 Fujitsu Ltd 熱伝導性接合材、半導体パッケージ、ヒートスプレッダ、半導体チップ、及び半導体チップとヒートスプレッダとを接合する接合方法
US7439617B2 (en) 2006-06-30 2008-10-21 Intel Corporation Capillary underflow integral heat spreader
US7977802B2 (en) 2009-03-05 2011-07-12 Stats Chippac Ltd. Integrated circuit packaging system with stacked die and method of manufacture thereof
US7961469B2 (en) 2009-03-31 2011-06-14 Apple Inc. Method and apparatus for distributing a thermal interface material
US9431316B2 (en) * 2010-05-04 2016-08-30 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming channels in back surface of FO-WLCSP for heat dissipation
US8574965B2 (en) 2010-10-22 2013-11-05 Ati Technologies Ulc Semiconductor chip device with liquid thermal interface material
KR20120053332A (ko) 2010-11-17 2012-05-25 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US9281228B2 (en) * 2011-11-01 2016-03-08 Stats Chippac, Ltd. Semiconductor device and method of forming thermal interface material and heat spreader over semiconductor die
US20140091461A1 (en) 2012-09-30 2014-04-03 Yuci Shen Die cap for use with flip chip package
US9040349B2 (en) 2012-11-15 2015-05-26 Amkor Technology, Inc. Method and system for a semiconductor device package with a die to interposer wafer first bond
KR101401708B1 (ko) 2012-11-15 2014-05-30 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9799592B2 (en) * 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
US9245813B2 (en) 2013-01-30 2016-01-26 International Business Machines Corporation Horizontally aligned graphite nanofibers in etched silicon wafer troughs for enhanced thermal performance
US8901732B2 (en) 2013-03-12 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device package and method
US8987876B2 (en) * 2013-03-14 2015-03-24 General Electric Company Power overlay structure and method of making same
US10163754B2 (en) * 2013-12-26 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Lid design for heat dissipation enhancement of die package
US9425114B2 (en) 2014-03-28 2016-08-23 Oracle International Corporation Flip chip packages
US9831148B2 (en) * 2016-03-11 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
US10002857B2 (en) 2016-04-12 2018-06-19 Qualcomm Incorporated Package on package (PoP) device comprising thermal interface material (TIM) in cavity of an encapsulation layer
US9812374B1 (en) 2017-03-22 2017-11-07 Xilinix, Inc. Thermal management device with textured surface for extended cooling limit
US10529645B2 (en) * 2017-06-08 2020-01-07 Xilinx, Inc. Methods and apparatus for thermal interface material (TIM) bond line thickness (BLT) reduction and TIM adhesion enhancement for efficient thermal management
US10510650B2 (en) * 2018-02-02 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100044856A1 (en) * 2008-08-19 2010-02-25 International Business Machines Corporation Electronic package with a thermal interposer and method of manufacturing the same
US20110044007A1 (en) * 2009-08-20 2011-02-24 Nec Electronics Corporation Heat sink, semiconductor device, and method of manufacturing heat sink
US20150035135A1 (en) * 2013-08-02 2015-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Packages with Heat Sinks Attached to Heat Dissipating Rings
US20150108628A1 (en) * 2013-08-02 2015-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Thermal Interface Material on the Sidewalls of Stacked Dies

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