CN108987358B - 封装件中具有不同厚度的热界面材料 - Google Patents
封装件中具有不同厚度的热界面材料 Download PDFInfo
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- CN108987358B CN108987358B CN201711202687.7A CN201711202687A CN108987358B CN 108987358 B CN108987358 B CN 108987358B CN 201711202687 A CN201711202687 A CN 201711202687A CN 108987358 B CN108987358 B CN 108987358B
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- device die
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- metal cap
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- 239000000463 material Substances 0.000 title claims abstract description 69
- 229910052751 metal Inorganic materials 0.000 claims abstract description 87
- 239000002184 metal Substances 0.000 claims abstract description 87
- 239000000758 substrate Substances 0.000 claims description 50
- 239000008393 encapsulating agent Substances 0.000 claims description 18
- 238000005538 encapsulation Methods 0.000 claims description 11
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 description 17
- 239000000945 filler Substances 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 7
- 239000002131 composite material Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000004593 Epoxy Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000005336 cracking Methods 0.000 description 4
- 238000001723 curing Methods 0.000 description 4
- 230000032798 delamination Effects 0.000 description 4
- 238000000227 grinding Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 101710149792 Triosephosphate isomerase, chloroplastic Proteins 0.000 description 3
- 101710195516 Triosephosphate isomerase, glycosomal Proteins 0.000 description 3
- 239000002313 adhesive film Substances 0.000 description 3
- 230000000712 assembly Effects 0.000 description 3
- 238000000429 assembly Methods 0.000 description 3
- 229910001092 metal group alloy Inorganic materials 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 238000003801 milling Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 239000012798 spherical particle Substances 0.000 description 2
- 238000001029 thermal curing Methods 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001152 differential interference contrast microscopy Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000395 magnesium oxide Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000003278 mimic effect Effects 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000003351 stiffener Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000005382 thermal cycling Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H01L23/367—Cooling facilitated by shape of device
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3733—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3737—Organic materials with or without a thermoconductive filler
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- H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
- H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
- H01L23/4012—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws for stacked arrangements of a plurality of semiconductor devices
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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Abstract
一种封装件包括封装组件,位于封装组件上方并且接合至封装组件的器件管芯,具有位于器件管芯上方的顶部的金属帽,以及位于器件管芯和金属帽之间并且接触器件管芯和金属帽的热界面材料。热界面材料包括直接位于器件管芯的内部上方的第一部分,以及直接在器件管芯的拐角区域上方延伸的第二部分。第一部分具有第一厚度。第二部分具有大于第一厚度的第二厚度。
Description
技术领域
本发明的实施例一般地涉及半导体技术领域,更具体地,涉及封装件。
背景技术
在一些三维集成电路(3DIC)中,首先将器件管芯接合至中介层,其中,该中介层进一步接合至封装衬底以形成封装件。在器件管芯运行期间在其中产生的热量需要扩散。在传统的结构中,为了扩散热量,将器件管芯的衬底附接至金属盖上,这有助于散热,并且还用作加强件。因此,将在器件管芯中产生的热量扩散至金属盖。可以将散热器附接至金属盖,以进一步扩散传导至金属盖的热量。
通过热界面材料(TIM)将器件管芯附接至金属盖,其中,该热界面材料可以包括环氧树脂基材料。由于TIM具有相对低的导热率,因此优选地,TIM是薄的,从而使得TIM不会在器件管芯和金属盖之间引入太多的热阻。
发明内容
根据本发明的一方面,提供了一种封装件,包括:第一封装组件;器件管芯,位于所述第一封装组件上方并且接合至所述第一封装组件;金属帽,包括位于所述器件管芯上方的顶部;以及热界面材料,位于所述器件管芯和所述金属帽之间并与所述器件管芯和所述金属帽接触,其中,所述热界面材料包括:第一部分,直接位于所述器件管芯的内部上方,其中,所述第一部分具有第一厚度;以及第二部分,直接在所述器件管芯的拐角区上方延伸,其中,所述第二部分具有大于所述第一厚度的第二厚度。
根据本发明的另一方面,提供了一种封装件,包括:堆叠件,包括:中介层;第一器件管芯和第二器件管芯,位于所述中介层上方并且接合至所述中介层;封装衬底,位于所述中介层下方并且接合至所述中介层;以及密封材料,环绕所述第一器件管芯和所述第二器件管芯中的每个;金属帽,包括:顶部;以及边缘部分,位于所述顶部下方并且连接至所述顶部;粘合剂,将所述边缘部分粘附至所述封装衬底;以及热界面材料,包括:平坦部分,具有均匀的厚度;以及突出部分,从所述平坦部分向上或向下突出,其中,所述突出部分与所述堆叠件的拐角部分重叠。
根据本发明的又一方面,提供了一种封装件,包括:封装衬底;中介层,位于所述封装衬底上方并且接合至所述封装衬底;器件管芯,位于所述中介层上方并且接合至所述中介层;金属帽,包括:顶部,位于所述器件管芯上方,其中,所述顶部包括多个凹槽,每个凹槽从所述顶部的底面凹进到所述顶部中;以及边缘部分,将所述器件管芯和所述中介层环绕在其中,其中,所述边缘部分粘附至所述封装衬底,并且所述边缘部分包括四个侧部;以及热界面材料,位于所述器件管芯和所述金属帽之间并且接触所述器件管芯和所述金属帽,其中,所述热界面材料延伸到所述金属帽的顶部的四个凹槽中。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1至图7A和图7B示出根据一些实施例的形成封装件的中间阶段的截面图。
图8A、图8B、图9A和图9B示出根据一些实施例的形成封装件的中间阶段的截面图和顶视图。
图10A至图10E示出根据一些实施例的一些封装件的顶视图。
图11示出根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为了便于描述,在此可以使用诸如“在…下方”、“在…之下”、“下部”、“在…上方”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且在此使用的空间相对描述符可以同样地作出相应的解释。
本发明根据各个示例性实施例提供了封装件及其形成方法,该封装件包括金属帽、器件管芯。示出形成该封装件的中间阶段。讨论了一些示例性实施例的变化。贯穿各个图和示例性实施例,相同的参考标号用于指定相同的元件。
图1至图7A示出根据本发明的一些实施例的形成封装件的中间阶段的截面图。此外,在图11所示的工艺流程中示意性地反映了图1至图7A中所示的步骤。
图1示出封装组件20的截面图,其中,该封装组件可以是中介层晶圆、封装衬底条、器件管芯晶圆或封装件。封装组件20包括可以彼此相同的多个封装组件40。封装组件40可以是器件芯片(当锯开时也称为管芯,其可以包括或不包括有源器件和/或无源器件)、封装衬底、封装件等。在整个说明书中,在下文中封装组件40可以可选地称为中介层40,而它们可以是如上所述的其他类型的封装组件。
根据本发明的一些实施例,封装组件20包括衬底22,其中,衬底22可以是诸如硅衬底的半导体衬底。衬底22还可以由诸如硅锗、硅碳等的另一半导体材料形成。根据一些实施例,在半导体衬底22的表面22A处形成诸如晶体管(未示出)的有源器件。还可以在封装组件20中形成诸如电阻器和/或电容器的无源器件(未示出)。根据本发明的可选实施例,衬底22可以是半导体衬底或介电衬底,并且相应的封装组件不包括其中的有源器件。根据这些实施例,封装组件20可以包括或不包括形成在其中的无源器件。
贯通孔(TV)24(可选地称为金属柱)可以形成为从衬底22的顶面22A延伸到衬底22中。TV 24有时也称为衬底贯通孔,或当衬底22是硅衬底时,称为硅贯通孔。互连结构28形成在衬底22上方,并且用于电连接至集成电路器件(如存在)和TV 24。互连结构28可以包括多个介电层30。在介电层30中形成金属线32。通孔34形成在上面的金属线32和下面的金属线32之间,并且互连上面的金属线32和下面的金属线32。根据本发明的一些实施例,介电层30由氧化硅、氮化硅、碳化硅、氮氧化硅、它们的组合和/或它们的多层形成。可选地,介电层30可以包括具有低介电常数(k值)的一个或多个低k介电层。例如,介电层30中的低k介电材料的k值可以小于约3.0,或小于约2.5。
在封装组件20的顶面处形成电连接件38。根据本发明的一些实施例,电连接件38包括金属柱,其中,可以在金属柱的顶面上形成或不形成焊料帽(solder cap)。根据本发明的可选实施例,电连接件38包括焊料区。根据其他实施例,电连接件38可以是铜柱凸块、焊料凸块或复合凸块,其中,该复合凸块包括铜柱、镍层、焊料帽、化学镀镍浸金(ENIG)、化学镀镍化学镀钯浸金(ENEPIG)等和/或它们的组合。
封装组件44可以例如通过倒装芯片接合而接合至封装组件20。相应步骤在图11所示的工艺流程200中示出为步骤202。电连接件38因此将封装组件44中的电路电连接至封装组件20中的金属线32和TV 24。封装组件44可以是包括逻辑电路、存储器电路等的器件管芯。因此,封装组件44在下文中可选地称为器件管芯44。可选地,封装组件44可以是包括接合至相应的中介层、封装衬底等的管芯的封装件。当电连接件38包括焊料区时,实施回流以将器件管芯44接合至中介层40。
在每个中介层40上,可以存在接合至中介层上的一个、两个、三个或多个器件管芯44。例如,如图1所示,将两个器件管芯44接合至相同的中介层40。根据本发明的一些实施例,器件管芯44包括半导体衬底,其中,根据本发明的一些实施例,该半导体衬底可以是硅衬底。因此,器件管芯44的顶面44A可以是诸如硅的半导体材料的表面。
接下来,可以通过底部填充物46来填充器件管芯44和封装组件20之间的间隙。底部填充物46可以包括用于保护电连接件38免受应力的聚合物或环氧树脂。底部填充物46还可以是模制底部填充物,当在图2所示的步骤中密封(encapsulate,又称封装)器件管芯44时,分配底部填充物,其中,相同的模制底部填充物可以用作图2中的底部填充物46和密封材料48。
参考图2,例如,使用压缩模制、传递模制等将密封材料48密封在器件管芯44和封装组件20上。相应步骤在图11所示的工艺流程200中示出为步骤204。根据本发明的一些实施例,密封材料48包括模塑料,其中,该模塑料包括基材和混合在基材中的填料(filler,又称填充物)。基材可以包括聚合物、树脂、环氧树脂等。填料可以由二氧化硅、氧化铝等的球形颗粒形成。实施固化步骤以固化和凝固密封材料48,其中,固化可以是热固化、紫外线(UV)固化等。根据一些实施例,可以将器件管芯44埋入密封材料48中。
在固化密封材料48之后,实施诸如化学机械抛光(CMP)或机械研磨的平坦化步骤,以去除密封材料48的多余部分,其中,该多余的部分位于器件管芯44的顶面44A上方。相应步骤在图11所示的工艺流程200中示出为步骤206。在图3中示出了所得到的结构。因此,暴露器件管芯44的衬底的顶面44A,并且该顶面44A与模制材料48的顶面48A共面。
图4示出形成封装组件20的背侧结构。相应步骤在图11所示的工艺流程200中示出为步骤208。在背侧结构的形成过程中,对衬底22的背侧实施背侧研磨以减薄衬底22,直到暴露TV 24。在半导体衬底22的背侧上形成介电层(或多个介电层)50。可以在介电层50中形成RDL 52。电连接件54还可以形成在封装组件20的背侧上并电连接至TV 24。根据本发明的一些实施例,电连接件54是焊料区。根据其他实施例,电连接件54可以包括金属焊盘、金属凸块、焊料帽等。在整个说明书中,图4所示的封装件称为复合晶圆61。
接下来,沿着划线25/27对复合晶圆61实施切割(分割),以将图4所示的封装件切割成多个封装件58,其中,每个封装件58都包括堆叠的封装组件。相应步骤还在图11所示的工艺流程200中示出为步骤208。所得到的封装件58中的每个包括一个中介层40和接合至该中介层上的相应的器件管芯44。图10A示出了示例性封装件58的顶视图。在顶视图中,密封材料48包括环绕器件管芯44的部分和位于相邻的器件管芯44之间的部分。
图5示出了例如通过电连接件54将封装件58接合至封装组件60。相应步骤在图11所示的工艺流程200中示出为步骤210。封装组件60可以是封装衬底、印刷电路板(PCB)等。封装组件60可以包括形成在封装组件60的相对侧上的电连接件(诸如金属焊盘64和焊料区66)。通过形成在封装组件60内的金属线和通孔(未示出)电互连封装组件60的相对侧上的电连接件。底部填充物62可以被分配到封装件58和封装组件60之间的间隙中并被固化。根据一些实施例,底部填充物62还具有位于间隙外的一些外部部分,其中,这些部分接触封装件58的外侧壁。底部填充物62的外部部分可以或可以不接触密封材料48。
图6和图7A以及图7B示出将金属帽70粘附至封装组件60的顶面。参考图6,金属帽70由金属或金属合金形成,其中,该金属帽具有例如高于约100W/m×K的高导热率。金属帽70的材料包括金属或金属合金。例如,金属帽70可以由选自Al、Cu、Ni、Co,不锈钢及它们的合金的金属或金属合金形成。根据本发明的一些实施例,整个金属帽70是由相同的同质金属材料形成的集成件。因此,没有可区分的界面来分离金属帽70的不同部分。
金属帽70包括顶部70A和从顶部70A的底面向下延伸的环状部分(边缘部分(skirtportion))70B。应当理解,顶部70A和环状部分70B之间没有任何可区分的界面。当从金属帽70的顶视图中观察时,环状部分70B可以形成一个完整的环(如图10A至图10E所示),其中,由环状部分70B环绕的区域足够大以容纳封装件58。
顶部70A具有顶面70TS,其中,该顶面可以是贯穿整个顶部70A延伸的平坦顶面。根据一些实施例,顶部70A还具有底面70BS-1,其中,该底面可以是最低的表面。底面70BS-1可以平行于顶面70TS,并且底面70BS-1的顶视区大于金属帽70的顶视区的50%,并且可以大于金属帽70的顶视区的约80%。
凹槽72形成为从顶部70A的底面70BS-1延伸到顶部70A中。相应步骤在图11所示的工艺流程200中示出为步骤212。可以通过铣削、压印、切割、锯切、研磨、蚀刻等形成凹槽72。可选地,当形成金属帽70时,存在凹槽72,而不是稍后形成该凹槽。因此,使用虚线框示出图11中的步骤212,以表示可能不需要实施该步骤。通过凹槽72,也暴露顶部70A的底面70BS-2。根据本发明的一些实施例,底面70BS-2是平坦的并且平行于顶面70TS。根据可选实施例,如虚线72BS-2'示意性地示出,底面70BS-2是直的但是倾斜的,其中,凹槽72的靠近环状部分70B的部分比靠近金属帽70的中心70C的部分更深。
根据本发明的一些实施例,凹槽74进一步形成为从金属帽70的底面70BS-1延伸到金属帽70中。图10A示出从环状部分70B的一个侧部延伸至相对侧部的示例性凹槽74。如将在后续段落中讨论的,凹槽74的数量和位置与器件管芯44的数量及其位置有关。根据本发明的可选实施例,不形成凹槽74,并且除了形成凹槽72的位置之外,金属帽70的整个底面是共面的。因此,凹槽74在图10A至图10E中标记为虚线,以指示它们可以形成或可以不形成。
再次参考图6,凹槽72的深度D1可以是大致均匀的,或者可以根据它们被测量的位置而变化。根据本发明的一些实施例,凹槽72的深度D1大于约10μm或大于约20μm,并且可以在约30μm和约70μm之间的范围内,其中,如果凹槽72的深度D1不均匀,则深度D1是凹槽72的最大深度。应当理解,凹槽72的深度D1与顶部70A的厚度有关,并且顶部70A的厚度越大,凹槽72越深。在本发明的示例性实施例中,顶部70A的厚度T1在约0.5mm和约3mm之间的范围内。
将粘合膜76粘附至环状部分70B的底面。在金属帽70的底视图中,粘合膜76可以具有完整环的形状。将热界面材料(TIM)78分配在器件管芯44和密封材料48的顶部上。相应步骤在图11所示的工艺流程200中示出为步骤214。TIM 78具有良好的导热率,该导热率可以大于约2W/m×K,并且可以等于或高于约10W/m×K或50W/m×K。TIM 78可以包括作为基材的聚合物、树脂或环氧树脂,以及改善其导热率的填料。填料可以包括诸如氧化铝、氧化镁、氮化铝、氮化硼和金刚石粉末的介电填料。填料还可以是诸如银、铜、铝等的金属填料。填料可以是球形颗粒的形式。
如箭头80所示,朝向封装组件60推压金属帽70,从而使得金属帽70通过粘合膜76粘附至封装组件60。相应步骤在图11所示的工艺流程200中示出为步骤216。所得到的封装件在下文中称为封装件100。还将底面70BS-1和70BS-2推压至TIM 78,从而使得TIM 78的直接位于器件管芯44和密封材料48上方的部分具有与底面70BS-1和70BS-2接触的顶面。图7A中示出所得到的结构。然后例如,TIM 78在热固化工艺中固化和凝固。
TIM 78包括具有厚度T2的多数部分78A(较薄部分)和具有大于厚度T2的厚度T3的拐角部分78B(较厚部分)。TIM部分78B包括延伸到凹槽72中的部分和直接位于凹槽72下方的部分。因此,也可以将TIM 78设想成具有贯穿器件管芯44和密封材料48扩展的平坦的较薄部分,以及从平坦的较薄部分突出到凹槽72和74中的突出部分。使得TIM 78的多数部分78A变薄可以降低金属帽70和器件管芯44之间的热阻,并且因此,由器件管芯44产生的热量可以扩散到金属帽70中,而不会经历过多的热阻。根据一些实施例,厚度T2小于约90μm,并且可以在约50μm和约90μm之间的范围内。厚度差(T3-T2)可以大于约10μm或大于约20μm,并且可以在约30μm和约70μm之间的范围内。应当理解,如果没有形成凹槽72和74,则TIM 78的直接位于器件管芯44和密封材料48上方的整个部分将具有小的厚度T2。在封装工艺中,封装件可能经历多个热循环,导致金属帽70、TIM78和封装件58的翘曲。因此,可能会在TIM 78和下面的器件管芯44之间发生分层和破裂。由于这些区域中的应力高于其他区域中的应力,因此在封装件58的拐角处的分层和破裂也很严重。通过使得拐角处的TIM 78的部分变厚,能够提高吸收应力的能力,并且不易发生分层和破裂。
图10A示出根据各个实施例的封装件100的顶视图,其中,可以从图10A至图10E所示的包含线C-C的平面获得图7A所示的截面图。参考图10A作为实例,示出凹槽72的相对位置和尺寸(相对于环状部分70B和封装件58)。根据一些实施例,凹槽72从金属帽70的环状部分70B朝向中心70C延伸。凹槽72至少覆盖封装件58的拐角部分。根据一些实施例,凹槽72覆盖器件管芯44和密封材料48这两者的拐角部分。根据可选实施例,凹槽72覆盖密封材料48的拐角部分,但不直接在器件管芯44的拐角部分上方延伸,其中,虚线82示意性地示出相应凹槽72的内边缘。
还如图10A所示,在相邻的器件管芯44之间的间隙上方直接形成凹槽74。凹槽74可以一直延伸到环状部分70B的相对侧部(所示的顶侧部分和底侧部分)。凹槽74的宽度可以等于、小于或大于器件管芯44之间的间隙的宽度。因此,参考图7A,凹槽74可以限制在直接位于器件管芯44之间的间隙上方区域中,或者横向扩展以覆盖器件管芯44的边缘部分。由于形成凹槽74,TIM 78还具有直接位于器件管芯44之间的间隙上方的厚部,并且因此提供TIM 78的更大体积的以缓冲该区域中的应力。TIM 78的直接位于间隙上方的部分的厚度T4可以大于、等于或小于厚度T3。
在图7A中,凹槽72的内边缘是弯曲的,这可以有助于释放应力。根据可选实施例,如图7B所示,凹槽72的内边缘是直的并且是垂直的。
图8A、图8B、图9A和图9B示出根据本发明的一些实施例的形成封装件100的中间阶段的截面图。除了凹槽形成为延伸到封装件58中,而不是延伸到金属帽70的顶部70A中之外,这些实施例类似于图1至图7A/图7B所示的实施例。除非另有规定,否则这些实施例中的组件的材料和形成方法与由图1至图7A/图7B所示的实施例中的相同的参考标号表示的相同的组件基本上相同。因此,可以在图1至图7A/图7B所示的实施例的讨论中找到关于图8A、图8B、图9A和图9B所示的组件的形成工艺和材料的具体细节。
这些实施例的初始步骤基本上与图1至图4所示的步骤相同。接下来,如图8A所示,凹槽72'和74'形成为延伸到复合晶圆61中。可以通过切割(使用锯片)、铣削、研磨等形成凹槽72'和74',其中,去除管芯44和密封材料48的顶部拐角部分。因此,可以以晶圆级实施形成凹槽72'和74',并且凹槽72'延伸到相邻的封装件58中。
图8B示出复合晶圆61的顶视图,其中,该复合晶圆包括通过划线25和27彼此分离的未分割的封装件58。如图8B所示,凹槽72'可以形成为离散的凹槽,每个凹槽位于四个封装件58的接合点处。每个凹槽72'可以穿过划线25中的一条和划线27中的一条,并且可以在器件管芯44(图8B中未示出,参考图10A)上方延伸。凹槽74'可以形成为长条形凹槽,每个凹槽都穿过整列封装件58。
接下来,沿着划线25和27切割复合晶圆61,以形成封装件58,其中,在图9A中示出封装件58中的一个。然后,金属帽70通过TIM 78附接至封装件58。类似地,TIM 78包括分别具有厚度T2和T3的较薄部分78A和较厚部分78B。根据这些实施例,TIM 78可以认为是具有在整个封装件58上方扩展的平坦部分,以及从平坦部分向下突出到封装件58的凹槽72'和74'中的突出部分。如图9A所示,TIM 78的突出部分的底面可以是平坦的并且平行于金属帽70的顶部70A的顶面70TS。图9B示出其中凹槽72'的底面是倾斜的实施例,并且该底面可能是直的或弯曲。除了用于形成凹槽的工具可以具有不同的形状之外,可以使用与图8A和图8B所示的基本上相同的方法形成如图9B所示的封装件100,。
图10A至10E示出根据本发明的一些实施例的凹槽72和74的顶视图。应当注意,当应用时,图10A至图10E所示的实施例可以与图1至图9B所示的实施例中的任一个进行组合。可以从图10A至图10E中包含线C-C的平面获得图1至图9B所示的截面图。尽管未示出,但是除了将凹槽72'和74'限制在器件管芯44和密封材料48的区域中之外,凹槽72'和74'的顶视图形状可以分别类似于凹槽72和74的顶视图形状。
参考图10A,凹槽72从环状部分70B延伸至器件管芯44上方。凹槽74还延伸至环状部分70B的相对侧部。图10B至图10E示出根据可选实施例的封装件100的顶视图。这些实施例类似于图10A所示的实施例。
已经实施了实验以确定TIM所遭受的压力。在一些实验中,发现高应力拐角区域具有使用虚线75所示的形状。根据本发明的一些实施例,凹槽72的内边缘的形状选择为模拟虚线75的形状,从而使应力减小的效果最大化,并且使凹槽72的尺寸最小化。通过最小化凹槽72/74/72'/74'的尺寸,可以使TIM 78的热阻的不利增加最小化。根据一些实施例,由于高应力区具有弯曲(有时接近四分之一圆)的内边缘(具有虚线75的形状),所以可以将凹槽72设计成具有如图10A所示的弯曲的内边缘。
在图10B所示的实施例中,凹槽72与环状部分70B间隔开。图10C示出凹槽72具有穿越(crossing over,又称穿过)器件管芯44和密封材料48上方的直的内边缘,并且凹槽72延伸到环状部分70B的侧部。在图10D所示的实施例中,凹槽72具有穿越器件管芯44和密封材料48上方的直的内边缘,并且凹槽72与环状部分70B的侧部间隔开。图10E示出封装件100,其中,额外的凹槽73形成为从金属帽70的顶部70A的底面延伸到顶部70A中。凹槽73与封装件58的边缘部分重叠,其中凹槽73可以连接至或不连接至凹槽72。因此,凹部73和74结合在一起形成与封装件58的整个周边区域重叠的完整环。类似地,TIM 78(参见图7A、图7B、图9A和图9B)的部分可以延伸到凹槽73中。由于器件管芯44和密封材料48的边缘处的应力也很高(但是比拐角区小),所以形成凹槽73还有助于释放这些区域中的应力。
本发明的实施例具有一些有利特征。通过形成凹槽,使得TIM的厚度在高应力区中增加,TIM能够在热循环中吸收更高的应力,因此减少了TIM从器件管芯和金属帽的分层和破裂。限制具有增加的厚度的TIM的区域,并且TIM的大部分不具有增加的厚度。因此,不能显著地影响用于导热的TIM的能力。
根据本发明的一些实施例,一种封装件包括封装组件,位于封装组件上方并且接合至封装组件的器件管芯、具有位于器件管芯上方的顶部的金属帽,以及位于器件管芯和金属帽之间并且接触器件管芯和金属帽的热界面材料。热界面材料包括直接位于器件管芯的内部上方的第一部分,以及直接在器件管芯的拐角区上方延伸的第二部分。第一部分具有第一厚度。第二部分具有大于第一厚度的第二厚度。
在实施例中,所述金属帽包括从所述金属帽的顶部的底面延伸到所述金属帽的顶部中的凹槽,其中,所述热界面材料的第二部分的上部位于所述凹槽中。
在实施例中,所述金属帽还包括位于所述顶部下方并连接至所述顶部的环状部分,其中,所述凹槽横向延伸至所述环状部分。
在实施例中,所述金属帽还包括位于所述顶部下方并连接至所述顶部的环状部分,其中,所述凹槽与所述环状部分横向间隔开。
在实施例中,所述器件管芯包括衬底,并且使所述衬底的拐角区凹进作为凹槽,并且所述热界面材料的第二部分的下部位于所述凹槽中。
在实施例中,封装件还包括环绕所述器件管芯的密封材料,其中,具有所述第二厚度的所述热界面材料的第二部分还直接在所述密封材料的拐角部分上方延伸。
在实施例中,封装件还包括额外的器件管芯,所述额外的器件管芯接合至所述第一封装组件,其中,所述热界面材料还包括与所述器件管芯和所述额外的器件管芯之间的间隙重叠的第三部分,并且所述热界面材料的第三部分具有大于所述第二厚度的第三厚度。
在实施例中,所述热界面材料的具有所述第二厚度的第二部分具有连续弯曲的内边缘。
在实施例中,所述热界面材料的第二部分的连续弯曲的内边缘具有四分之一圆的形状。
在实施例中,所述第二部分具有连续变化的厚度,所述热界面材料的靠近所述金属帽的顶部的中心的部分比远离所述中心的部分更薄。
根据本发明的一些实施例,一种封装件包括堆叠件和金属帽。该堆叠件包括中介层,位于中介层上方并且接合至中介层的第一器件管芯和第二器件管芯,以及位于中介层下方并且接合至中介层的封装衬底,以及环绕第一器件管芯和第二器件管芯的每个的密封材料。金属帽包括顶部和位于顶部下方并且连接至顶部的边缘部分。粘合剂将边缘部分粘附至封装衬底。热界面材料具有厚度大致均匀的平坦部分和从平坦部分向上或向下突出的突出部分。突出部分与堆叠件的拐角部分重叠。
在实施例中,所述热界面材料包括四个所述突出部分,每个突出部分与所述堆叠件的拐角重叠,其中,四个所述突出部分彼此离散。
在实施例中,所述突出部分向上突出以延伸至所述金属帽的顶部的凹槽中。
在实施例中,所述突出部分向下突出以延伸到所述堆叠件的凹槽中。
在实施例中,所述突出部分与所述堆叠件的周边部分重叠,并且所述周边部分形成完整的环。
在实施例中,封装件还包括向上或向下突出的额外的突出部分,其中,所述额外的突出部分与位于所述第一器件管芯和所述第二器件管芯之间的间隙重叠。
根据本发明的一些实施例,一种封装件包括封装衬底、位于封装衬底上方并且接合至封装衬底的中介层,以及位于中介层上方并且接合至中介层的器件管芯。金属帽具有位于器件管芯上方的顶部。顶部具有多个凹槽,每个凹槽从顶部的底面凹进到顶部中。金属帽还包括将器件芯片和中介层环绕在其中的边缘部分。将边缘部分粘附至封装衬底,并且边缘部分具有四个侧部。热界面材料位于器件管芯和金属帽之间并与器件管芯和金属帽接触。热界面材料延伸到金属帽的顶部的四个凹槽中。
在实施例中,除了所述多个凹槽之外,所述金属帽的顶部的整个底面是平坦的。
在实施例中,所述多个凹槽具有大于10μm的深度。
在实施例中,所述多个凹槽中的每个具有面向所述金属帽的顶部的中心的内边缘,并且所述内边缘是弯曲的。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (20)
1.一种封装件,包括:
第一封装组件;
器件管芯,位于所述第一封装组件上方并且接合至所述第一封装组件;
密封材料,环绕所述器件管芯;
金属帽,包括位于所述器件管芯上方的顶部;以及
热界面材料,位于所述器件管芯和所述金属帽之间并与所述器件管芯和所述金属帽接触,其中,所述热界面材料包括:
第一部分,直接位于所述器件管芯的内部上方,其中,所述第一部分具有第一厚度;以及
第二部分,直接在所述器件管芯的拐角区上方延伸并且从所述器件管芯的内部的主顶面延伸至所述器件管芯中,其中,所述第二部分具有大于所述第一厚度的第二厚度,并且其中,所述第二部分的底面包括:
第一界面,与所述器件管芯的拐角区接触;以及
第二界面,与所述密封材料接触,其中,所述第一界面连续地连接至所述第二界面以形成连续的界面,并且所述第一界面和所述第二界面平行于所述器件管芯的主顶面。
2.根据权利要求1所述的封装件,其中,所述封装件还包括另一器件管芯,所述热界面材料还包括延伸至所述器件管芯和所述另一器件管芯之间的间隙内的第三部分。
3.根据权利要求1所述的封装件,其中,所述封装件还包括另一器件管芯,所述热界面材料还包括在所述器件管芯和所述另一器件管芯之间的间隙的位置处远离所述间隙延伸的第三部分。
4.根据权利要求1所述的封装件,其中,所述金属帽还包括位于所述顶部下方并连接至所述顶部的环状部分。
5.根据权利要求1所述的封装件,其中,所述器件管芯包括衬底,并且使所述衬底的拐角区凹进作为凹槽,并且所述热界面材料的第二部分的下部位于所述凹槽中。
6.根据权利要求1所述的封装件,其中,具有所述第二厚度的所述热界面材料的第二部分还直接在所述密封材料的拐角部分上方延伸。
7.根据权利要求1所述的封装件,还包括额外的器件管芯,所述额外的器件管芯接合至所述第一封装组件,其中,所述热界面材料还包括与所述器件管芯和所述额外的器件管芯之间的间隙重叠的第三部分,并且所述热界面材料的第三部分具有大于所述第二厚度的第三厚度。
8.根据权利要求1所述的封装件,其中,所述热界面材料的具有所述第二厚度的第二部分具有连续弯曲的内边缘。
9.根据权利要求8所述的封装件,其中,所述热界面材料的第二部分的连续弯曲的内边缘具有四分之一圆的形状。
10.根据权利要求1所述的封装件,其中,所述第二部分具有连续变化的厚度,所述热界面材料的靠近所述金属帽的顶部的中心的部分比远离所述中心的部分更薄。
11.一种封装件,包括:
堆叠件,包括:
中介层;
第一器件管芯和第二器件管芯,位于所述中介层上方并且接合至所述中介层;
封装衬底,位于所述中介层下方并且接合至所述中介层;以及
密封材料,环绕所述第一器件管芯和所述第二器件管芯中的每个;
金属帽,包括:
顶部;以及
边缘部分,位于所述顶部下方并且连接至所述顶部;
粘合剂,将所述边缘部分粘附至所述封装衬底;以及
热界面材料,包括:
平坦部分,具有均匀的厚度;以及
突出部分,从所述平坦部分向下突出,其中,所述突出部分与所述堆叠件的拐角部分重叠,并且其中,所述突出部分的第二底面低于所述平坦部分的第一底面,所述第二底面平行于所述第一底面,并且所述第二底面和所述第一底面是平坦的;
其中,所述第二底面从所述第一器件管芯和所述第二器件管芯中的一个正上方延伸至所述密封材料正上方。
12.根据权利要求11所述的封装件,其中,所述热界面材料包括四个所述突出部分,每个突出部分与所述堆叠件的拐角重叠,其中,四个所述突出部分彼此离散。
13.根据权利要求11所述的封装件,其中,所述热界面材料的所述突出部分具有连续弯曲的内边缘。
14.根据权利要求11所述的封装件,其中,所述突出部分向下突出以延伸到所述堆叠件的凹槽中。
15.根据权利要求11所述的封装件,其中,所述突出部分与所述堆叠件的周边部分重叠,并且所述周边部分形成完整的环。
16.根据权利要求11所述的封装件,还包括向上或向下突出的额外的突出部分,其中,所述额外的突出部分与位于所述第一器件管芯和所述第二器件管芯之间的间隙重叠。
17.一种封装件,包括:
封装衬底;
中介层,位于所述封装衬底上方并且接合至所述封装衬底;
器件管芯,位于所述中介层上方并且接合至所述中介层;
金属帽,包括:
顶部,位于所述器件管芯上方,其中,所述顶部包括多个凹槽,每个凹槽从所述顶部的底面凹进到所述顶部中;以及
边缘部分,将所述器件管芯和所述中介层环绕在其中,其中,所述边缘部分粘附至所述封装衬底,并且所述边缘部分包括四个侧部;以及
热界面材料,位于所述器件管芯和所述金属帽之间并且接触所述器件管芯和所述金属帽,其中,所述热界面材料延伸到所述金属帽的顶部的四个凹槽中,从而形成突出部分,
其中,所述四个凹槽靠近所述边缘部分的部分比靠近所述顶部的部分更深。
18.根据权利要求17所述的封装件,其中,除了所述多个凹槽之外,所述金属帽的顶部的整个底面是平坦的。
19.根据权利要求17所述的封装件,其中,所述多个凹槽具有大于10μm的深度。
20.根据权利要求17所述的封装件,其中,所述多个凹槽中的每个具有面向所述金属帽的顶部的中心的内边缘,并且所述内边缘是弯曲的。
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Also Published As
Publication number | Publication date |
---|---|
TW201903996A (zh) | 2019-01-16 |
US20240162166A1 (en) | 2024-05-16 |
KR20180131320A (ko) | 2018-12-10 |
KR102068224B1 (ko) | 2020-01-21 |
US20200402926A1 (en) | 2020-12-24 |
DE102017119017A1 (de) | 2018-12-06 |
US10707177B2 (en) | 2020-07-07 |
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TWI635588B (zh) | 2018-09-11 |
US10770405B2 (en) | 2020-09-08 |
US20180350754A1 (en) | 2018-12-06 |
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US20180350755A1 (en) | 2018-12-06 |
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