TWI753587B - 封裝結構及其形成方法 - Google Patents

封裝結構及其形成方法 Download PDF

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TWI753587B
TWI753587B TW109133245A TW109133245A TWI753587B TW I753587 B TWI753587 B TW I753587B TW 109133245 A TW109133245 A TW 109133245A TW 109133245 A TW109133245 A TW 109133245A TW I753587 B TWI753587 B TW I753587B
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Taiwan
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die
interface material
thermal interface
adhesive pattern
layer
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TW109133245A
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TW202205571A (zh
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陳志豪
高金福
鄭禮輝
盧思維
潘志堅
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台灣積體電路製造股份有限公司
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Publication of TW202205571A publication Critical patent/TW202205571A/zh

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Abstract

提供一種封裝結構及其形成方法。所述封裝結構包括第一晶粒、第二晶粒、中介層、底部填充層、熱界面材料及黏合劑圖案。所述第一晶粒及所述第二晶粒並排設置在所述中介層上。所述底部填充層設置在所述第一晶粒與所述第二晶粒之間。所述熱界面材料設置在所述第一晶粒、所述第二晶粒及所述底部填充層上。所述黏合劑圖案設置在所述底部填充層與所述熱界面材料之間，以將所述底部填充層與所述熱界面材料分隔開。

Description

封裝結構及其形成方法
本發明實施例有關於一種封裝結構及其形成方法。
在積體電路的封裝中，半導體晶粒可通過接合來堆疊，且可接合到例如中介層及封裝基底等的其他封裝組件。所得封裝體被稱為三維積體電路(Three-Dimensional Integrated Circuit，3DIC)。熱量耗散是3DIC中的一項挑戰。
在典型的3DIC中，散熱器黏附到半導體晶粒，以耗散從半導體晶粒產生的熱量。然而，例如底部填充劑、模塑化合物等包封材料存在有與散熱器的黏附性不良，從而導致散熱器與包封材料之間的脫層問題。因此，3DIC技術面臨許多待解決的挑戰。
本發明實施例提供一種封裝結構包括第一晶粒、第二晶粒群組、中介層、底部填充層、熱界面材料(TIM)及黏合劑圖案。所述第一晶粒及所述第二晶粒群組並排設置在所述中介層上。所 述底部填充層設置在所述第一晶粒與所述第二晶粒群組之間。所述TIM設置在所述第一晶粒、所述第二晶粒群組及所述底部填充層上。所述黏合劑圖案設置在所述底部填充層與所述TIM之間，以將所述底部填充層與所述TIM分隔開。
本發明實施例提供一種封裝結構包括第一晶粒、第二晶粒、中介層、底部填充層及熱界面材料(TIM)。所述第一晶粒及所述第二晶粒並排設置在所述中介層上。所述底部填充層設置在所述第一晶粒與所述第二晶粒之間。所述TIM設置在所述第一晶粒、所述第二晶粒及所述底部填充層上。所述TIM的邊緣厚度大於所述TIM的中心厚度。
本發明實施例提供一種形成封裝結構的方法包括：將第一晶粒及第二晶粒接合到中介層上；將底部填充層點膠在所述第一晶粒與所述第二晶粒之間；形成第一包封體，以橫向包封所述第一晶粒、所述第二晶粒及所述底部填充層；在所述第一晶粒與所述第二晶粒之間的所述底部填充層上及在所述第一包封體上形成黏合劑圖案；以及將熱界面材料(TIM)點膠在所述黏合劑圖案上。
10、20、30、40:封裝結構
10a:初始結構
100:封裝體
110:第一晶粒
110a、120a:前側
110b、120b:背側
110p、120p:周邊
110t、115t、120t、125t、150t’、270t:頂表面
112、122:晶粒連接件
115:底部填充層
120:第二晶粒
125:第一包封體
125s、130s:側壁
130:中介層
130a:上表面
130b:下表面
132:基底穿孔(TSV)
134:重佈線層(RDL)結構
135:第二包封體
136:導電連接件
140:被動裝置
150、150a、150b、450:黏合劑圖案
150bt:底表面
150bt’:底表面
150p:封裝結構的一部分
150t:頂表面
152、262:點膠器
154:開口
160、260、360:熱界面材料(TIM)
170、270:蓋
172:黏合劑
200:電路基底
202:接合墊
260t、270ct:凹頂表面
270ft:平坦頂表面
360t、362t、364t、T1、T2:厚度
362:第一金屬層
364:第二金屬層
365:複合結構
D1:距離
L1、L2:延伸長度
S1:第一界面
S2:第二界面
S3:第三界面
T3:邊緣厚度
T4:中心厚度
W1、W2:寬度
θ1、θ2:夾角
結合附圖閱讀以下詳細說明，會最佳地理解本揭露的各個態樣。應注意，根據本產業中的標準慣例，各種特徵並非按比例繪製。事實上，為使論述清晰起見，可任意增大或減小各種特 徵的尺寸。
圖1A至圖1C是根據第一實施例形成封裝結構的方法的剖視圖。
圖2是圖1C所示封裝結構的俯視圖。
圖3A及圖3B是圖1C所示封裝結構的一部分的放大視圖。
圖4A至圖4C是根據第二實施例形成封裝結構的方法的剖視圖。
圖5A至圖5D是根據第三實施例形成封裝結構的方法的剖視圖。
圖6是根據第四實施例的封裝結構的剖視圖。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本發明。當然，這些僅為實例而不旨在進行限制。例如，以下說明中將第一特徵形成在第二特徵之上或第二特徵上可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、以使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明可在各種實例中重複使用元件標號及/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「在...之下(beneath)」、「在...下面(below)」、「下部的(lower)」、「在..上方(above)」、「上部的(upper)」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(些)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外還囊括裝置在使用或操作中的不同定向。設備可具有其他定向(旋轉90度或其他定向)，且本文中所用的空間相對性描述語可同樣相應地進行解釋。
也可包括其他特徵及製程。例如，可包括測試結構，以說明對三維(3D)封裝或3DIC裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基底上形成的測試墊(test pad)，以便能夠對3D封裝或3DIC進行測試、對探針及/或探針卡(probe card)進行使用等。可對中間結構以及最終結構執行驗證測試。另外，可將本文中所公開的結構及方法與包括對已知良好晶粒進行中間驗證的測試方法結合使用，以提高良率並降低成本。
根據一些實施例，將多個黏合劑層選擇性地點膠在第一晶粒與多個第二晶粒之間的底部填充層上以及在第一晶粒及第二晶粒旁邊的包封體上。然後在第一晶粒、第二晶粒及黏合劑層上形成熱界面材料(thermal interface material，TIM)，使得黏合劑層由TIM包繞。在這種情況下，黏合劑層將TIM與底部填充層及包封體分隔開，以改善TIM與底部填充層及包封體之間的黏附性，從而減少脫層問題並提高可靠性。
圖1A至圖1C是根據第一實施例形成封裝結構的方法的 剖視圖。圖2是圖1C所示封裝結構的俯視圖。
參照圖1A至圖1C，形成封裝結構10(如圖1C所示)的方法包括以下步驟。首先，提供圖1A所示的初始結構10a。初始結構10a包括將封裝體100接合在電路基底200上所形成的基底上晶圓上晶片(chip-on-wafer-on-substrate，CoWoS)封裝體，然而應瞭解，實施例可應用於其他3DIC封裝體。
詳細來說，封裝體100可包括第一晶粒110、具有多個第二晶粒120的第二晶粒群組、底部填充層115、第一包封體125及中介層130。具體來說，第一晶粒110具有彼此相對的前側110a(即，主動表面)及背側110b(即，非主動表面)。每一第二晶粒120也具有彼此相對的前側120a(即，主動表面)及背側120b(即，非主動表面)。第一晶粒110及第二晶粒120被翻轉，使得第一晶粒110的前側110a及第二晶粒120的前側120a均面向中介層130的上表面130a。第一晶粒110及第二晶粒120通過多個晶粒連接件112、122接合到中介層130的上表面130a上，以形成晶圓上晶片(chip-on-wafer，CoW)封裝體，然而應瞭解，實施例可應用於其他3DIC封裝體。
在一些實施例中，第一晶粒110及第二晶粒120各自具有單一功能(例如，邏輯裝置、記憶體晶粒等)，或者可具有多種功能(例如，系統晶片(system-on-chip，SoC))。在特定實施例中，第一晶粒110是處理器，且第二晶粒120是記憶體模組。在一些替代實施例中，第一晶粒110被稱為晶粒堆疊，其包括兩個 被接合的積體電路晶粒。所述兩個積體電路晶粒通過混合接合、熔融接合、直接接合、介電接合、金屬接合等被接合，使得主動表面彼此面對(「面對面」)。在其他實施例中，第一晶粒110是處理器，例如中央處理器(central processing unit，CPU)、圖形處理器(graphics processing unit，GPU)、專用積體電路(application-specific integrated circuit，ASIC)等。在特定實施例中，第一晶粒110是系統晶片(SoC)。
在一些實施例中，第二晶粒120是記憶體裝置，例如動態隨機存取記憶體(dynamic random access memory，DRAM)晶粒、靜態隨機存取記憶體(static random access memory，SRAM)晶粒、混合記憶體立方體(hybrid memory cube，HMC)模組、高頻寬記憶體(high bandwidth memory，HBM)模組等。在特定實施例中，第二晶粒120是HBM模組。
如圖1A所示，在一些實施例中，晶粒連接件112、122由導電材料(例如焊料、銅、鋁、金、鎳、銀、鈀、錫等或其組合)形成。在特定實施例中，晶粒連接件112、122是包含夾置在兩個金屬層之間的焊料的微凸塊。另外，在晶粒連接件112、122與中介層130的上表面130a之間視需要設置有重佈線層(redistribution layer，RDL)結構134，以將晶粒連接件112、122與中介層130中的基底穿孔(through substrate via，TSV)132電連接。在一些實施例中，RDL結構134包括交替堆疊的多個聚合物層及多個重佈線層。重佈線層可形成在聚合物層中，以將晶粒 連接件112、122與TSV 132電連接。重佈線層分別包括彼此連接的多個通孔及多個跡線。在這種情況下，如圖1A所示，第一晶粒110及第二晶粒120可通過晶粒連接件112、122及RDL結構134電連接到中介層130中的TSV 132。
如圖1A所示，底部填充層115設置在第一晶粒110與第二晶粒120之間，且橫向包封晶粒連接件112、122。在一些實施例中，底部填充層115由任何可接受的材料(例如聚合物、環氧樹脂、模塑底部填充劑等)形成。底部填充層115可在第一晶粒110及第二晶粒120被貼合之後通過毛細管流動製程形成，或者可在第一晶粒110及第二晶粒120被貼合之前通過合適的沉積方法形成。
第一包封體125被設置成橫向包封底部填充層115及第二晶粒120。在一些實施例中，第一包封體125由任何可接受的材料(例如模塑化合物、環氧樹脂等)形成。第一包封體125可通過壓縮模塑(compression molding)、傳遞模塑(transfer molding)等形成。在一些其他實施例中，第一包封體125的填料的平均粒徑大於或等於底部填充層115的填料的平均粒徑。可在中介層130之上形成第一包封體125，使得第一晶粒110及第二晶粒120被掩埋或覆蓋。然後，使第一包封體125固化並通過化學機械拋光(chemical mechanical polishing，CMP)製程、研磨製程等對其進行平坦化，以暴露出第一晶粒110的背側110b(頂表面110t)及第二晶粒120的背側120b(頂表面120t)。在平坦化之後，如圖 1A所示，第一包封體125的頂表面125t、第一晶粒110的頂表面110t、第二晶粒120的頂表面120t以及底部填充層115的頂表面115t是實質上齊平或共面的。
在一些實施例中，通過對包括多個第一晶粒110及第二晶粒120、所述多個第一晶粒110及第二晶粒120上的底部填充層115及第一包封體125的晶圓執行單體化製程而形成封裝體100。作為單體化製程的結果，晶圓被單體化成多個中介層130，其中封裝體100中的每一者具有一個中介層130。在一些實施例中，單體化製程包括鋸切製程、雷射製程或其組合。在這種情況下，如圖1A所示，第一包封體125與中介層130的邊緣是相連的，即，第一包封體125的側壁125s與中介層130的側壁130s實質上對齊。
在單體化製程之後，通過多個導電連接件136將CoW封裝體100接合到電路基底200上。在一些實施例中，導電連接件136配置在中介層130的下表面130b上，以電連接及/或物理連接到電路基底200。導電連接件136可為球格陣列(ball grid array，BGA)連接件、焊料球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、微凸塊、由無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸塊等。在一些實施例中，通過例如蒸鍍、電鍍、印刷、焊料轉移、置球等此類常用方法首先形成焊料層來形成導電連接件136。一旦在結構上形成了焊料層，就可執行回焊，以將材料成形為所期望的凸塊形狀。
在一些實施例中，電路基底200由例如矽、鍺、金剛石等半導體材料製成。作為另一選擇，也可使用化合物材料，例如矽鍺、碳化矽、鎵砷、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、這些的組合等。另外，電路基底200可為絕緣體上矽(silicon on insulator，SOI)基底。一般來說，SOI基底包含一層半導體材料，例如外延矽、鍺、矽鍺、SOI、絕緣體上矽鍺(silicon germanium on insulator，SGOI)或其組合。在一個替代實施例中，電路基底200是基於絕緣芯，例如玻璃纖維增強樹脂芯。一種示例性芯材料是例如FR4等的玻璃纖維樹脂。芯材料的替代方案包括雙馬來醯亞胺-三嗪BT樹脂，或作為另一選擇包括其他印刷電路板(printed circuit board，PCB)材料或膜。可對電路基底200使用例如味之素增層膜(Ajinomoto Buildup Film，ABF)或其他積層體等的增層膜。
電路基底200可包括主動裝置及被動裝置(未示出)，例如電晶體、電容器、電阻器、這些的組合及可用於產生設計的結構及功能要求的類似裝置。電路基底200還可包括金屬化層及通孔(未示出)以及所述金屬化層及通孔之上的接合墊202。金屬化層可形成在主動裝置及被動裝置之上，且被設計成將各種裝置連接以形成功能電路系統。金屬化層可由交替的介電材料(例如低介電常數(low-k)介電材料)層與導電材料(例如銅)層形成(其中通孔內連各導電材料層)，且可通過任何合適的製程(例如沉積、鑲嵌、雙重鑲嵌等)來形成。在一些其他實施例中，電路基底200 實質上不含主動裝置及被動裝置。
在一些實施例中，導電連接件136貼合到接合墊202上，從而將中介層130接合到電路基底200。導電連接件136將電路基底200電連接及/或物理連接到封裝體100。在一些實施例中，多個被動裝置140(例如，表面安裝裝置(surface mount device，SMD))貼合到電路基底200(例如，接合到接合墊202)。在此種實施例中，被動裝置140與導電連接件136被接合到電路基底200的同一表面。導電連接件136在被回焊之前其上可形成有環氧助焊劑(未示出)，在封裝體100貼合到電路基底200之後，所述環氧助焊劑的環氧部分中的至少一些保留下來。此種保留的環氧部分可充當底部填充劑，以減小應力並保護因將導電連接件136回焊而產生的接縫。
如圖1A所示，形成第二包封體135以橫向包封導電連接件136、中介層130、第一包封體125的下側壁。在一個實施例中，第二包封體135由任何合適的底部填充材料(例如聚合物、環氧樹脂、模塑底部填充劑等)形成。第二包封體135可在封裝體100被貼合之後通過毛細管流動製程形成，或者可在封裝體100被貼合之前通過合適的沉積方法形成。
參照圖1B，通過點膠器152將黏合劑圖案150選擇性地點膠在第一晶粒110與第二晶粒120之間的底部填充層115上以及在第一包封體125上。在一些實施例中，黏合劑圖案150包含聚合物材料，例如液狀晶粒貼合膜(die attaching film，DAF)、聚 醯亞胺(polyimide，PI)系聚合物、環氧系聚合物等。在一些替代實施例中，黏合劑圖案150不含填料。
參照圖1B及圖1C，將熱界面材料(TIM)160點膠在第一晶粒110、第二晶粒120及黏合劑圖案150上。然後，將蓋170貼合到封裝體100及電路基底200，以形成封裝結構10。如圖1C所示，蓋170覆蓋並環繞封裝體100及被動裝置140。在一些實施例中，蓋170由具有高熱導率(k)的材料(例如鋼、不銹鋼、銅等或其組合)形成。在一些替代實施例(以下所論述)中，蓋170塗布有另一種金屬，例如金、鎳等。在一些其他實施例中，蓋170是單一連續材料。在另一實施例中，蓋170包括可為相同材料或不同材料的多個塊件。
具體來說，蓋170通過TIM 160黏附到封裝體100。TIM 160夾置在蓋170與第一晶粒110及第二晶粒120之間，以將蓋170與第一晶粒110及第二晶粒120熱耦合。另外，TIM 160被形成為足夠大的厚度以掩埋黏合劑圖案150。也就是說，如圖1C所示，黏合劑圖案150可由TIM 160環繞或包繞。在一些實施例中，黏合劑圖案150被形成為約0.5μm至100μm的高度，例如約10μm。TIM 160可被形成為約5μm至約300μm的厚度，例如約60μm。TIM的厚度大於黏合劑圖案150的高度或厚度。另一方面，蓋170通過黏合劑172黏附到電路基底200。在一些實施例中，黏合劑172是環氧樹脂、膠等。作為另一選擇，黏合劑172可為導熱材料。
在一些實施例中，第一晶粒110及第二晶粒120可陷獲 熱量而成為封裝結構10中的熱點。因此，TIM 160將封裝體100與蓋170熱耦合，以將熱量從第一晶粒110及第二晶粒120耗散到蓋170。應注意，黏合劑圖案150可設置在TIM 160與底部填充層115及/或第一包封體125之間，以改善TIM 160與底部填充層115及/或第一包封體125之間的黏附性，從而減少脫層問題並提高可靠性。從剖視圖1C來看，黏合劑圖案150可包括彼此橫向間隔開的多個黏合劑層。也就是說，黏合劑層離散地分布在第一晶粒110與第二晶粒120之間的底部填充層115上以及第一包封體125上。黏合劑圖案150將TIM 160與底部填充層115及/或第一包封體125分隔開，使得TIM 160不與底部填充層115及/或第一包封體125(物理)接觸。
在一些實施例中，TIM 160及黏合劑圖案150具有不同的材料。TIM 160的熱導率(k)可大於黏合劑圖案150的熱導率。在這種情況下，TIM 160的與第一晶粒110及第二晶粒120的頂表面110t、120t接觸的區域可被稱為用於將熱量從第一晶粒110及第二晶粒120耗散的熱路徑。在一些實施例中，TIM 160由具有較高熱導率(k)的材料(例如Ag、Cu、Sn、In、碳奈米管(carbon nanotube，CNT)、石墨等)形成。黏合劑圖案150可由具有較低熱導率(k)的材料(例如液狀晶粒貼合膜(DAF)、聚醯亞胺(PI)系聚合物、環氧系聚合物等)形成。在一些實施例中，TIM 160的熱導率(k)為約0.5Wm-1K-1至約200Wm-1K-1或者約10Wm-1K-1至約50Wm-1K-1，例如約10Wm-1K-1。黏合劑圖案150的熱導率 (k)可為約0.5Wm-1K-1至約100Wm-1K-1或者約0.5Wm-1K-1至約10Wm-1K-1，例如約2Wm-1K-1。
在一些替代實施例中，TIM 160由例如聚合物材料、焊料膏、銦焊料膏等的另一種材料形成。在一些替代實施例中，TIM 160的熱導率(k)為約0.5Wm-1K-1至約200Wm-1K-1或者約10Wm-1K-1至約50Wm-1K-1，例如約10Wm-1K-1。
在一些實施例中，由於黏合劑圖案150及TIM 160具有不同的材料，因此在黏合劑圖案150與TIM 160之間包括第一界面S1。在一些其他實施例中，TIM 160具有多種填料，而黏合劑圖案150不含填料。因此，TIM 160中的填料可環繞黏合劑圖案150的上表面，以形成第一界面S1。
類似地，黏合劑圖案150及底部填充層115可具有不同的材料，因此在黏合劑圖案150與底部填充層115之間包括第二界面S2。在一些其他實施例中，底部填充層115具有多種填料，而黏合劑圖案150不含填料。因此，底部填充層115中的填料可環繞黏合劑圖案150的下表面，以形成第二界面S2。另外，黏合劑圖案150及第一包封體125具有不同的材料，因此在黏合劑圖案150與第一包封體125之間包括第三界面S3。在一些其他實施例中，第一包封體125具有多種填料，而黏合劑圖案150不含填料。因此，第一包封體125中的填料可環繞黏合劑圖案150的下表面，以形成第三界面S3。
從俯視圖2來看，封裝結構10包括並排設置的第一晶粒 110及第二晶粒120。在本實施例中，第一晶粒110是SoC，且第二晶粒120是HBM模組。詳細來說，第一晶粒110的面積可大於第二晶粒120之一的面積。第二晶粒120的數目可大於第一晶粒110的數目。第二晶粒120設置在第一晶粒110的兩側處。第一晶粒110及第二晶粒120可通過RDL結構134、中介層130及電路基底200彼此電連接，如圖1C所示。如俯視圖2所示，黏合劑圖案150具有多個開口154，以暴露出第一晶粒110及第二晶粒120。換句話說，黏合劑圖案150設置在底部填充層115及第一包封體125上，以在俯視圖中環繞第一晶粒110的周邊110p及第二晶粒120的周邊120p。在替代實施例中，黏合劑圖案150包括分別設置在第一晶粒110與第二晶粒120之間的底部填充層115上的兩個黏合劑層。換句話說，所述兩個黏合劑層可沿著第一晶粒110的兩側(例如，右側及左側)設置。在其他實施例中，在俯視圖中，黏合劑圖案150包括離散地分布並環繞第一晶粒110的周邊110p及第二晶粒120的周邊120p的多個點結構。
在一些實施例中，黏合劑圖案150的佈局面積小於整個封裝體100的佈局面積。例如，黏合劑圖案150的佈局面積對封裝體100的佈局面積的比率為約5%至約99%。
圖3A及圖3B是圖1C所示封裝結構10的一部分150p的放大視圖。
參照圖3A，黏合劑圖案150a形成並限制在底部填充層115上，而不延伸到第一晶粒110及第二晶粒120的頂表面110t、 120t上。詳細來說，黏合劑圖案150a的寬度W1可實質上等於或小於第一晶粒100與相鄰的第二晶粒120之間的距離D1。在一些實施例中，寬度W1為約10μm至約300μm，例如100μm。距離D1可為約10μm至約300μm，例如100μm。另外，黏合劑圖案150a可具有平坦底表面150bt及彎曲頂表面150t。在一些實施例中，黏合劑圖案150a的底表面150bt與第一晶粒110及第二晶粒120的頂表面110t、120t實質上對齊。黏合劑圖案150a的彎曲頂表面150t可為沿著從底表面150bt到頂表面150t的方向突出的凸表面。在黏合劑圖案150a的頂表面150t與底表面150bt之間有夾角θ1，其中夾角θ1可為銳角。在一些實施例中，夾角θ1為約5度至約85度，例如45度。另外，黏合劑圖案150a的厚度T1沿著從中心到邊緣的方向逐漸減小。例如，黏合劑圖案150a的最高厚度T1為約0.5μm至100μm，例如約10μm。
參照圖3B，黏合劑圖案150b不僅覆蓋在底部填充層115上，而且延伸覆蓋第一晶粒110及第二晶粒120的頂表面110t、120t的一部分。在這種情況下，黏合劑圖案150b還覆蓋並保護底部填充層115與第一晶粒110及第二晶粒120之間的界面，從而避免缺陷。具體來說，黏合劑圖案150b的寬度W2可大於第一晶粒100與相鄰的第二晶粒120之間的距離D1。在一些實施例中，寬度W2為約10μm至約300μm，例如140μm。在這種情況下，黏合劑圖案150b可與第一晶粒110及第二晶粒120的頂表面110t、120t的一部分接觸。黏合劑圖案150b可具有從第一晶粒110與底 部填充層115之間的界面到黏合劑圖案150b的右邊緣而測量的延伸長度L1。另外，黏合劑圖案150b可具有從第二晶粒120與底部填充層115之間的界面到黏合劑圖案150b的左邊緣而測量的另一延伸長度L2。在一個實施例中，延伸長度L1與延伸長度L2相同。在另一實施例中，延伸長度L1不同于延伸長度L2。舉例來說，延伸長度L1為約3μm至60μm，例如約20μm。延伸長度L2可為約3μm至60μm，例如約20μm。在黏合劑圖案150b的頂表面150t’與底表面150bt’之間具有夾角θ2，其中夾角θ2可為銳角。在一些實施例中，夾角θ2為約5度至約85度，例如45度。在一個實施例中，夾角θ2小於夾角θ1。在其他實施例中，夾角θ2大於或實質上等於夾角θ1。另外，黏合劑圖案150b的厚度T2也沿著從中心到邊緣的方向逐漸減小。例如，黏合劑圖案150b的最高厚度T2為約0.5μm至100μm，例如約10μm。
圖4A至圖4C是根據第二實施例形成封裝結構的方法的剖視圖。
參照圖4A，提供CoWoS封裝體10a。結構、材料及功能可類似於圖1A中所示及參照圖1A所論述的結構、材料及功能。因此本文中不再對細節予以贅述。
參照圖4B，通過點膠器262將TIM 260點膠在第一晶粒110、第二晶粒120、底部填充層115及第一包封體125上。在一些實施例中，TIM 260包含具有較高熱導率(k)的材料，例如Ag、Cu、Sn、In、碳奈米管(CNT)、石墨等。應注意，TIM 260的邊 緣厚度T3大於或實質上等於TIM 260的中心厚度T4。較厚的邊緣厚度T3可在TIM 260與邊緣包封體125之間提供更好的黏附性，從而減少脫層問題並提高高翹曲區域的可靠性。較薄的中心厚度T4可實現更好的熱耗散，尤其是從第一晶粒110(例如，SoC或GPU)的熱耗散。在一些實施例中，邊緣厚度T3為約5μm至約400μm，例如約200μm；中心厚度T4為約3μm至約300μm，例如約100μm；邊緣厚度T3對中心厚度T4的比率(T3/T4)為約1.1至約5，例如約2。在這種情況下，TIM 260的邊緣厚度T3及/或中心厚度T4的特定範圍可提供比更薄TIM更好的覆蓋性及比更厚TIM更好的熱耗散。也就是說，當邊緣厚度T3小於5μm且中心厚度T4小於3μm時，TIM 260可能具有不良的覆蓋性，而未完全覆蓋下伏結構。另一方面，當邊緣厚度T3大於400μm且中心厚度T4大於300μm時，TIM 260可能具有不良的熱耗散。
參照圖4C，然後將蓋270貼合到封裝體100及電路基底200，以形成封裝結構20。如圖4C所示，蓋270覆蓋並環繞封裝體100及被動裝置140。具體來說，蓋270通過TIM 260黏附到封裝體100，且通過黏合劑172黏附到電路基底200。由於TIM 260具有較厚的邊緣厚度T3及較薄的中心厚度T4，因此TIM 260具有凹頂表面260t。凹頂表面260t可沿著從第一晶粒110到中介層130的方向凹陷。此外，蓋270可共形地覆蓋TIM 260的凹頂表面260t，且具有與TIM 260的凹頂表面260t對應的凹頂表面270ct。如圖4C所示，蓋270具有頂表面270t，頂表面270t包括平坦頂 表面270ft及凹頂表面270ct。凹頂表面270ct由平坦頂表面270ft環繞。平坦頂表面270ft高於凹頂表面270ct。TIM 260及蓋270的佈置及材料類似於TIM 160及蓋170的佈置及材料，且已在上述實施例中詳細闡述。因此，此處省略其細節。
圖5A至圖5D是根據第三實施例形成封裝結構的方法的剖視圖。
參照圖5A，提供CoWoS封裝體10a。結構、材料及功能可類似於圖1A中所示並參照圖1A所論述的結構、材料及功能。因此本文中不再對細節予以贅述。
參照圖5B，在封裝體100上形成第一金屬層362。第一金屬層362可在封裝體100被單體化之前或之後形成在封裝體100上。第一金屬層362可由導電材料或金屬(例如Ag、Au、Ti、NiV、Al、TiN、Cu、Sn等或其組合)形成。可通過在中介層130之上(例如，在第一包封體125、第一晶粒110及第二晶粒120以及底部填充層115上)沉積晶種層且然後將導電材料電鍍到晶種層上來形成第一金屬層362。也可通過將導電材料濺鍍到封裝體100上來形成第一金屬層362。在一些實施例中，第一金屬層362是毯覆式地覆蓋第一包封體125、第一晶粒110及第二晶粒120以及底部填充層115的連續結構。在一些實施例中，第一金屬層362是電性浮置的。也就是說，第一金屬層362可與第一晶粒110及第二晶粒120的主動裝置及/或被動裝置以及其他周圍裝置電絕緣。
參照圖5C及圖5D，然後將TIM 360點膠在第一金屬層 362上。TIM 360的材料類似於TIM 160的材料，且已在上述實施例中詳細地闡述。因此，此處省略其細節。然後，將塗布有第二金屬層364的蓋170貼合到封裝體100及電路基底200，以形成封裝結構30。在這種情況下，如圖5D所示，第一金屬層362、第二金屬層364及夾置在第一金屬層362與第二金屬層364之間的TIM 360構成複合結構365，以將蓋170與第一晶粒110及第二晶粒120熱耦合。第二金屬層364可由導電材料或金屬(例如Ag、Au、Ti、NiV、Al、TiN、Cu、Sn等或其組合)形成。可通過沉積晶種層且然後將導電材料電鍍到晶種層上來形成第二金屬層364。也可通過將導電材料濺鍍到蓋170的內表面上來形成第二金屬層364。在一些實施例中，第二金屬層364是覆蓋TIM 360的連續結構。在一些實施例中，第二金屬層364是電性浮置的。也就是說，第二金屬層364可與第一晶粒110及第二晶粒120的主動裝置及/或被動裝置以及其他周圍裝置電隔離。作為另一選擇，可省略第二金屬層364，且TIM 360與蓋170接觸。
在一些實施例中，第一金屬層362及第二金屬層364具有相同的材料或不同的材料。在一些實施例中，第一金屬層362的厚度362t實質上等於第二金屬層364的厚度364t。第一金屬層362的厚度362t可為約0.1μm至約10μm，例如約1μm。第二金屬層364的厚度364t可為約0.1μm至約10μm，例如約1μm。在這種情況下，厚度362t及/或厚度364t的特定範圍可提供比更薄金屬層更好的覆蓋性及比更厚金屬層更好的熱耗散。也就是說， 當厚度362t及/或厚度364t小於0.1μm時，第一金屬層362及/或第二金屬層364可能具有不良的覆蓋性，而未完全覆蓋下伏結構。另一方面，當厚度362t及/或厚度364t大於10μm時，第一金屬層362及/或第二金屬層364可能具有不良的熱耗散。在一些替代實施例中，第一金屬層362的厚度362t小於或大於第二金屬層364的厚度364t。在一些實施例中，TIM 360的厚度360t大於或實質上等於第一金屬層362的厚度362t及/或第二金屬層364的厚度364t。TIM 360的厚度360t可為約3μm至約300μm，例如約60μm。
應注意，第一金屬層362可改善TIM 360與封裝體100(尤其是底部填充層115及第一包封體125)之間的黏附性，從而減少脫層問題並提高可靠性。換句話說，第一金屬層362可被稱為黏合劑膜、層或圖案。類似地，第二金屬層364可改善TIM 360與蓋170之間的黏附性，從而減少脫層問題並提高可靠性。第二金屬層364也可被稱為黏合劑膜、層或圖案。此外，包括夾置在第一金屬層362與第二金屬層364之間的TIM 360的複合結構365可具有高熱導率，且可適形于封裝體100的形狀，包括適形于封裝體100中可能已引入的任何翹曲。如此一來，封裝結構30的總熱阻可降低。
圖6示出具有黏合劑圖案450及TIM 260的封裝結構40。具體來說，將黏合劑圖案450點膠在底部填充層115上。然後，在黏合劑圖案450、第一包封體125以及第一晶粒110及第二晶粒 120上點膠具有不同厚度的TIM 260，使得黏合劑圖案450由TIM 260環繞。黏合劑圖案450的材料類似於黏合劑圖案150的材料，且已在上述實施例中詳細闡述。因此，此處省略其細節。在這種情況下，封裝結構40可具有由封裝結構10及20組合成的優點。也就是說，黏合劑圖案450可改善TIM 260與底部填充層115之間的黏附性。較厚的邊緣厚度T3可改善TIM 260與邊緣包封體125之間的黏附性，從而減少脫層問題並提高高翹曲區域的可靠性。較薄的中心厚度T4可實現更好的熱耗散，尤其是從第一晶粒110(例如，SoC或GPU)的熱耗散。在一些實施例中，黏合劑圖案450形成並限制在底部填充層115上。在一些其他實施例中，黏合劑圖案450延伸以覆蓋第一晶粒110及第二晶粒120的一部分。在一些實施例中，黏合劑圖案450的佈局面積小於圖2所示的黏合劑圖案150的佈局面積。例如，黏合劑圖案450的佈局面積對封裝體100的佈局面積的比率為約5%至約99%。作為另一選擇，黏合劑圖案450可視需要形成在第一包封體125上，以將第一包封體125與TIM 260分隔開。
根據一些實施例，一種封裝結構包括第一晶粒、第二晶粒群組、中介層、底部填充層、熱界面材料(TIM)及黏合劑圖案。所述第一晶粒及所述第二晶粒群組並排設置在所述中介層上。所述底部填充層設置在所述第一晶粒與所述第二晶粒群組之間。所述TIM設置在所述第一晶粒、所述第二晶粒群組及所述底部填充層上。所述黏合劑圖案設置在所述底部填充層與所述TIM之間， 以將所述底部填充層與所述TIM分隔開。
在一些實施例中，所述第二晶粒群組包括至少一個第二晶粒或多個第二晶粒，所述多個第二晶粒分別設置在所述第一晶粒的兩側處，且所述黏合劑圖案包括離散地分布在所述第一晶粒與所述多個第二晶粒之間的所述底部填充層上的多個黏合劑層。在一些實施例中，上述的封裝結構更包括橫向包封所述第一晶粒、所述多個第二晶粒及所述底部填充層的包封體，其中所述多個黏合劑層的一部分設置在所述包封體與所述熱界面材料之間，以將所述包封體與所述熱界面材料分隔開。在一些實施例中，所述包封體的側壁與所述中介層的側壁實質上對齊。在一些實施例中，所述多個黏合劑層中的一者具有彎曲頂表面，且具有沿著從中心到邊緣的方向減小的厚度。在一些實施例中，所述黏合劑圖案從所述底部填充層的頂表面延伸，以覆蓋所述第一晶粒的頂表面的一部分及所述第二晶粒群組的頂表面的一部分。在一些實施例中，在所述黏合劑圖案與所述熱界面材料之間具有第一界面，且在所述黏合劑圖案與所述底部填充層之間具有第二界面。在一些實施例中，所述熱界面材料具有多種填料，且所述黏合劑圖案不含填料。在一些實施例中，所述黏合劑圖案包括延伸以覆蓋所述第一晶粒及所述第二晶粒群組的第一金屬層。在一些實施例中，上述的封裝結構，更包括：電路基底，接合到所述中介層；蓋，黏附到所述電路基底、所述第一晶粒及所述第二晶粒群組，所述蓋覆蓋並環繞所述第一晶粒及所述第二晶粒群組；以及第二金屬層， 設置在所述熱界面材料與所述蓋之間，其中包括所述熱界面材料、所述第一金屬層及所述第二金屬層的複合結構將所述蓋與所述第一晶粒及所述第二晶粒群組熱耦合。在一些實施例中，所述第一金屬層及所述第二金屬層均為電性浮置的。在一些實施例中，所述熱界面材料的邊緣厚度大於所述熱界面材料的中心厚度。在一些實施例中，所述熱界面材料的熱導率大於所述黏合劑圖案的熱導率。
根據一些實施例，一種封裝結構包括第一晶粒、第二晶粒、中介層、底部填充層及熱界面材料(TIM)。所述第一晶粒及所述第二晶粒並排設置在所述中介層上。所述底部填充層設置在所述第一晶粒與所述第二晶粒之間。所述TIM設置在所述第一晶粒、所述第二晶粒及所述底部填充層上。所述TIM的邊緣厚度大於所述TIM的中心厚度。
在一些實施例中，上述的封裝結構，更包括：電路基底，接合到所述中介層；被動裝置，接合到所述電路基底；以及蓋，黏附到所述電路基底、所述第一晶粒及所述第二晶粒，所述蓋覆蓋並環繞所述被動裝置、所述第一晶粒及所述第二晶粒。在一些實施例中，所述熱界面材料具有第一凹頂表面，所述蓋共形地覆蓋所述熱界面材料的所述第一凹頂表面，且所述蓋具有與所述第一凹頂表面對應的第二凹頂表面。
根據一些實施例，一種形成封裝結構的方法包括：將第一晶粒及第二晶粒接合到中介層上；將底部填充層點膠在所述第 一晶粒與所述第二晶粒之間；形成第一包封體，以橫向包封所述第一晶粒、所述第二晶粒及所述底部填充層；在所述第一晶粒與所述第二晶粒之間的所述底部填充層上及在所述第一包封體上形成黏合劑圖案；以及將熱界面材料(TIM)點膠在所述黏合劑圖案上。
在一些實施例中，所述形成所述黏合劑圖案包括：形成延伸以覆蓋所述第一晶粒及所述第二晶粒的第一金屬層。在一些實施例中，上述的方法更包括：在所述熱界面材料上形成第二金屬層，使得所述第一金屬層、所述熱界面材料及所述第二金屬層形成為複合結構；將所述中介層接合到電路基底上；以及將蓋黏附到所述電路基底及所述複合結構上，其中所述複合結構將所述蓋與所述第一晶粒及所述第二晶粒熱耦合。在一些實施例中，所述黏合劑圖案被形成為具有在剖視圖中彼此橫向間隔開的多個黏合劑層。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本揭露的各個態樣。熟習此項技術者應理解，他們可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本揭露的精神及範圍，而且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替及變更。
10:封裝結構
100:封裝體
110:第一晶粒
112、122:晶粒連接件
115:底部填充層
120:第二晶粒
125:第一包封體
130:中介層
132:基底穿孔(TSV)
134:重佈線層(RDL)結構
135:第二包封體
136:導電連接件
140:被動裝置
150:黏合劑圖案
150p:封裝結構的一部分
160:熱界面材料(TIM)
170:蓋
172:黏合劑
200:電路基底
202:接合墊
S1:第一界面
S2:第二界面
S3:第三界面

Claims (10)

  1. 一種封裝結構，包括：第一晶粒及第二晶粒群組，並排設置在中介層上；底部填充層，設置在所述第一晶粒與所述第二晶粒群組之間；熱界面材料，設置在所述第一晶粒、所述第二晶粒群組及所述底部填充層上；黏合劑圖案，設置在所述底部填充層與所述熱界面材料之間，以將所述底部填充層與所述熱界面材料分隔開；以及蓋，通過所述熱界面材料黏附到所述第一晶粒及所述第二晶粒群組上，其中所述黏合劑圖案被所述熱界面材料包繞而不與所述蓋接觸。
  2. 如請求項1所述的封裝結構，其中所述第二晶粒群組包括至少一個第二晶粒或多個第二晶粒，所述多個第二晶粒分別設置在所述第一晶粒的兩側處，且所述黏合劑圖案包括離散地分布在所述第一晶粒與所述多個第二晶粒之間的所述底部填充層上的多個黏合劑層。
  3. 如請求項2所述的封裝結構，更包括橫向包封所述第一晶粒、所述多個第二晶粒及所述底部填充層的包封體，其中所述多個黏合劑層的一部分設置在所述包封體與所述熱界面材料之間，以將所述包封體與所述熱界面材料分隔開。
  4. 如請求項1所述的封裝結構，其中所述黏合劑圖案從所述底部填充層的頂表面延伸，以覆蓋所述第一晶粒的頂表面的一部分及所述第二晶粒群組的頂表面的一部分。
  5. 如請求項1所述的封裝結構，其中所述黏合劑圖案包括延伸以覆蓋所述第一晶粒及所述第二晶粒群組的第一金屬層。
  6. 如請求項5所述的封裝結構，更包括：電路基底，接合到所述中介層；所述蓋，黏附到所述電路基底，其中所述蓋覆蓋並環繞所述第一晶粒及所述第二晶粒群組；以及第二金屬層，設置在所述熱界面材料與所述蓋之間，其中包括所述熱界面材料、所述第一金屬層及所述第二金屬層的複合結構將所述蓋與所述第一晶粒及所述第二晶粒群組熱耦合。
  7. 如請求項6所述的封裝結構，其中所述第一金屬層及所述第二金屬層均為電性浮置的。
  8. 如請求項1所述的封裝結構，其中所述熱界面材料的熱導率大於所述黏合劑圖案的熱導率。
  9. 一種封裝結構，包括：第一晶粒及第二晶粒，並排設置在中介層上；底部填充層，設置在所述第一晶粒與所述第二晶粒之間；熱界面材料，設置在所述第一晶粒、所述第二晶粒及所述底部填充層上，其中所述熱界面材料的邊緣厚度大於所述熱界面材料的中心厚度； 黏合劑圖案，設置在所述底部填充層與所述熱界面材料之間，以將所述底部填充層與所述熱界面材料分隔開；以及蓋，通過所述熱界面材料黏附到所述第一晶粒及所述第二晶粒上，其中所述黏合劑圖案被所述熱界面材料包繞而不與所述蓋接觸。
  10. 一種形成封裝結構的方法，包括：將第一晶粒及第二晶粒接合到中介層上；將底部填充層點膠在所述第一晶粒與所述第二晶粒之間；形成第一包封體，以橫向包封所述第一晶粒、所述第二晶粒及所述底部填充層；在所述第一晶粒與所述第二晶粒之間的所述底部填充層上及在所述第一包封體上形成黏合劑圖案；將熱界面材料點膠在所述黏合劑圖案上；以及將蓋通過所述熱界面材料黏附到所述第一晶粒及所述第二晶粒上，其中所述黏合劑圖案被所述熱界面材料包繞而不與所述蓋接觸。
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Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
US11239136B1 (en) * 2020-07-28 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Adhesive and thermal interface material on a plurality of dies covered by a lid

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170263518A1 (en) * 2016-03-11 2017-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated Fan-Out Package Including Voltage Regulators and Methods Forming Same
TW201913920A (zh) * 2017-08-31 2019-04-01 台灣積體電路製造股份有限公司 半導體元件及其製造方法
US20200219786A1 (en) * 2019-01-08 2020-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Package Structure and Method and Equipment for Forming the Same

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7168484B2 (en) * 2003-06-30 2007-01-30 Intel Corporation Thermal interface apparatus, systems, and methods
US7183641B2 (en) * 2005-03-30 2007-02-27 Intel Corporation Integrated heat spreader with intermetallic layer and method for making
US7651938B2 (en) * 2006-06-07 2010-01-26 Advanced Micro Devices, Inc. Void reduction in indium thermal interface material
US20090057884A1 (en) * 2007-08-29 2009-03-05 Seah Sun Too Multi-Chip Package
US7678615B2 (en) * 2007-08-29 2010-03-16 Advanced Micro Devices, Inc. Semiconductor device with gel-type thermal interface material
US8304291B2 (en) * 2009-06-29 2012-11-06 Advanced Micro Devices, Inc. Semiconductor chip thermal interface structures
US8039304B2 (en) * 2009-08-12 2011-10-18 Stats Chippac, Ltd. Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structures
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US10770405B2 (en) * 2017-05-31 2020-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal interface material having different thicknesses in packages
CN108717939B (zh) * 2018-06-01 2020-06-12 京东方科技集团股份有限公司 静电释放保护电路、阵列基板和显示装置
US10756058B2 (en) * 2018-08-29 2020-08-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US11935799B2 (en) * 2019-06-25 2024-03-19 Intel Corporation Integrated circuit package lids with polymer features
US11705417B2 (en) * 2019-10-08 2023-07-18 Intel Corporation Backside metallization (BSM) on stacked die packages and external silicon at wafer level, singulated die level, or stacked dies level
CN113035788A (zh) * 2019-12-25 2021-06-25 台湾积体电路制造股份有限公司 封装结构及其制作方法
US11239134B2 (en) * 2020-01-17 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
US11239136B1 (en) * 2020-07-28 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Adhesive and thermal interface material on a plurality of dies covered by a lid
US11469197B2 (en) * 2020-08-26 2022-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170263518A1 (en) * 2016-03-11 2017-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated Fan-Out Package Including Voltage Regulators and Methods Forming Same
TW201913920A (zh) * 2017-08-31 2019-04-01 台灣積體電路製造股份有限公司 半導體元件及其製造方法
US20200219786A1 (en) * 2019-01-08 2020-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Package Structure and Method and Equipment for Forming the Same

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