CN107978583B - 封装结构及其制造方法 - Google Patents

封装结构及其制造方法 Download PDF

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CN107978583B
CN107978583B CN201710975893.5A CN201710975893A CN107978583B CN 107978583 B CN107978583 B CN 107978583B CN 201710975893 A CN201710975893 A CN 201710975893A CN 107978583 B CN107978583 B CN 107978583B
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substrate
circuit carrier
conductive
package structure
die
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CN107978583A (zh
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王启安
徐宏欣
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Powertech Technology Inc
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Powertech Technology Inc
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Abstract

本发明提供一种封装结构及其制造方法。封装结构包含电路载体、衬底、晶粒、多根导电线以及密封体。衬底设置于电路载体上且包含多个开口。晶粒设置于电路载体与衬底之间。导电线穿过衬底的开口以电性连接在衬底与电路载体之间。密封体设置于电路载体上且密封晶粒、衬底以及导电线。

Description

封装结构及其制造方法
技术领域
本发明大体上涉及一种封装结构(package structure)及其制造方法，尤其涉及一种半导体封装结构(semiconductor package structure)。
背景技术
为了使电子产品设计实现轻、薄、短且小，半导体封装技术正持续进步，以尝试开发出体积较小、重量较轻、集成度较高且更具市场竞争力的产品。举例来说，已开发例如封装等3D堆叠技术以满足较高封装密度的要求。因此，对于本领域研究人员来说，如何以较低制造成本增加输入/输出(Input/output，I/O)连接的数目已成为挑战。
发明内容
本发明提供一种封装结构及其制造方法，其降低制造成本且增加I/O连接的数目。
本发明提供一种封装结构制造方法。所述方法至少包含以下步骤。设置晶粒于电路载体上。设置衬底于晶粒上。衬底包含多个开口。形成穿过衬底的开口的多根导电线，以在衬底与电路载体之间形成电性连接。形成密封体在电路载体上，以密封晶粒、衬底以及导电线。
在本发明的一实施例中，晶粒是经由倒装芯片接合而设置于电路载体上。
在本发明的一实施例中，设置衬底于晶粒上是使用粘着层将衬底与晶粒彼此粘附。
在本发明的一实施例中，导电线是经由打线机形成。
在本发明的一实施例中，在衬底上形成开口，其中开口环绕晶粒的外围。
本发明提供一种封装结构，包含电路载体、衬底、晶粒、多根导电线以及密封体。衬底设置于电路载体上且包含多个开口。晶粒设置于电路载体与衬底之间。导电线穿过衬底的开口，以在衬底与电路载体之间电性连接。密封体设置于电路载体上且密封晶粒、衬底以及导电线。
在本发明的一实施例中，封装结构进一步包括设置于电路载体与衬底之间的粘着层。
在本发明的一实施例中，晶粒包括面向电路载体的多个导电凸块，且晶粒经由导电凸块电性连接到电路载体。
在本发明的一实施例中，导电线中的每一者的线弧高度大于衬底的与电路载体相对的表面及电路载体的面向衬底的表面之间的距离。
在本发明的一实施例中，开口环绕晶粒的外围而布置于衬底上。
基于上述，设置于晶粒上的衬底有利于形成导电线。此外，衬底可以作为用于进一步电性连接的导电界面。此外，因为通孔形成于密封体上以暴露出衬底的至少一部分，因此使得封装结构更灵活以与不同装置应用兼容。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A到图1D为说明根据本发明的实施例的封装结构制造方法的剖面示意图；
图2为说明根据本发明的实施例的封装结构的衬底的俯视示意图；
图3为说明根据本发明的实施例的封装结构的剖面示意图；
图4为说明根据本发明的实施例的封装结构的剖面示意图。
附图标号说明
10、20、30：封装结构；
110：电路载体；
112：核心层；
114：顶部电路层；
114a、116a：导电衬垫；
116：底部电路层；
118：导电结构；
120：晶粒；
122：导电凸块；
130：衬底；
130a：开口；
130b：导电层；
130c：表面；
140：粘着层；
150：导电线；
150a：第一区段；
150b：中心区段；
150c：第二区段；
160：密封体；
160a：通孔；
160b：表面；
170：导电元件；
200：半导体元件；
202：导电结构；
D1、D3：距离；
D2：深度；
H：高度；
S1：顶表面；
S2：底表面。
具体实施方式
图1A到图1D为说明根据本发明的实施例的封装结构制造方法的剖面示意图。图2为说明根据本发明的实施例的封装结构的衬底的俯视示意图。参考图1A，提供电路载体(circuit carrier)110。电路载体110可以具有顶表面S1以及与顶表面S1相对的底表面S2。举例来说，电路载体110可以包含核心层112(core layer)、设置于顶表面S1上的顶部电路层114以及设置于电路载体110的底表面S2上的底部电路层116。换句话说，核心层112设置于顶部电路层114与底部电路层116之间，且电性连接顶部电路层114与底部电路层116。在一些实施例中，顶部电路层114可以包含多个导电衬垫(conductive pad)114a，且底部电路层116可以包含用于电性连接的多个导电衬垫116a。此外，顶部电路层114的导电衬垫114a与底部电路层116的导电衬垫116a可以是由相同材料如铜、焊料、金、镍等等，以及例如光刻(photolithography)和蚀刻(etching)工艺等相同工艺形成。在其它实施例中，顶部电路层114的导电衬垫114a与底部电路层116的导电衬垫116a可以根据设计要求而由不同材料和/或不同工艺形成。
核心层112可以包含作为中间电路层以电性连接顶部电路层114与底部电路层116的多个嵌入电路层。举例来说，核心层112可以包含基底层(base layer)以及穿透所述基底层的多个导电通孔(conductive vias)。此外，核心层112的导电通孔的两个相对末端可以电性连接到顶部电路层114的导电衬垫114a以及底部电路层116的导电衬垫116a。在一些实施例中，电路载体110可以包含形成于底表面S2上的多个导电结构118。举例来说，导电结构118的材料可以包含铜、锡、金、镍或其它合适导电材料，并不限于此。此外，导电结构118可以例如为导电凸块(conductive bump)、导电柱(conductive pillar)或通过植球工艺(ball placement process)以及回焊工艺(reflow process)形成的焊球(solder ball)。可以利用其它可能的形式和形状的导电结构118，以进行进一步的电性连接。在一些实施例中，导电结构118可以根据后续工艺的需要，而形成布置于电路载体110的底表面S2上的带微间距的阵列(fine pitched array)。
此外，晶粒(die)120接合于电路载体110的顶表面S1上。晶粒120可以经由倒装芯片接合(flip-chip bonding)而电性连接到电路载体110。在一些实施例中，晶粒120的有源面(active surface)(未示出)可以经由面向电路载体110的多个导电凸块122而连接到电路载体110的顶部电路层114的导电衬垫114a。导电凸块122可以是铜凸块(copper bumps)。在一些实施例中，焊料(solders)(未示出)可以施加到导电凸块122的表面上，以与电路载体110的顶部电路层114的导电衬垫114a耦合。此外，晶粒120可以是例如专用集成电路(Application-Specific Integrated Circuit，ASIC)。在一些实施例中，晶粒120可以用来执行逻辑应用(logic applications)，但本发明并不以此为限。其它合适有源装置也可以作为晶粒120。此外，底胶(underfill)(未示出)可以形成于电路载体110的顶表面S1上，并且形成于晶粒120的有源面与电路载体110的顶表面S1之间的间隙中，以增强晶粒接合工艺的可靠性(reliability)。
参考图1B以及图2，衬底130设置于晶粒120上。衬底130可以包含多个开口130a。衬底130的材料可以包含导电材料(例如铝、铜、镍、金或其合金等)、非导电材料(例如玻璃、刚性塑料(rigid plastic)等)或其组合。其它合适的材料可以适用为衬底130，只要材料能够耐受在其上执行的处理工艺即可。此外，本发明并不限制衬底130的大小、形状以及厚度。此外，衬底130的开口130a可以经由机械钻孔、光刻以及蚀刻或其它合适的方法形成，并不限于此。此外，参考图2，衬底130的开口130a可以形成于衬底130上，环绕晶粒120的外围。此外，开口130a可以与晶粒120错开(staggered)。本发明并不限制开口130a的数目。
在一些实施例中，导电层130b可以利用物理气相沉积(physical vapordeposition，PVD)、化学气相沉积(chemical vapor deposition，CVD)、电镀或其它合适的金属沉积工艺而形成于与衬底130的晶粒120相对的表面130c上，但不限于此。导电层130b的材料可以包含铝、铜、金、银或其它合适的导电材料，但本发明并不以此为限。在其它实施例中，导电层130b可以经图案化以形成为多个导电连接器(conductive connectors)，例如接触衬垫(如铝衬垫、铜衬垫等)。换句话说，衬底130不仅作为用于执行后续电接合处理的导电连接器，而且提供隔板(spacer)功能，以防止损坏晶粒120。
衬底130可以是经由粘着层(adhesive layer)140接合到晶粒120。在一些实施例中，粘着层140可以是晶粒附着膜(die attach film)或由包含环氧树脂(epoxy resin)的粘着材料形成。粘着层140可以通过例如旋涂(spin coating)、喷墨印刷(injectprinting)或其它合适的方法或用于提供结构支撑的其它合适方法而形成，而不需要晶粒120与衬底130之间的机械夹持。
参考图1C，衬底130与电路载体110通过穿过衬底130的开口130a的多根导电线150而电性连接。举例来说，导电线150可以经由打线机(wire bonder)(未示出)形成。打线机的类型可以根据设计要求而包含楔型接合(wedge bond)、球型接合(ball bond)或其它合适的打线机。此外，导电线150连接于衬底130的导电层130b与电路载体110之间。导电线150的材料可以是金、铜或其它合适材料，并不限于此。在一些实施例中，导电线150可以从衬底130形成到电路载体110。在其它实施例中，导电线150可以从电路载体110形成到衬底130。导电线150的形成顺序可以取决于设计要求。在一些实施例中，因为导电线150形成于衬底130的导电层130b与电路载体110之间且穿过衬底130的开口130a，因此衬底130的开口130a的大小可以是足够大的尺寸，以使打线机通过。
此外，导电线150中的每一者的顶端(peak)(未示出)定义为在连接衬底130与电路载体110之后，相对于导电线150中的每一者的两个末端之间的最高点。此外，导电线150中的每一者的线弧(loop)高度H定义为导电线150中的每一者的顶端与电路载体110之间的距离。导电线150中的每一者的线弧高度H的数值取决于打线机的类型和/或设计要求。
此外，导电线150中的每一者可以包含第一区段150a、中心区段150b以及第二区段150c。第一区段150a可以连接到电路载体110，第二区段150c可以连接到衬底130，且中心区段150b可以是第一区段150a与第二区段150c之间的区段。在一些实施例中，第一区段150a可以形成于衬底130下方，且第二区段150c可以形成于衬底130上方。导电线150中的每一者的第二区段150c可以形成为弧形(arc shape)。此外，导电线150中的每一者的顶端可以是第二区段150c的最高点。此外，中心区段150b可以穿过对应的衬底130的开口130a。在一些实施例中，导电线150中的每一者的线弧高度H可以大于衬底130的表面130c与电路载体110的顶表面S1之间的距离D1。
参考图1D，密封体(encapsulant)160形成于电路载体110上，以密封晶粒120、衬底130、粘着层140以及导电线150。在一些实施例中，密封体160的厚度大于导电线150的线弧高度H。此外，密封体160可以包含通过模制工艺(molding process)形成的模制化合物(molding compound)。在一些实施例中，密封体160可以通过例如环氧树脂、树脂、可模制聚合物(moldable polymer)或其它合适的树脂等绝缘材料形成，但本发明不限于此。
因此，封装结构10具有堆叠于晶粒120上的衬底130，衬底130作为用于执行打线工艺的导电界面，且不必在封装结构10内形成额外中介层(interposer)来进行进一步的电性连接。以此方式，可以实现制造成本较低的简化的制造方法。
图3为说明根据本发明的实施例的封装结构的剖面示意图。参考图3，封装结构20的制造方法类似于图1A到图1D中所说明的实施例的制造方法。本文中省略详细描述。本实施例与图1A到图1D中所说明的实施例之间的差异在于，多个通孔160a可以形成于密封体160上，通孔160a从密封体160的表面160b延伸到衬底130的表面130c，以暴露出衬底130的至少一部分，以便在电路载体110上形成密封体160之后形成封装结构20，如图1D中所示。
举例来说，可以通过激光烧蚀(laser ablation)、激光钻孔、机械钻孔或其它合适的方法移除密封体160以形成通孔160a。本发明并不限制通孔160a的数目。此外，举例来说，可以通过激光的功率(power)、激光的移动速度和/或其它工艺参数(processing factors)来控制通孔160a中的每一个的深度D2。在一些实施例中，通孔160a中的每一个的深度D2可以等于衬底130的表面130c与密封体160的最远离电路载体110的表面160b之间的距离D3。在一些实施例中，通孔160a的一部分可以形成在对应于晶粒120的区域内。因为衬底130提供隔板功能，因此在形成在对应于晶粒120的区域内的通孔160a的部分时，晶粒120的可靠性可不受影响。
在一些实施例中，通孔160a可以与衬底130的开口130a错开。由此，在密封体160上形成通孔160a时，导电线150可不受影响，藉此来确保衬底130与电路载体110之间的电性连接。在一些实施例中，通孔160a可以对应于导电层130b而形成，藉以形成导电通孔。由此，通孔160a可以作为封装结构20与外部连接器之间的导电路径。此外，封装结构20可以实现微间距(fine pitch)要求，且增加I/O连接的数目。因此，封装结构20可以与高端装置应用以及I/O连接的数目较多且每个晶粒的衬垫间距较窄的高级前端技术节点(advanced front-end technology node)兼容。
图4为说明根据本发明的实施例的封装结构的剖面示意图。参考图4，封装结构30的制造方法类似于图3中所说明的实施例的制造方法。本文中省略详细描述。如图4中所示，通孔160a可以用导电元件170填充，且半导体元件200可以堆叠于密封体160上，并且电性连接到衬底130，以形成封装结构30。
举例来说，填充于通孔160a中的导电元件170可以形成为导电凸块、导电柱、导电衬垫或其它导电连接器。在一些实施例中，可以通过将导电材料(例如，铝、铜、镍、金、银、焊料或合金等)沉积于密封体160的表面160b上且经由蒸镀(evaporation)、电镀(electro-plating)、植球(ball drop)、网版印刷(screen printing)或其它合适的方法填充通孔160a来形成导电元件170。此外，导电材料可以经由光刻以及蚀刻工艺加以图案化，以形成导电元件170。然而，本发明中不限制导电元件170的材料以及其形成工艺。由此，在用导电元件170填充通孔160a之后，导电元件170与电路载体110的导电结构118位于半导体封装结构30的两个相对的侧边上，由此增加I/O连接的数目。
在一些实施例中，可以通过膏体印刷工艺(paste print process)来用焊料填充通孔160a，以实现球栅阵列(ball grid array，BGA)互连。在其它实施例中，通孔160a可以用来作为增层(build up)互连结构(例如导电元件170)，以进一步电性连接到半导体元件200。在其它实施例中，半导体元件200可以包含动态随机存取存储器(DRAM)、NAND快闪存储器或其它合适的有源装置，其不限于此。此外，半导体元件200可以进一步包含对应地耦接到例如导电元件170的多个导电结构202。此外，导电结构202可以是导电凸块、导电柱或通过植球工艺以及回焊工艺形成的焊球。换句话说，半导体元件200可以堆叠于密封体160上，且经由导电元件170、衬底130以及导电线150电性连接到电路载体110，以形成封装结构30。
在一些实施例中，封装结构30可以称为堆叠封装(package-on-package，POP)结构。因为衬底130可以作为导电界面且通孔160a形成于密封体160上以暴露出衬底130的至少一部分，因此，封装结构可利于进一步的电性连接。由此，使得封装结构更灵活以与不同装置应用兼容。
基于上述，设置于晶粒上的衬底不仅利于形成导电线，而且提供隔板功能，以防止在后续工艺中损坏晶粒。此外，当在通孔形成于密封体上，以暴露出衬底的至少一部分时，导电线可以作为用于进一步电性连接的导电界面。因此，封装结构可以实现微间距要求，并且增加I/O连接的数目。由此，使得封装结构更灵活以与不同装置应用兼容。据此，可以较低制造成本开启各种封装设计的可能性。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中技术人员，在不脱离本发明的精神和范围内，当可作些许的更改与润饰，故本发明的保护范围当视权利要求书所界定的为准。

Claims (10)

1.一种封装结构制造方法，其特征在于，包括：
设置晶粒于电路载体的顶表面上；
设置衬底于所述晶粒上，其中所述衬底包括多个开口，且所述多个开口与所述晶粒错开；
形成穿过所述衬底的所述开口的多根导电线，以在所述衬底与所述电路载体之间形成电性连接；
形成密封体在所述电路载体上，以密封所述晶粒、所述衬底以及所述导电线；以及
形成多个导电结构于所述电路载体相对所述顶表面的底表面上。
2.根据权利要求1所述的封装结构制造方法，其特征在于，其中所述导电线中的每一者包括连接到所述电路载体的第一区段、连接到所述衬底的第二区段以及连接于所述第一区段与所述第二区段之间的中心区段，所述第一区段形成于所述衬底下方，所述第二区段形成于所述衬底上方，且所述中心区段形成于对应的所述衬底的所述开口中的任一者内。
3.根据权利要求1所述的封装结构制造方法，其特征在于，进一步包括：
形成多个通孔在所述密封体上，以暴露出所述衬底的至少一部分。
4.根据权利要求3所述的封装结构制造方法，其特征在于，其中所述通孔的深度为所述衬底的最远离所述电路载体的表面与所述密封体的最远离所述电路载体的表面之间的距离。
5.根据权利要求3所述的封装结构制造方法，其特征在于，进一步包括：
用导电元件填充所述通孔；以及
设置半导体元件于所述密封体上，且经由所述通孔将所述半导体元件电性连接到所述衬底。
6.一种封装结构，其特征在于，包括：
电路载体；
衬底，设置于所述电路载体的顶表面上，其中所述衬底包括多个开口，且所述多个开口与晶粒错开；
所述晶粒，设置于所述电路载体与所述衬底之间；
多根导电线，穿过所述衬底的所述开口，以电性连接在所述衬底与所述电路载体之间；
密封体，设置于所述电路载体上，其中所述密封体密封所述晶粒、所述衬底以及所述导电线；以及
多个导电结构，设置于所述电路载体相对所述顶表面的底表面上。
7.根据权利要求6所述的封装结构，其特征在于，其中所述导电线中的每一者包括连接到所述电路载体的第一区段、连接到所述衬底的第二区段以及连接于所述第一区段与所述第二区段之间的中心区段，所述第一区段设置于所述衬底下方，所述第二区段设置于所述衬底上方，且所述中心区段设置于对应的所述衬底的所述开口中的任一者内。
8.根据权利要求6所述的封装结构，其特征在于，其中所述密封体包括暴露出所述衬底的至少一部分的多个通孔。
9.根据权利要求8所述的封装结构，其特征在于，其中所述通孔的深度为所述衬底的最远离所述电路载体的表面与所述密封体的最远离所述电路载体的表面之间的距离。
10.根据权利要求8所述的封装结构，其特征在于，其中所述密封体包括设置于所述通孔中的导电元件，所述封装结构还包括设置于所述密封体上的半导体元件，其中所述半导体元件经由所述通孔电性连接到所述衬底。
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Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102018103505A1 (de) * 2018-02-16 2019-08-22 Osram Opto Semiconductors Gmbh Komposithalbleiterbauelement und Verfahren zur Herstellung eines Komposithalbleiterbauelements
US10748831B2 (en) * 2018-05-30 2020-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages having thermal through vias (TTV)
TWI674708B (zh) * 2018-08-31 2019-10-11 唐虞企業股份有限公司 晶片封裝結構半成品、晶片封裝結構模組與晶片封裝結構的製造方法
TWI733056B (zh) * 2018-09-19 2021-07-11 矽品精密工業股份有限公司 電子封裝件及其製法
CN111106096B (zh) * 2018-10-26 2024-01-05 恒劲科技股份有限公司 半导体封装结构及其制作方法
US20210320096A1 (en) * 2018-10-26 2021-10-14 Phoenix Pioneer Technology Co., Ltd. Manufacturing method for semiconductor package structure
TWI680553B (zh) * 2018-10-26 2019-12-21 英屬開曼群島商鳳凰先驅股份有限公司 半導體封裝結構及其製作方法
US10629575B1 (en) * 2018-12-13 2020-04-21 Infineon Techologies Ag Stacked die semiconductor package with electrical interposer
US11476200B2 (en) * 2018-12-20 2022-10-18 Nanya Technology Corporation Semiconductor package structure having stacked die structure
TWI733093B (zh) * 2019-03-14 2021-07-11 力成科技股份有限公司 半導體封裝結構及其製造方法
TWI700796B (zh) * 2019-05-23 2020-08-01 矽品精密工業股份有限公司 電子封裝件及其製法
US11587881B2 (en) * 2020-03-09 2023-02-21 Advanced Semiconductor Engineering, Inc. Substrate structure including embedded semiconductor device
US11335646B2 (en) 2020-03-10 2022-05-17 Advanced Semiconductor Engineering, Inc. Substrate structure including embedded semiconductor device and method of manufacturing the same
US20210320085A1 (en) * 2020-04-09 2021-10-14 Nanya Technology Corporation Semiconductor package
US11600562B2 (en) * 2020-10-21 2023-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and method of manufacturing the same
TWI749860B (zh) * 2020-11-10 2021-12-11 菱生精密工業股份有限公司 晶片封裝方法
TWI798647B (zh) * 2021-02-23 2023-04-11 華泰電子股份有限公司 電子封裝件及其製法
US11791326B2 (en) 2021-05-10 2023-10-17 International Business Machines Corporation Memory and logic chip stack with a translator chip
US11715731B2 (en) * 2021-08-29 2023-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
CN113611618A (zh) * 2021-09-28 2021-11-05 深圳新声半导体有限公司 用于芯片系统级封装的方法和芯片系统级封装结构

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1289143A (zh) * 1999-09-17 2001-03-28 株式会社日立制作所 半导体器件及其生产工艺

Family Cites Families (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6861290B1 (en) * 1995-12-19 2005-03-01 Micron Technology, Inc. Flip-chip adaptor package for bare die
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US20070003731A1 (en) * 2005-06-29 2007-01-04 Micron Technology, Inc. Gold-semiconductor phase change memory for archival data storage
US8026611B2 (en) * 2005-12-01 2011-09-27 Tessera, Inc. Stacked microelectronic packages having at least two stacked microelectronic elements adjacent one another
JP2009044110A (ja) * 2007-08-13 2009-02-26 Elpida Memory Inc 半導体装置及びその製造方法
TW200910564A (en) * 2007-08-17 2009-03-01 United Test Ct Inc Multi-substrate block type package and its manufacturing method
JP2009088254A (ja) * 2007-09-28 2009-04-23 Toshiba Corp 電子部品パッケージ及び電子部品パッケージの製造方法
US8188586B2 (en) * 2007-11-01 2012-05-29 Stats Chippac Ltd. Mountable integrated circuit package system with mounting interconnects
TW201023308A (en) 2008-12-01 2010-06-16 Advanced Semiconductor Eng Package-on-package device, semiconductor package and method for manufacturing the same
US7955942B2 (en) * 2009-05-18 2011-06-07 Stats Chippac, Ltd. Semiconductor device and method of forming a 3D inductor from prefabricated pillar frame
KR101624973B1 (ko) * 2009-09-23 2016-05-30 삼성전자주식회사 패키지 온 패키지 타입의 반도체 패키지 및 그 제조방법
US8421210B2 (en) * 2010-05-24 2013-04-16 Stats Chippac Ltd. Integrated circuit packaging system with dual side connection and method of manufacture thereof
US8349658B2 (en) * 2010-05-26 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframe
US8105872B2 (en) * 2010-06-02 2012-01-31 Stats Chippac, Ltd. Semiconductor device and method of forming prefabricated EMI shielding frame with cavities containing penetrable material over semiconductor die
KR101855294B1 (ko) * 2010-06-10 2018-05-08 삼성전자주식회사 반도체 패키지
TWI421955B (zh) * 2010-06-30 2014-01-01 矽品精密工業股份有限公司 具壓力感測器之微機電結構及其製法
US9159708B2 (en) * 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8581997B2 (en) * 2010-10-28 2013-11-12 Intellectual Ventures Fund 83 Llc System for locating nearby picture hotspots
US8970028B2 (en) * 2011-12-29 2015-03-03 Invensas Corporation Embedded heat spreader for package with multiple microelectronic elements and face-down connection
TWI409885B (zh) * 2011-05-16 2013-09-21 矽品精密工業股份有限公司 具微機電元件之封裝結構及其製法
US8389329B2 (en) * 2011-05-31 2013-03-05 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
US8754514B2 (en) * 2011-08-10 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip wafer level package
US9142502B2 (en) 2011-08-31 2015-09-22 Zhiwei Gong Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits
US8404520B1 (en) * 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8372741B1 (en) * 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9040346B2 (en) * 2012-05-03 2015-05-26 Infineon Technologies Ag Semiconductor package and methods of formation thereof
US9559039B2 (en) * 2012-09-17 2017-01-31 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using substrate having base and conductive posts to form vertical interconnect structure in embedded die package
US9508674B2 (en) * 2012-11-14 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control of semiconductor die package
KR20140083657A (ko) * 2012-12-26 2014-07-04 하나 마이크론(주) 인터포저가 임베디드 되는 전자 모듈 및 그 제조방법
US9368438B2 (en) * 2012-12-28 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package (PoP) bonding structures
US9378982B2 (en) * 2013-01-31 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
US8970023B2 (en) * 2013-02-04 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming same
DE202013100760U1 (de) * 2013-02-20 2014-05-22 Eugster/Frismag Ag Kaffeemaschine
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
KR20140130921A (ko) * 2013-05-02 2014-11-12 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9368475B2 (en) * 2013-05-23 2016-06-14 Industrial Technology Research Institute Semiconductor device and manufacturing method thereof
TWI539572B (zh) * 2013-05-23 2016-06-21 財團法人工業技術研究院 半導體裝置及其製造方法
JP6273362B2 (ja) 2013-12-23 2018-01-31 インテル コーポレイション パッケージ構造上のパッケージ及びこれを製造するための方法
US10049977B2 (en) 2014-08-01 2018-08-14 Qualcomm Incorporated Semiconductor package on package structure and method of forming the same
US9666730B2 (en) * 2014-08-18 2017-05-30 Optiz, Inc. Wire bond sensor package
US10177115B2 (en) * 2014-09-05 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming
US9679842B2 (en) * 2014-10-01 2017-06-13 Mediatek Inc. Semiconductor package assembly
CN105895610B (zh) 2014-11-18 2019-11-22 恩智浦美国有限公司 半导体装置以及具有竖直连接条的引线框
US9899248B2 (en) * 2014-12-03 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
KR102265243B1 (ko) * 2015-01-08 2021-06-17 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9613931B2 (en) * 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
US9595494B2 (en) * 2015-05-04 2017-03-14 Qualcomm Incorporated Semiconductor package with high density die to die connection and method of making the same
US9418926B1 (en) * 2015-05-18 2016-08-16 Micron Technology, Inc. Package-on-package semiconductor assemblies and methods of manufacturing the same
US9613942B2 (en) * 2015-06-08 2017-04-04 Qualcomm Incorporated Interposer for a package-on-package structure
US11018025B2 (en) * 2015-07-31 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution lines having stacking vias
KR102424402B1 (ko) * 2015-08-13 2022-07-25 삼성전자주식회사 반도체 패키지 및 그 제조방법
US10021790B2 (en) * 2016-02-26 2018-07-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Module with internal wire fence shielding
US9859258B2 (en) * 2016-05-17 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1289143A (zh) * 1999-09-17 2001-03-28 株式会社日立制作所 半导体器件及其生产工艺

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