US20180114786A1 - Method of forming package-on-package structure - Google Patents

Method of forming package-on-package structure Download PDF

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Publication number
US20180114786A1
US20180114786A1 US15/423,597 US201715423597A US2018114786A1 US 20180114786 A1 US20180114786 A1 US 20180114786A1 US 201715423597 A US201715423597 A US 201715423597A US 2018114786 A1 US2018114786 A1 US 2018114786A1
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Prior art keywords
semiconductor package
mold compound
substrate
package
conductive material
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US15/423,597
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English (en)
Inventor
Hung-Hsin Hsu
Chi-An Wang
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Powertech Technology Inc
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Powertech Technology Inc
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Priority to US15/423,597 priority Critical patent/US20180114786A1/en
Assigned to POWERTECH TECHNOLOGY INC. reassignment POWERTECH TECHNOLOGY INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HSU, HUNG-HSIN, WANG, CHI-AN
Priority to TW106122989A priority patent/TW201828370A/zh
Priority to CN201710594258.2A priority patent/CN107978532A/zh
Publication of US20180114786A1 publication Critical patent/US20180114786A1/en
Abandoned legal-status Critical Current

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a packaging method, and more particularly, to a method of forming a package-on-package (POP) structure.
  • POP package-on-package
  • POP Package-on-package
  • SMT surface mount technology
  • a POP structure includes at least two packages stacking onto one another, a common problem is that the thickness of a POP structure is too large and difficult to be reduced. For applications such as mobile devices, a large POP structure may be difficult to be embedded in a small device. Hence, a solution for reducing the thickness of a package structure is required in the field.
  • An embodiment provides a method of forming a package-on-package (POP) structure.
  • the method comprises performing a laser drilling on a mold compound of a first semiconductor package to form a plurality of through holes in the mold compound, forming a conductive layer on the mold compound such that the mold compound is covered by a conductive material and the through holes are filled with the conductive material, grinding the conductive layer to expose the mold compound, and stacking a second semiconductor package on the first semiconductor package such that a plurality of metal bumps of the second semiconductor package attach to the conductive material filled in the through holes.
  • POP package-on-package
  • FIGS. 1 to 6 are component cross-sectional views showing corresponding processing steps of the method of forming a package-on-package (POP) structure according to a first embodiment of the present invention.
  • POP package-on-package
  • FIGS. 7 to 12 are component cross-sectional views showing corresponding processing steps of the method of forming a POP structure according to a second embodiment of the present invention.
  • FIGS. 1 to 6 a method of forming a package-on-package (POP) structure is illustrated in FIGS. 1 to 6 for a cross-sectional view.
  • POP package-on-package
  • a first semiconductor package 100 is provided.
  • the first semiconductor package 100 comprises a first die 110 , a mold compound 120 , a plurality of conductive pads 132 , a substrate 140 and a plurality of metal bumps 150 .
  • the first die 110 and the conductive pads 132 are disposed on the substrate 140 and encapsulated by the mold compound 120 .
  • the metal bumps 150 are formed below the substrate 140 .
  • the first semiconductor package 100 is a flip-chip package, but the present invention is not limited thereto.
  • the first die 110 has a plurality of pillar bumps 112 disposed on the substrate 140 and electrically connected to some of the metal bumps 150 .
  • the pillar bumps 112 are used as an I/O interface of the first die 110 .
  • the substrate 140 may comprise a pad mask layer 130 and a plurality of conductive pillars 142 .
  • the conductive pillars 142 are formed in the substrate 140 and pass through the substrate 140 .
  • Some of the metal bumps 150 are electrically connected to the conductive pads 132 via the conductive pillars 142 .
  • the first semiconductor package 100 may be a fan-out package.
  • a laser drilling is performed on the mold compound 120 to form a plurality of through holes 122 in the mold compound 120 , such that the conductive pads 132 are exposed on bottoms of the through holes 122 .
  • a conductive layer 160 is formed on the mold compound 120 such that the mold compound 120 is covered by a conductive material and the through holes 122 are filled with the conductive material.
  • the conductive material may be copper (Cu), gold (Au) or a copper gold (Au-Cu) alloy.
  • the conductive layer 160 may be formed on the mold compound 120 by sputtering or electroplating the conductive material on the mold compound 120 .
  • the conductive layer 160 is grinded to expose the mold compound 120 . Accordingly, the conductive material filled in the through holes 122 forms a plurality of through hole vias 160 A.
  • the through hole vias 160 A are in contact with the conductive pads 132 .
  • a height H of each through hole via 160 A may range from 200 micrometers to 300 micrometers.
  • a distance D between bottoms of two adjacent through hole vias 160 A may be less than 300 micrometers.
  • the mold compound 120 may be grinded when grinding the conductive layer 160 . Since the conductive layer 160 and the mold compound 120 may be grinded, the thickness of the first semiconductor package 100 may be reduced.
  • the substrate 140 of the first semiconductor package 100 may be removed after the through hole vias 160 A are formed. Accordingly, the thickness of the first semiconductor package 100 may be further reduced.
  • a second semiconductor package 200 is stacked on the first semiconductor package 100 .
  • a plurality of metal bumps 250 of the second semiconductor package 200 are attached to the through hole vias 160 A when the second semiconductor package 200 is stacked on the first semiconductor package 100 .
  • the metal bumps 250 of the second semiconductor package 200 may be attached to the exposed surface of through hole vias 160 A by performing a reflow soldering process.
  • the first semiconductor package 100 and the second semiconductor package 200 are integrated as a package-on-package (POP) structure 300 . Since the through holes 122 are formed by performing a laser drilling, the POP structure 300 would be a fine pitch package.
  • the second semiconductor package 200 may be a fan-out package and/or a flip-chip package, but the present invention is not limited thereto.
  • the second semiconductor package 200 comprises a second die 210 , a mold compound 220 , a substrate 240 and the metal bumps 250 .
  • the second die 210 is disposed on the substrate 240 and encapsulated by the mold compound 220 .
  • the metal bumps 250 are formed below the substrate 240 .
  • the second die 210 is electrically connected to some of the metal bumps 150 of the first semiconductor package 100 via the metal bumps 250 of the second semiconductor package 200 , the through hole vias 160 A and the conductive circuit of the substrate 140 .
  • the second die 210 comprises a plurality of pillar bumps 212 .
  • the conductive pillars 242 are disposed in the substrate 240 and electrically connected to the metal bumps 250 .
  • FIGS. 7 to 12 another method of forming a POP structure is illustrated in FIGS. 7 to 12 for a cross-sectional view.
  • the same reference numbers used in the first embodiment and the second embodiment represent the same elements.
  • a first semiconductor package 400 according to another embodiment is provided.
  • the major difference between the two semiconductor packages 100 and 400 is that the first die 110 in FIG. 7 is coupled to the substrate 140 through wire bonding.
  • the first die 110 is coupled to a circuitry formed in the substrate 140 via a plurality of wires 114 .
  • the circuitry formed in the substrate 140 is electrically connected to some of the metal bumps 150 .
  • a laser drilling is performed on the mold compound 120 to form a plurality of through holes 122 in the mold compound 120 , such that the conductive pads 132 are exposed on bottoms of the through holes 122 .
  • a conductive layer 160 is form on the mold compound 120 such that the through holes 122 are filled with the conductive material and the mold compound 120 is covered by the conductive material.
  • the conductive layer 160 is grinded to expose the mold compound 120 .
  • the conductive material filled in the through holes 122 forms a plurality of through hole vias 160 A.
  • the through hole vias 160 A may be in contact with the conductive pads 132 .
  • a height H of each through hole via 160 A may be range from 200 micrometers to 300 micrometers.
  • a distance D between bottoms of two adjacent through hole vias 160 A may be less than 300 micrometers.
  • the mold compound 120 may be grinded when grinding the conductive layer 160 . Since the conductive layer 160 and the mold compound 120 may be grinded, the thickness of the first semiconductor package 400 may be reduced.
  • the second semiconductor package 200 is stacked on the first semiconductor package 400 .
  • a plurality of metal bumps 250 of the second semiconductor package 200 are attached to the through hole vias 160 A when the second semiconductor package 200 is stacked on the first semiconductor package 400 .
  • the metal bumps 250 of the second semiconductor package 200 may be bonded to the through hole vias 160 A of the first semiconductor package 400 by performing a reflow soldering process.
  • the first semiconductor package 400 and the second semiconductor package 200 are integrated as a package-on-package (POP) structure 500 .
  • POP package-on-package
  • a laser drilling is performed to form a plurality of through holes in the mold compound, and the through holes are filled with the conductive material to form a plurality of through hole vias.
  • the distance between the bottoms of two adjacent through hole vias may be less than 300 micrometers.
  • the POP structure would be a fine pitch package.
  • the conductive layer and the mold compound may be grinded, and the substrate of the first semiconductor package may be removed after the through hole vias are formed. Accordingly, the thickness of the POP structure would be reduced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
US15/423,597 2016-10-21 2017-02-03 Method of forming package-on-package structure Abandoned US20180114786A1 (en)

Priority Applications (3)

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US15/423,597 US20180114786A1 (en) 2016-10-21 2017-02-03 Method of forming package-on-package structure
TW106122989A TW201828370A (zh) 2016-10-21 2017-07-10 形成堆疊式封裝結構的方法
CN201710594258.2A CN107978532A (zh) 2016-10-21 2017-07-20 形成堆叠式封装结构的方法

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US201662410851P 2016-10-21 2016-10-21
US15/423,597 US20180114786A1 (en) 2016-10-21 2017-02-03 Method of forming package-on-package structure

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US15/717,944 Abandoned US20180114781A1 (en) 2016-10-21 2017-09-28 Package structure and manufacturing method thereof
US15/717,953 Abandoned US20180114782A1 (en) 2016-10-21 2017-09-28 Manufacturing method of package-on-package structure
US15/782,862 Expired - Fee Related US10170458B2 (en) 2016-10-21 2017-10-13 Manufacturing method of package-on-package structure
US15/787,712 Expired - Fee Related US10276553B2 (en) 2016-10-21 2017-10-19 Chip package structure and manufacturing method thereof

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US15/717,953 Abandoned US20180114782A1 (en) 2016-10-21 2017-09-28 Manufacturing method of package-on-package structure
US15/782,862 Expired - Fee Related US10170458B2 (en) 2016-10-21 2017-10-13 Manufacturing method of package-on-package structure
US15/787,712 Expired - Fee Related US10276553B2 (en) 2016-10-21 2017-10-19 Chip package structure and manufacturing method thereof

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US10276553B2 (en) 2019-04-30
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