TWI680553B - 半導體封裝結構及其製作方法 - Google Patents

半導體封裝結構及其製作方法 Download PDF

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Publication number
TWI680553B
TWI680553B TW107137896A TW107137896A TWI680553B TW I680553 B TWI680553 B TW I680553B TW 107137896 A TW107137896 A TW 107137896A TW 107137896 A TW107137896 A TW 107137896A TW I680553 B TWI680553 B TW I680553B
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Taiwan
Prior art keywords
substrate
conductive
wafer
layer
pads
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TW107137896A
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English (en)
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TW202017133A (zh
Inventor
胡竹青
Chu Chin Hu
許詩濱
Shih Ping Hsu
許哲瑋
Che Wei Hsu
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英屬開曼群島商鳳凰先驅股份有限公司
Phoenix & Corporation
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Priority to TW107137896A priority Critical patent/TWI680553B/zh
Priority to US16/659,716 priority patent/US20200135693A1/en
Application granted granted Critical
Publication of TWI680553B publication Critical patent/TWI680553B/zh
Publication of TW202017133A publication Critical patent/TW202017133A/zh
Priority to US17/355,252 priority patent/US20210320096A1/en

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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一種半導體封裝結構，包括一線路增層基板、一晶片、複數個導電柱、一模封層及至少一記憶體模組；線路增層基板具有第一表面及第二表面，分別暴露出複數個覆晶焊墊、複數個第一焊墊及複數個第二焊墊；晶片之第一面電性連接於該等覆晶焊墊；導電柱設於線路增層基板之第一表面，並分別電性連接於對應的第一焊墊；模封層設於線路增層基板之第一表面，且覆蓋晶片及導電柱；晶片之第二面及各導電柱之第一端係暴露於模封層；記憶體模組設於模封層上，並電性連接暴露於模封層之導電柱之第一端。本發明復提供上述半導體封裝結構之製作方法。

Description

半導體封裝結構及其製作方法
本發明是有關於一種封裝結構及其製作方法，且特別是有關於一種堆疊式封裝層疊的半導體封裝結構及其製作方法。
晶片封裝主要提供積體電路(IC)保護、散熱、電路導通等功能。隨晶圓製程技術演進，積體電路密度、傳輸速率及降低訊號干擾等效能需求提高，使得積體電路晶片封裝的技術要求逐漸增加。
為了整合多數的元件於一封裝體中，一種堆疊式層疊封裝(stacked package on package,PoP)技術於是被開發出來。堆疊式層疊封裝技術是將兩個或更多的元件，以垂直堆疊或是背部搭載的方式，在底層(基礎)封裝中整合高密度的數位或混合訊號邏輯元件，而在頂層(堆疊的)封裝中整合高密度或組合記憶體。相較於傳統並排排列方式的封裝，堆疊式層疊封裝占用更少的印刷電路板(printed circuit board,PCB)的版面並簡化電路板設計，可透過記憶體與邏輯電路的直接連線改善頻率效能表現。
再隨著技術的演進，又再發展出一種扇出型晶圓級封裝(Fan-out wafer level package,FOWLP)技術，又或稱之為整合型扇出封裝(Integrated Fan-out,InFO)技術，其優勢在於可省去載板，因而成本可較傳統的PoP封裝更為低廉，大幅節省晶片封裝的成本，並可應用於行動通訊裝置的處理器晶片(application processor,AP)或其他射頻(RF)、電源管理IC等大宗應用市場。
請搭配第1A圖至第1K圖所示，一種習知的整合型扇出封裝10的製作方法係包括下列步驟。如第1A圖，步驟S01係將一 晶片11放置於一玻璃基板12上。如第1B圖，步驟S02係形成一模封層13於玻璃基板12以及晶片11上，以覆蓋晶片11。如第1C圖，步驟S03係於模封層13形成複數個開孔131。如第1D圖，步驟S04係於開孔131中形成導電柱14。如第1E圖，步驟S05係將一載板15設置於模封層13以及導電柱14上。如第1F，步驟S06係將玻璃基板12移除而形成一半導體封裝半成品10a，並翻轉半導體封裝半成品10a，使得晶片11之一主動面111朝上。
再如第1G圖，步驟S07係於半導體封裝半成品10a上形成重分布層(redistribution layer,RDL)16，其依據所需的層數而分別執行下述子步驟：形成介電層，接著於介電層形成開孔，再接著於開孔中形成金屬層，最後研磨上表面。如第1G圖所示之重分布層16共包括十層金屬層，因此，其必須執行十次上述的子步驟，最後暴露於最上層表面的金屬層則作為連接焊墊161。
如第1H圖，步驟S08係於連接焊墊161上形成導電凸塊17a。如第1I圖，步驟S09係移除載板15以暴露出導電柱14之一端。如第1J圖，步驟S10，接著提供一記憶體模組18，並藉由導電凸塊17b而電性連接於導電柱14。最後如第1K圖，步驟S11係於導電凸塊17b周圍的空隙中形成介電層19，以完成整合型扇出封裝10。
承上所述，習知的整合型扇出封裝具有下列缺點：(1)晶片無法裸露，因而其散熱效果將被限制。(2)先設置晶片後，再於半導體封裝半成品上製作重分布層。倘若在製作重分布層的過程中因為失誤而導致產生不良品，則晶片將可能隨之報廢，或需要進行費時與費工的重工(rework)程序。
本發明之一目的係提供一種半導體封裝結構及其製作方法，能夠增加晶片的散熱能力以及避免因導電線路良率問題而造成晶片的陪葬耗損。
本發明之另一目的係提供一種半導體封裝結構及其製作方法，能夠優化製程及封裝結構而將記憶體各自獨立模組 化，因此可以僅針對有異常的記憶體模組進行重工更換，而無需將整組封裝件完全報廢，故可節省重工時所需的時間及成本。
為達上述目的，本發明提供之一種半導體封裝結構，係包括一線路增層基板、一晶片、複數個導電柱、一模封層以及至少一記憶體模組。線路增層基板具有相對之一第一表面及一第二表面，其中，第一表面係暴露出複數個覆晶焊墊及複數個第一焊墊，而第二表面係暴露出複數個第二焊墊。晶片具有相對之一第一面及一第二面，且晶片係以第一面面對於線路增層基板之第一表面，而電性連接於該等覆晶焊墊。導電柱具有相對之一第一端及一第二端，且係以第二端設置於線路增層基板之第一表面，並分別電性連接於對應的第一焊墊。模封層係設置於線路增層基板之第一表面上，而覆蓋晶片及導電柱，晶片之第二面及各導電柱之一第一端係暴露於模封層。記憶體模組係設置於模封層上，並電性連接暴露於模封層之導電柱之第一端。
於本發明之一實施例，半導體封裝結構更包含一導電黏著層，其係設置於導電柱的第二端與第一焊墊之間。
於本發明之一實施例，半導體封裝結構更包含一散熱元件，其係設置於記憶體模組上。
於本發明之一實施例，半導體封裝結構更包含一散熱元件，其係設置於晶片之第二面上。
於本發明之一實施例，其中晶片與記憶體模組於一正投影方向係不重疊的。
於本發明之一實施例，其中線路增層基板具有至少一線路增層結構。線路增層結構具有一導線層、一導電柱層及一介電層，且導線層及導電柱層係相互疊接，並嵌設於介電層中。
於本發明之一實施例，其中線路增層基板之該等第一焊墊係位於該等覆晶焊墊的周圍。
另外，為達上述目的，本發明提供之一種半導體封裝結構的製作方法，其包括下列步驟。提供一線路增層基板，其具有一第一表面，且第一表面暴露出複數個覆晶焊墊及位於該等 覆晶焊墊周圍之複數個第一焊墊。形成一嵌埋有一晶片及複數個導電柱之導電基板於該線路增層基板之該第一表面，該晶片之一第一面對應於該等覆晶焊墊設置，該等導電柱係以第二端分別對應於該等第一焊墊設置，而該晶片之一第二面及各導電柱之一第一端係暴露於該導電基板之一上表面。將至少一記憶體模組對應於該等導電柱之第一端，而設置於導電基板上。
於本發明製作方法之一實施例，形成嵌埋有晶片及該等導電柱之導電基板的步驟，係包括將該等導電柱以第二端對應於該等第一焊墊，而設置於線路增層基板之第一表面。將晶片之第一面對應於該等覆晶焊墊，而設置於線路增層基板之第一表面。形成一模封層於線路增層基板之第一表面上，以覆蓋該等導電柱及晶片，並暴露出各導電柱之第一端及晶片之第二面。
於本發明之一實施例，其中各導電柱係為一導電柱體(例如為銅柱)，係以第二端經由一導電黏著層而電性連接於對應的各第一焊墊。
於本發明製作方法之一實施例，其中，設置該等導電柱的步驟更包含形成一圖案化光阻層於線路增層基板之第一表面，並形成複數盲孔以暴露該等第一焊墊。形成一金屬層於該等盲孔及暴露之該等第一焊墊上。移除該圖案化光阻層，以形成該等導電柱及暴露出該等覆晶焊墊。
於本發明製作方法之一實施例，其中，形成嵌埋有晶片及該等導電柱之導電基板的步驟，係包含將晶片之第一面對應於該等覆晶焊墊，而設置於線路增層基板之第一表面。形成一模封層於線路增層基板之第一表面上，以覆蓋晶片。於模封層對應於該等第一焊墊形成複數個開孔。於開孔中形成複數個導電柱，以電性連接對應的該等第一焊墊。使模封層暴露出該等導電柱之一第一端及該晶片之一第二面。
於本發明製作方法之一實施例，半導體封裝結構的製作方法更包含設置一散熱元件於晶片之第二面及/或記憶體模組上。
10‧‧‧整合型扇出封裝
10a‧‧‧半導體封裝半成品
11‧‧‧晶片
111‧‧‧主動面
12‧‧‧玻璃基板
13‧‧‧模封層
131‧‧‧開孔
14‧‧‧導電柱
15‧‧‧載板
16‧‧‧重分布層
161‧‧‧連接焊墊
17a、17b‧‧‧導電凸塊
18‧‧‧記憶體模組
19‧‧‧介電層
20、30、40‧‧‧半導體封裝結構
21、31、41‧‧‧線路增層基板
211、311、411‧‧‧第一表面
212、312、412‧‧‧第二表面
213、313、413‧‧‧覆晶焊墊
214、314、414‧‧‧第一焊墊
215、315、415‧‧‧第二焊墊
21a、21b、21c‧‧‧線路增層結構
21a1‧‧‧導線層
21a2‧‧‧導電柱層
21a3‧‧‧介電層
22、32、42‧‧‧導電柱
221、321、421‧‧‧第一端
222、322‧‧‧第二端
223‧‧‧導電黏著層
23、33、43‧‧‧晶片
231、431‧‧‧第一面
232、332、432‧‧‧第二面
24、34、44‧‧‧模封層
27、37、47‧‧‧導電基板
25、35、45‧‧‧記憶體模組
261、262、263、361、362、363‧‧‧散熱元件
341‧‧‧開孔
46‧‧‧圖案化光阻層
461‧‧‧盲孔
462‧‧‧金屬層
D1‧‧‧投影方向
第1A圖至第1K圖繪示的是習知一種整合型扇出封裝的製程示意圖。
第2A圖至第2F圖繪示的是依據本發明第一實施例之半導體封裝結構的製程示意圖。
第3圖繪示的是本發明第一實施例之半導體封裝結構的俯視示意圖。
第3-1圖繪示的是本發明另一實施例之半導體封裝結構的俯視示意圖。
第4A圖至第4G圖是本發明第二實施例之半導體封裝結構的製程示意圖。
第5A圖至第5D圖是本發明第三實施例之半導體封裝結構的製程示意圖。
關於本發明之優點與精神可以藉由以下發明詳述及所附圖式得到進一步的瞭解。本發明較佳實施例之製造及使用係詳細說明如下。必須瞭解的是本發明提供了許多可應用的創新概念，在特定的背景技術之下可以做廣泛的實施。此特定的實施例僅以特定的方式表示，以製造及使用本發明，但並非限制本發明的範圍。
以下，請參照第2A圖至第2F圖，以說明本發明第一實施例之半導體封裝結構20的製作方法，其包括步驟S21至步驟S28。
步驟S21係如第2A圖所示，提供一線路增層基板21。線路增層基板21具有一第一表面211及一第二表面212。第一表面211係暴露出複數個覆晶焊墊213及複數個第一焊墊214，而第二表面212係暴露出複數個第二焊墊215。其中，線路增層基板21之該等第一焊墊214係位於該等覆晶焊墊213的周圍。
在本實施例中，線路增層基板21具有線路增層結構 21a、21b、21c。線路增層結構21a具有一導線層21a1、一導電柱層21a2及一介電層21a3。導線層21a1及導電柱層21a2係相互疊接以電性連接，並嵌設於介電層21a3之中。
導線層21a1及導電柱層21a2可包括導電金屬材料，例如銅、銀、鎳或其組成之合金。可利用微影蝕刻技術，配合額外之光阻層(圖中未顯示)執行曝光顯影工序，並執行電鍍工序以完成。
另外，線路增層結構21b、21c可與線路增層結構21a具有類似的結構組成，並且可藉由微影蝕刻以及金屬電鍍技術而完成，於此不再贅述。值得一提的是，在線路增層結構中，暴露出的導線層或導電柱層，則分別可成為覆晶焊墊213、第一焊墊214及第二焊墊215。
步驟S22係如第2B圖所示，將複數個材料為銅的導電柱22以第二端222對應於該等第一焊墊214，而設置於線路增層基板21之第一表面211。在本實施例中，導電柱22係先行製作成形，再分別以第二端222藉由例如為導電膠的導電黏著層223設置並電性連接於對應的第一焊墊214上。
步驟S23係如第2B圖所示，將一晶片23之一第一面231對應於該等覆晶焊墊213，而設置於線路增層基板21之第一表面211。晶片23可以是處理器晶片(application processor,AP)，其中第一面231係為其主動面，而與第一面231相對之一第二面232係為其背面。晶片23之第一面231係透過複數銲球(導電凸塊或導電膠等)而與覆晶焊墊213電性連接。在本實施例中，步驟S22以及步驟S23的執行順序係可相互調換，換句話說，在其他實施例中，可以先設置晶片23之後，再設置導電柱22。
值得一提的是，上述步驟S21開始的線路增層基板21係為一大版面形式的線路增層基板。於傳統之晶圓型式(wafer type)之製程中，僅能對於形成於單一晶圓內之晶粒(die)或晶片(chip)同時進行封裝製程，其較為耗時且具有製程上之諸多限制。相較於傳統之晶圓型式之封裝製程，本發明採用大版面型式 (panel type)之封裝製程；其中，如第2A圖，本發明之線路增層基板21之面積為單一晶圓面積之複數倍。據此，本發明之大尺寸線路增層基板21能夠對於切割自複數個晶圓之全部晶粒或晶片在經過步驟S23之製程後，同時進行後續封裝製程，而能有效節省製造時程。
接著，步驟S24係如第2C圖所示，形成一模封層24於線路增層基板21之第一表面211上，以覆蓋該等導電柱22及晶片23。模封層24的材料係例如為酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)或矽基樹脂(Silicone-Based Resin)的絕緣材料。另外，模封層24還可以是高填料含量介電材(high filler content dielectric material)，例如為鑄模化合物(molding compound)，其係以環氧樹脂(epoxy)為主要基質，其佔鑄模化合物之整體比例約為8%~12%，並摻雜佔整體比例約70%~90%的填充劑而形成。其中，填充劑可以包括二氧化矽及氧化鋁，以達到增加機械強度、降低線性熱膨脹係數、增加熱傳導、增加阻水及減少溢膠的功效。
步驟S25係如第2D圖所示，研磨模封層24之頂面，以暴露出各導電柱22之一第一端221及晶片23之第二面232。步驟至此，導電柱22、晶片23及模封層24係構成嵌埋有晶片23及導電柱22之導電基板27。
步驟S26係如第2E圖所示，將記憶體模組25設置於模封層24上，並且藉由銲球(導電膠或導電凸塊等)而電性連接於對應的導電柱22之第一端221。由於導電柱22係對應於線路增層基板21之第一焊墊214而設置，而第一焊墊214係位於覆晶焊墊213的周圍，因此記憶體模組25與晶片23於一正投影方向D1，可以如第3圖所示係不重疊的。據此，晶片23係可直接暴露而達到較佳的散熱效果。
在其他實施例中，記憶體模組25還可以如第3-1圖所示之配置設置。其中，記憶體模組25在俯視方向係圍設於晶片23的周圍，且於正投影方向D1亦不重疊。更甚者，記憶體模組25的 配置方式並無限制，主要係能夠暴露出晶片23為重點。
步驟S27係如第2E圖所示，將銲球(導電膠或導電凸塊等)設置並電性連接於第二焊墊215。根據不同的製程設備及技術，此步驟係可與步驟S26中設置銲球的步驟同時執行。
步驟S28係如第2F圖所示，將散熱元件261、262、263選擇性地設置於記憶體模組25以及晶片23之第二面232上，進一步增加散熱效率，並完成半導體封裝結構20。
承上所述，散熱元件261、262、263係選擇性地設置，倘若散熱效果已經足夠，則不需要再設置散熱元件。
接著，請再參照第4A圖至第4G圖，以說明依據本發明第二實施例之半導體封裝結構30的製作方法，其包括步驟S31至步驟S38。
步驟S31係如第4A圖所示，提供一線路增層基板31，並於線路增層基板31上設置一晶片33。線路增層基板31具有一第一表面311、第二表面312，且第一表面311暴露出複數個覆晶焊墊313及複數個第一焊墊314，而第二表面312暴露出複數個第二焊墊315。其中，線路增層基板31與晶片33之材料及結構皆與第一實施例之線路增層基板21與晶片23相同，於此不再贅述。
步驟S32係如第4B圖所示，形成一模封層34於線路增層基板31之第一表面311上，以覆蓋晶片33及線路增層基板31之第一表面311。
步驟S33係如第4C圖所示，利用雷射鑽孔(laser drilling)技術、機械鑽孔技術或其他鑽孔技術，於模封層34對應於該等第一焊墊314的位置形成複數個開孔341。
步驟S34係如第4D圖所示，於開孔341中填入(或電鍍)金屬材料以形成複數個導電柱32，以第二端322電性連接對應的該等第一焊墊314。
步驟S35係如第4E圖所示，研磨模封層34之頂面，以暴露出該等導電柱32之第一端321及晶片33之第二面332。步驟至此，導電柱32、晶片33及模封層34係構成嵌埋有導電柱32及晶片 33之導電基板37。
步驟S36係如第4F圖所示，將記憶體模組35設置於模封層34上，並且藉由銲球(導電膠或導電凸塊等)而電性連接於對應的導電柱32之第一端321。
步驟S37係如第4G圖所示，將銲球(導電膠或導電凸塊等)設置並電性連接於第二焊墊315。根據不同的製程設備及技術，此步驟係可與步驟S36中設置銲球的步驟同時執行。
步驟S38係如第4G圖所示，將散熱元件361、362、363選擇性地設置於記憶體模組35以及晶片33之第二面332上，進一步增加散熱效率，並完成半導體封裝結構30。
承上所述，散熱元件361、362、363係選擇性地設置，倘若散熱效果已經足夠，則不需要再設置散熱元件。
接著，請再參照第5A圖至第5D圖，以說明依據本發明第三實施例之半導體封裝結構40的製作方法，其包括步驟S41至步驟S51。
步驟S41係如第5A圖所示，提供一線路增層基板41。 線路增層基板41具有一第一表面411及一第二表面412。第一表面411係暴露出複數個覆晶焊墊413及複數個第一焊墊414，而第二表面412係暴露出複數個第二焊墊415。其中，線路增層基板41之該等第一焊墊414係位於該等覆晶焊墊413的周圍。
步驟S42，係於線路增層基板41之第一表面411形成一圖案化光阻層46。圖案化光阻層46上並形成複數盲孔461以暴露出該等第一焊墊414。
步驟S43係如第5B圖所示，形成一金屬層462於暴露之該等第一焊墊414上。其中，金屬層462可藉由電鍍工序而形成。
接著請參照第5C圖所示，步驟S44係移除圖案化光阻層46，以令該等金屬層462形成為複數個導電柱42及暴露出該等覆晶焊墊413。
步驟S45，係將一晶片43之一第一面431對應於該等覆晶焊墊413，而設置於線路增層基板41之第一表面411。晶片43 可以與前述之晶片23類似，於此不再加以贅述。
接著請參照第5D圖，步驟S46係形成一模封層44於線路增層基板41之第一表面411上，並包覆住該等導電柱42與晶片43，而後再研磨模封層44之頂面，以暴露出各導電柱42之一第一端421及晶片43之第二面432。步驟至此，導電柱42、晶片43及模封層44係構成嵌埋有導電柱42及晶片43之導電基板47。
步驟S47，係將記憶體模組45設置於模封層44上，並且藉由銲球(導電膠或導電凸塊等)而電性連接於對應的導電柱42之第一端421，以形成半導體封裝結構40(亦可再於晶片43之第二面432及/或記憶體模組45上選擇性地設置散熱元件)。
綜上所述，相較於習知技術，本發明之半導體封裝結構具有下列特點：
(1)晶片與記憶體模組於投影方像是不重疊的，因此晶片可以暴露出來，而不被記憶體模組等元件覆蓋，具有較佳的散熱效果。
(2)晶片的第二面及/記憶體模組上可以選擇性地設置散熱元件，而可進一步的增加散熱效果。
(3)記憶體模組係分別設置於模封層上，當部分的記憶體模組異常時，可僅針對有異常的記憶體模組重工更換處理，而無需將整組的封裝件報廢，因此可以節省成本與工時。
(4)相較於InFO封裝結構及製作方法是晶片前置(Die First)的特徵而言，本發明是晶片後置(Die Last)的特徵，所以本發明可以減省因為導電結構製程良率所造成的晶片陪葬率，因此能有效降地生產成本與提升產品良率。
以上所述僅為舉例性，而非為限制性者。任何未脫離本發明之精神與範疇，而對其進行之等效修改或變更，均應包括於後附之申請專利範圍中。

Claims (11)

  1. 一種半導體封裝結構，包含：一線路增層基板，具有相對之一第一表面及一第二表面，該第一表面暴露出複數個覆晶焊墊及複數個第一焊墊，該第二表面暴露出複數個第二焊墊；一晶片，具有相對之一第一面及一第二面，係以該第一面面對於該線路增層基板之該第一表面，而電性連接於該等覆晶焊墊；複數個導電柱，具有相對之第一端及第二端，係設置於該線路增層基板之該第一表面，並以第二端分別電性連接於對應之該等第一焊墊；一模封層，係設置於該線路增層基板之該第一表面上，而覆蓋該晶片及該等導電柱，該晶片之該第二面及各導電柱之一第一端係暴露於該模封層；以及複數個記憶體模組，係相互獨立地設置於該模封層上之不同位置而於一縱向投影方向互不重疊，並分別電性連接至暴露於該模封層之對應的該導電柱之該第一端，其中，該晶片與該等記憶體模組於該縱向投影方向互不重疊，並且該晶片係嵌埋於該模封層內部而與該等記憶體模組於一橫向投影方向互不重疊。
  2. 如請求項1所述之半導體封裝結構，更包含：一導電黏著層，設置於該等導電柱與該等第一焊墊之間。
  3. 如請求項1所述之半導體封裝結構，更包含一散熱元件，其係設置於該記憶體模組及/或該晶片之該第二面上。
  4. 如請求項1所述之半導體封裝結構，其中該線路增層基板具有至少一線路增層結構，該線路增層結構具有一導線層、一導電柱層及一介電層，該導線層及該導電柱層係相互疊接，並嵌設於該介電層中。
  5. 如請求項1所述之半導體封裝結構，其中該線路增層基板之該等第一焊墊係位於該等覆晶焊墊的周圍。
  6. 一種半導體封裝結構的製作方法，包含：提供一線路增層基板，該線路增層基板具有一第一表面，且該第一表面暴露出複數個覆晶焊墊及位於該等覆晶焊墊周圍之複數個第一焊墊；形成一嵌埋有一晶片及複數個導電柱之導電基板於該線路增層基板之該第一表面，該晶片之一第一面對應於該等覆晶焊墊設置，該等導電柱係以第二端分別對應於該等第一焊墊設置，而該晶片之一第二面及各導電柱之一第一端係暴露於該導電基板之一上表面；以及將複數個記憶體模組分別對應於該等導電柱之該第一端，而相互獨立地設置於該導電基板上之不同位置，以使得該等記憶體模組於一縱向投影方向互不重疊，其中，該晶片與該等記憶體模組於該縱向投影方向互不重疊，並且該晶片係嵌埋於該導電基板內部而與該等記憶體模組於一橫向投影方向互不重疊。
  7. 如請求項6所述之半導體封裝結構的製作方法，其中，形成該嵌埋有該晶片及該等導電柱之導電基板的步驟，係包含：將該等導電柱以第二端對應於該等第一焊墊，而設置於該線路增層基板之該第一表面；將該晶片之該第一面對應於該等覆晶焊墊，而設置於該線路增層基板之該第一表面；以及形成一模封層於該線路增層基板之該第一表面上，以覆蓋該等導電柱及該晶片，並暴露出各導電柱之該第一端及該晶片之該第二面。
  8. 如請求項7所述之半導體封裝結構的製作方法，其中各導電柱係以第二端經由一導電黏著層而電性連接於對應的各第一焊墊。
  9. 如請求項7所述之半導體封裝結構的製作方法，其中，設置該等導電柱的步驟，更包含：形成一圖案化光阻層於該線路增層基板之該第一表面，並形成複數盲孔以暴露該等第一焊墊；形成一金屬層於該等盲孔內及暴露之該等第一焊墊上；以及移除該圖案化光阻層，以令該等金屬層形成為該等導電柱及暴露出該等覆晶焊墊。
  10. 如請求項6所述之半導體封裝結構的製作方法，其中，形成嵌埋有該晶片及該等導電柱之導電基板的步驟，係包含：將該晶片之該第一面對應於該等覆晶焊墊，而設置於該線路增層基板之該第一表面；形成一模封層於該線路增層基板之該第一表面上，以覆蓋該晶片；於該模封層對應於該等第一焊墊形成複數個開孔；於該開孔中形成複數個導電柱以電性連接對應的該等第一焊墊；以及使該模封層暴露出該等導電柱之該第一端及該晶片之該第二面。
  11. 如請求項6所述之半導體封裝結構的製作方法，更包含設置一散熱元件於該記憶體模組及/或該晶片之該第二面上。
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