TW201737415A - 封裝基板的製作方法 - Google Patents

封裝基板的製作方法 Download PDF

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Publication number
TW201737415A
TW201737415A TW105111841A TW105111841A TW201737415A TW 201737415 A TW201737415 A TW 201737415A TW 105111841 A TW105111841 A TW 105111841A TW 105111841 A TW105111841 A TW 105111841A TW 201737415 A TW201737415 A TW 201737415A
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Taiwan
Prior art keywords
material layer
dielectric material
conductive line
connecting unit
forming
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TW105111841A
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English (en)
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TWI563602B (en
Inventor
胡竹青
許詩濱
許哲瑋
劉晉銘
楊智貴
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恆勁科技股份有限公司
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Application filed by 恆勁科技股份有限公司 filed Critical 恆勁科技股份有限公司
Priority to TW105111841A priority Critical patent/TWI563602B/zh
Priority to CN201610683394.4A priority patent/CN107301954A/zh
Application granted granted Critical
Publication of TWI563602B publication Critical patent/TWI563602B/zh
Priority to US15/465,775 priority patent/US9831217B2/en
Publication of TW201737415A publication Critical patent/TW201737415A/zh

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本發明揭示一種封裝基板的製作方法，其包含：提供一第一承載板；形成一第一導電線路與一第一連接單元於該第一承載板上；形成一第一介電材料層於該第一承載板上，使得該第一介電材料層圍繞該第一導電線路與該第一連接單元，並露出該第一連接單元的一端面；黏接一第二承載板於該第一介電材料層，並移除該第一承載板；設置一第一電路晶片並形成一第二連接單元於該第一導電線路上；形成一第二介電材料層於該第二承載板上，使得該第二介電材料層圍繞該第一電路晶片與該第二連接單元，並露出該第二連接單元的一端面；形成一第二導電線路於該第二介電材料層上；設置一第二電路晶片於該第二導電線路上；形成一第三介電材料層於該第二承載板上；以及移除該第二承載板。

Description

封裝基板的製作方法
本發明係關於一種封裝基板的製作方法，特別是以「面板等級封裝製程(Panel-level processing)」或「晶圓等級封裝製程(Wafer-level processing)」在一大片的原始基板(original substrate)以及承載板(carrier substrate)上使得相同的製程同時製作眾多的封裝基板之方法。
新一代電子產品不僅追求輕薄短小的高密度，更有朝向高功率發展的趨勢；因此，積體電路(Integrated Circuit，簡稱IC)技術及其後端的晶片封裝技術亦隨之進展，以符合此新一代電子產品的效能規格。電路晶片埋入封裝基板的內埋元件技術，因為具有降低封裝基板產品受到雜訊干擾及產品尺寸減小的優點，近年來已成為本領域製造商的研發重點。然而，此類內埋元件封裝基板仍有製作成本偏高的缺點；因此，有必要發展新的封裝基板技術，以降低其製作成本。
為達成此目的，本發明提供一種封裝基板之製作方法，包含：(A)提供一第一承載板；(B)形成一第一導電線路與一第一連接單元於該第一承載板上；(C)形成一第一介電材料層於該第一承載板上，使得該第一介電材料層圍繞該第一導電線路與該第一連接單元，並露出該第一連接單元的一端面；(D)黏接一第二承載板於該第一介電材料層，並移除該第一承載板；(E)設置一第一電路晶片並形成一第二連接單元於該第一導電線路上；(F)形成一第二介電 材料層於該第二承載板上，使得該第二介電材料層圍繞該第一電路晶片與該第二連接單元，並露出該第二連接單元的一端面；(G)形成一第二導電線路於該第二介電材料層上；(H)設置一第二電路晶片於該第二導電線路上；(I)形成一第三介電材料層於該第二承載板上；以及(J)移除該第二承載板。
在一實施例中，步驟(B)包含：形成該第一導電線路於該第一承載板上；以及形成該第一連接單元於該第一導電線路上。
在一實施例中，步驟(C)包含：形成該第一介電材料層於該第一承載板上，使得該第一介電材料層覆蓋該第一導電線路與該第一連接單元；以及部分移除該第一介電材料層，使得該第一連接單元的該端面被露出。
在一實施例中，步驟(E)係：先設置該第一電路晶片於該第一導電線路上，再形成該第二連接單元於該第一導電線路上。
在一實施例中，步驟(E)係：先形成該第二連接單元於該第一導電線路上，再設置該第一電路晶片於該第一導電線路上。
在一實施例中，該第一電路晶片與該第二連接單元上下不重疊。
在一實施例中，該第二連接單元係為以電鍍方式形成的金屬柱狀物。
在一實施例中，步驟(F)包含：形成該第二介電材料層於該第二承載板上，使得該第二介電材料層覆蓋該第一電路晶片與該第二連接單元；以及部分移除該第二介電材料層，使得該第二連接單元的該端面被露出。
在一實施例中，步驟(G)進一步包含：使該第二導電線路連接該第二連接單元的該端面。
100‧‧‧封裝基板
110‧‧‧第一承載板
111‧‧‧第二承載板
120‧‧‧第一導電線路
122‧‧‧第一次導電線路
123‧‧‧第四介電材料層
124‧‧‧次連接單元
126‧‧‧第二次導電線路
130‧‧‧第一連接單元
131‧‧‧端面
140‧‧‧第一介電材料層
150‧‧‧第一電路晶片
151‧‧‧外接腳墊
156‧‧‧第二連接單元
157‧‧‧端面
160‧‧‧第二介電材料層
170‧‧‧第二導電線路
180‧‧‧第二電路晶片
181‧‧‧外接腳墊
190‧‧‧第三介電材料層
200‧‧‧次面板
300‧‧‧面板
第1圖為根據本發明實施例的封裝基板之剖面示意圖。
第2圖為一片面板上同時安排900個封裝基板的平面示意圖。
第3~9圖分別對應第1圖實施例之封裝基板的各個製程步驟之剖 面示意圖。
為使對本發明之特徵、目的及功能有更進一步的認知與瞭解，茲配合圖式詳細說明本發明的實施例如後。在所有的說明書及圖示中，將採用相同的元件編號以指定相同或類似的元件。
在各個實施例的說明中，當一元素被描述是在另一元素之「上方/上」或「下方/下」，係指直接地或間接地在該另一元素之上或之下的情況，其可能包含設置於其間的其他元素；所謂的「直接地」係指其間並未設置其他中介元素。「上方/上」或「下方/下」等的描述係以圖式為基準進行說明，但亦包含其他可能的方向轉變。所謂的「第一」、「第二」、及「第三」係用以描述不同的元素，這些元素並不因為此類謂辭而受到限制。為了說明上的便利和明確，圖式中各元素的厚度或尺寸，係以誇張或省略或概略的方式表示，且各元素的尺寸並未完全為其實際的尺寸。
第1圖為根據本發明實施例的封裝基板100之剖面示意圖。該封裝基板100包含：一第一導電線路120、一第一連接單元130、一第一介電材料層140、一第一電路晶片150、一第二連接單元156、一第二介電材料層160、一第二導電線路170、一第二電路晶片180、以及一第三介電材料層190。該封裝基板100的結構屬於該技術領域所稱的「封裝上封裝(Package on Package，簡稱PoP)」基板，也就是具有多個封裝單元且其形成多層堆疊結構的封裝基板。如第1圖所示，該第一導電線路120、該第一電路晶片150、及該第二介電材料層160的組合可視為第一封裝單元，該第二導電線路170、該第二電路晶片180、及該第三介電材料層190的組合可視為第二封裝單元，其堆疊於該第一封裝單元上；因此，該封裝基板100具有「封裝上封裝(PoP)」的基板結構。
該第一導電線路120代表該封裝基板100的主要線路布局，其可以是單層或多層的結構。在本實施例中，該第一導電線路120具有多層的線路結構，其包含：形成於一第四介電材料層123內 的一第一次導電線路122、一次連接單元124、及一第二次導電線路126，如第1圖所示。該第一次導電線路122代表該第一導電線路120的上層線路布局，該第二次導電線路126代表該第一導電線路120的下層線路布局，並藉由該次連接單元124連接該第一次導電線路122與該第二次導電線路126。該第一次導電線路122及該第二次導電線路126可藉由金屬的電鍍(Electrolytic Plating)或蒸鍍(Evaporation)技術來製作，例如，銅、鋁、或鎳，而其線路的圖案可藉由光微影蝕刻(Photolithography)技術來製作。該次連接單元124可以是金屬材質的柱狀物，例如，銅柱，其穿過該第四介電材料層123以連接該第一次導電線路122(該第一導電線路120的上層線路)與該第二次導電線路126(該第一導電線路120的下層線路)。
如上所述，該第一導電線路120、該第一電路晶片150、及該第二介電材料層160的組合為第一封裝單元，該第二導電線路170、該第二電路晶片180、及該第三介電材料層190的組合為第二封裝單元。其中，該第一電路晶片150及該第二電路晶片180可以是主動或被動元件，其係以積體電路製程技術施加於半導體晶圓(wafer)，並加以切割成晶粒(die)及接上外接腳墊(例如，導電接腳(pin)、導電墊片(pad)或導電凸塊(bump))151及181；該第一電路晶片150的外接腳墊151用以連接該第一導電線路120，該第二電路晶片180的外接腳墊181用以連接該第二導電線路170。在本實施例中，該第一電路晶片150為特殊應用積體電路(Application-Specific Integrated Circuit，簡稱ASIC)，例如，微處理器，而該第二電路晶片180為記憶體。此外，該第一封裝單元可進一步包含該第二連接單元156，其可以是金屬材質的柱狀物，例如，銅柱，穿過該第二介電材料層160以連接該第一導電線路120與該第二導電線路170；或是說，該第二連接單元156用以電性連接該第一封裝單元與該第二封裝單元。該第二導電線路170代表該第二封裝單元的線路布局，其可以是單層或多層的結構；在本實施例中，其係為單層的線路。該第二導電線路170亦可藉由金 屬的電鍍或蒸鍍技術來製作，例如，銅、鋁、或鎳，而其線路的圖案可藉由光微影蝕刻技術來製作。
該第一連接單元130位於該封裝基板100的最下側，如第1圖所示，其用以將該封裝基板100連接至一外部電路。例如，藉由在該第一連接單元130下方製作錫球(Solder ball)，則可將該封裝基板100焊接至一印刷電路板上。該第一連接單元130可以是金屬材質的柱狀物，例如，銅柱，其穿過該第一介電材料層140以將該第一導電線路120連接至外部電路。
上述的該第一介電材料層140、該第二介電材料層160、該第三介電材料層190、及該第四介電材料層123可藉由封裝膠體的鑄模技術來製作，例如，壓縮鑄模法(Compression molding)，而封裝膠體的組成材質可以是酚醛基樹脂(Novolac-based resin)、環氧基樹脂(Epoxy-based resin)、或矽基樹脂(Silicone-based resin)等絕緣材料；但不以此為限，例如，該第二介電材料層160及該第三介電材料層190亦可以是毛細作用(capillarity)較佳但成本較高的底部填充劑(Underfill)，藉以使該第一電路晶片150的外接腳墊151之間以及該第二電路晶片180的外接腳墊181之間得到較佳的填充效果。該第二介電材料層160會包覆該第一電路晶片150，並充填該第一封裝單元中該第一電路晶片150與該第二連接單元156以外的空間，使得該第一封裝單元具有穩固的結構。該第三介電材料層190會包覆該第二電路晶片180，並充填該第二封裝單元中該第二電路晶片180以外的空間，使得該第二封裝單元具有穩固的結構。該第一介電材料層140、該第二介電材料層160、該第三介電材料層190、及該第四介電材料層123可以選用相同的材料或是不同的材料，本發明對此不加以限制。此外，該第三介電材料層190之超出該第二電路晶片180上表面的部分亦可作為該封裝基板100的外側保護層，用以保護該封裝基板100免於受到來自外部環境或後續製程(例如，焊接)的可能傷害。
以下將說明上述封裝基板100的製作方法及程序。請先留意，在本實施例中，該封裝基板100的製作係建構於所謂的「面板等 級封裝製程」或「晶圓等級封裝製程」；也就是說，眾多的封裝基板100以類似矩陣方式排列於一大片的原始基板以及承載板上，使得相同的製程可同時製作該等眾多的封裝基板100，直到整個製作程序完成後，再以切割方式分成各自獨立且如第1圖所示的封裝基板100。由於該等封裝基板100的製作程序都是在同一片面板等級或晶圓等級的基板上進行，因此稱之為「面板等級」或「晶圓等級」的封裝製程。例如，第2圖為一片面板300上同時安排900個封裝基板100的平面示意圖；其中，75個封裝基板100以15×5之矩陣排列而形成一次面板(sub-panel)200，且12個次面板200以2×6之矩陣而排列於整個面板300上。
請參照第3~9圖及第1圖，其分別對應上述實施例之封裝基板100的各個製程步驟之剖面示意圖。
首先，提供一第一承載板110，其為一導電材質且面板或晶圓等級尺寸的基板，例如，金屬基板或是表面鍍有導電層的介電材質基板，用以承載或支持該封裝基板100的整個製程，包含以下即將描述的各個製程步驟。上述的金屬基板包含鐵(Fe)、銅(Cu)、鎳(Ni)、錫(Sn)、鋁(Al)、鎳/金(Ni/Au)及其組合或合金，但本發明不以此為限。
接著，如第3圖所示，形成一第一導電線路120於該第一承載板110上，再形成一第一連接單元130於該第一導電線路120上。該第一導電線路120包含至少一金屬走線，其可以是單層或多層的結構，代表該封裝基板100的主要線路布局。以第3圖為例，該第一導電線路120為多層線路結構，其包含：形成於該第一承載板110上的第一次導電線路122、形成於該第一次導電線路122上的次連接單元124、及形成於該次連接單元124上的第二次導電線路126；在該第一導電線路120所在的層中，一第四介電材料層123將佔滿或充填該次導電線路122及216與該次連接單元124以外的空間。該第一次導電線路122代表該第一導電線路120的上層線路布局，該第二次導電線路126代表該第一導電線路120的下層線路布局，並藉由該次連接單元124連接該第一次導電線 路122與該第二次導電線路126。該第一次導電線路122及該第二次導電線路126可藉由金屬的電鍍或蒸鍍技術來製作，例如，銅、鎳、錫及鎳/金之組合或合金，而其線路的圖案可藉由光微影蝕刻技術來製作。該次連接單元124可以是金屬材質的柱狀物，例如，銅柱，其穿過該第四介電材料層123以連接該第一次導電線路122(該第一導電線路120的上層線路)與該第二次導電線路126(該第一導電線路120的下層線路)。例如，我們可使用感光型的光阻材料，先在該第一承載板110上形成一光阻薄膜，再藉由光微影蝕刻技術進行圖案化，形成金屬電鍍的阻鍍層，再電鍍金屬膜於其上，而形成金屬走線的圖案於該第一承載板110上。或者是，我們可使用非感光型的介電材料，先在該第一承載板110上形成一介電薄膜，再藉由雷射轉印技術對該介電薄膜進行圖案化，再蒸鍍或濺鍍金屬膜於其上，最後以舉離法(Lift-off)移除該介電薄膜，同時將金屬走線的圖案留在該第一承載板110上該第四介電材料層123可藉由封裝膠體的鑄模技術來製作，例如，壓縮鑄模法，而封裝膠體的組成材質可以是酚醛基樹脂、環氧基樹脂、或矽基樹脂等絕緣材料。
接著，如第4圖所示，形成一第一介電材料層140於該第一承載板110上，使得該第一介電材料層140圍繞該第一導電線路120與該第一連接單元130，並露出該第一連接單元130的一端面131。該第一介電材料層140可藉由封裝膠體的鑄模技術來製作，例如，壓縮鑄模法，而封裝膠體的組成材質可以是酚醛基樹脂、環氧基樹脂、或矽基樹脂等絕緣材料，但不以此為限。該第一介電材料層140會覆蓋該第一連接單元130與該第一導電線路120，而在該第一介電材料層140硬化後，該第一連接單元130將得以形成穩固的結構。接著，移除該第一介電材料層140超出該第一連接單元130的部分，例如，採用研磨方式，自上而下移除該第一介電材料層140的上半部，而以該第一連接單元130的端面131為研磨停止點，使得該第一連接單元130的該端面131被露出。
接著將進行承載板的轉換。如第5圖所示，將該第一承載板 110上下翻轉，黏接於一第二承載板111上，使得該第一連接單元130的該端面131與該第二承載板111彼此面對面密合，再將該第一承載板110移除；至此，該第一導電線路120被翻轉為在該第二承載板111的最上層，且該封裝基板100將由該第二承載板111接手承載或支持其後續製程。該第二承載板111亦為一導電材質且面板或晶圓等級尺寸的基板，例如，金屬基板或是表面鍍有導電層的介電材質基板，其中的金屬材質包含鐵、銅、鎳、錫、鋁、鎳/金及其組合或合金，但本發明不以此為限。
接著，設置一第一電路晶片150並形成一第二連接單元156於該第一導電線路120上，如第6圖所示。在本步驟中，可以先設置該第一電路晶片150於該第一導電線路120上，再形成該第二連接單元156於該第一導電線路120上，亦可以先形成該第二連接單元156於該第一導電線路120上，再設置該第一電路晶片150於該第一導電線路120上，端視實際製程的需要而定。其中，該第一電路晶片150與該等第二連接單元156係並排於該第一導電線路120上，亦即該第一電路晶片150與該第二連接單元156在垂直方向上並不重疊。該第一電路晶片150可以是主動或被動元件，其係以積體電路製程技術施加於半導體晶圓，並加以切割成晶粒及接上外接腳墊(例如，導電接腳、導電墊片或導電凸塊)151；例如，第6圖的該第一電路晶片150具有八個外接腳墊151，藉以分別電性連接該第一導電線路120的金屬走線。在本實施例中，該第一電路晶片150為特殊應用積體電路(ASIC)之微處理器。此外，該第二連接單元156可以是金屬材質的柱狀物，例如，銅柱，其可藉由金屬的電鍍或蒸鍍技術來製作，例如，銅、鎳、錫及鎳/金之組合或合金，而其柱狀物的圖案可藉由光微影蝕刻技術來製作。
接著，如第7圖所示，形成一第二介電材料層160於該第二承載板111上，使得該第二介電材料層160圍繞該第一電路晶片150與該第二連接單元156，並露出該第二連接單元156的端面157。該第二介電材料層160可藉由封裝膠體的鑄模技術來製作，例如，壓縮鑄模法，而封裝膠體的組成材質可以是酚醛基樹脂、 環氧基樹脂、或矽基樹脂等絕緣材料；但不以此為限，其亦可以是毛細作用較佳但成本較高的底部填充劑(Underfill)。該第二介電材料層160會覆蓋該第一電路晶片150與該第二連接單元156，並充填該第一電路晶片150下方的外接腳墊151之間的空間，而在該第二介電材料層160硬化後，該第一電路晶片150與該第二連接單元156將得以形成穩固結構的如上所述之第一封裝單元。接著，移除該第二介電材料層160超出該第二連接單元156的部分，例如，採用研磨方式，自上而下移除該第二介電材料層160的上半部，而以該第二連接單元156的端面157為研磨停止點，使得該第二連接單元156的該端面157被露出。
接著將進行第二封裝單元的製作。先形成一第二導電線路170於該第二介電材料層160上，使得該第二導電線路170連接該第二連接單元156的該端面157，如第8圖所示。該第二導電線路170代表該第二封裝單元的線路布局，其可以是單層或多層的結構；在本實施例中，其係為包含至少一金屬走線的單層線路。該第二導電線路170亦可藉由金屬的電鍍或蒸鍍技術來製作，例如，銅、鋁、或鎳，而其線路的圖案可藉由光微影蝕刻技術來製作。
接著，設置一第二電路晶片180於該第二導電線路170上，如第9圖所示。該第二電路晶片180可以是主動或被動元件，其係以積體電路製程技術施加於半導體晶圓，並加以切割成晶粒及接上外接腳墊(例如，導電接腳、導電墊片或導電凸塊)181；例如，第9圖的該第二電路晶片180具有八個外接腳墊181，藉以分別電性連接該第二導電線路170的金屬走線。在本實施例中，該第一電路晶片150為記憶體晶粒。
接著仍如第9圖所示，形成一第三介電材料層190於該第二承載板111上，使得該第三介電材料層190圍繞該第二電路晶片180。該第三介電材料層190可藉由封裝膠體的鑄模技術來製作，例如，壓縮鑄模法，而封裝膠體的組成材質可以是酚醛基樹脂、環氧基樹脂、或矽基樹脂等絕緣材料；但不以此為限，其亦可以是毛細作用較佳但成本較高的底部填充劑。該第三介電材料層190 會覆蓋該第二電路晶片180，並充填該第二電路晶片180下方的外接腳墊181之間的空間，而在該第三介電材料層190硬化後，該第二電路晶片180將得以形成穩固結構的如上所述之第二封裝單元。此外，該第三介電材料層190之超出該第二電路晶片180上表面的部分亦可作為該封裝基板100的外側保護層，用以保護該封裝基板100免於受到來自外部環境或後續製程(例如，焊接)的可能傷害。
最後，將該第二承載板111移除，即可完成如第1圖所示的封裝基板100。且如上所述，眾多的該封裝基板100都是在同一片承載基板上進行「面板等級」或「晶圓等級」的封裝製程，因此…。
唯以上所述者，僅為本發明之較佳實施例，當不能以之限制本發明的範圍。即大凡依本發明申請專利範圍所做之均等變化及修飾，仍將不失本發明之要義所在，亦不脫離本發明之精神和範圍，故都應視為本發明的進一步實施狀況。
100‧‧‧封裝基板
120‧‧‧第一導電線路
122‧‧‧第一次導電線路
123‧‧‧第四介電材料層
124‧‧‧次連接單元
126‧‧‧第二次導電線路
130‧‧‧第一連接單元
131‧‧‧端面
140‧‧‧第一介電材料層
150‧‧‧第一電路晶片
151‧‧‧外接腳墊
156‧‧‧第二連接單元
157‧‧‧端面
160‧‧‧第二介電材料層
170‧‧‧第二導電線路
180‧‧‧第二電路晶片
181‧‧‧外接腳墊
190‧‧‧第三介電材料層

Claims (10)

  1. 一種封裝基板的製作方法，其步驟包含：(A)提供一第一承載板；(B)形成一第一導電線路與一第一連接單元於該第一承載板上；(C)形成一第一介電材料層於該第一承載板上，使得該第一介電材料層圍繞該第一導電線路與該第一連接單元，並露出該第一連接單元的一端面；(D)黏接一第二承載板於該第一介電材料層，並移除該第一承載板；(E)設置一第一電路晶片並形成一第二連接單元於該第一導電線路上；(F)形成一第二介電材料層於該第二承載板上，使得該第二介電材料層圍繞該第一電路晶片與該第二連接單元，並露出該第二連接單元的一端面；(G)形成一第二導電線路於該第二介電材料層上；(H)設置一第二電路晶片於該第二導電線路上；(I)形成一第三介電材料層於該第二承載板上；以及(J)移除該第二承載板。
  2. 如申請專利範圍第1項所述的製作方法，其中的步驟(B)包含：(B11)形成該第一導電線路於該第一承載板上；以及(B12)形成該第一連接單元於該第一導電線路上。
  3. 如申請專利範圍第1項所述的製作方法，其中的步驟(C)包含：(C11)形成該第一介電材料層於該第一承載板上，使得該第一介電材料層覆蓋該第一導電線路與該第一連接單元；以及(C12)部分移除該第一介電材料層，使得該第一連接單元的該端面被露出。
  4. 如申請專利範圍第1項所述的製作方法，其中的步驟(E)係：先設置該第一電路晶片於該第一導電線路上，再形成該第二連接單元於該第一導電線路上。
  5. 如申請專利範圍第1項所述的製作方法，其中的步驟(E)係：先 形成該第二連接單元於該第一導電線路上，再設置該第一電路晶片於該第一導電線路上。
  6. 如申請專利範圍第1項所述的製作方法，其中的步驟(E)進一步包含：使該第一電路晶片與該第二連接單元上下不重疊。
  7. 如申請專利範圍第1項所述的製作方法，其中的步驟(E)係以電鍍方式形成該第二連接單元。
  8. 如申請專利範圍第1項所述的製作方法，其該第二連接單元係為一金屬柱狀物。
  9. 如申請專利範圍第1項所述的製作方法，其中的步驟(F)包含：(F11)形成該第二介電材料層於該第二承載板上，使得該第二介電材料層覆蓋該第一電路晶片與該第二連接單元；以及(F12)部分移除該第二介電材料層，使得該第二連接單元的該端面被露出。
  10. 如申請專利範圍第1項所述的製作方法，其中的步驟(G)進一步包含：使該第二導電線路連接該第二連接單元的該端面。
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TWI770854B (zh) * 2020-03-27 2022-07-11 南亞科技股份有限公司 雙晶粒半導體封裝結構及其製備方法
US11469216B2 (en) 2020-03-27 2022-10-11 Nanya Technology Corporation Dual-die semiconductor package and manufacturing method thereof

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