TWI563602B - Method of fabricating a package substrate - Google Patents

Method of fabricating a package substrate

Info

Publication number
TWI563602B
TWI563602B TW105111841A TW105111841A TWI563602B TW I563602 B TWI563602 B TW I563602B TW 105111841 A TW105111841 A TW 105111841A TW 105111841 A TW105111841 A TW 105111841A TW I563602 B TWI563602 B TW I563602B
Authority
TW
Taiwan
Prior art keywords
fabricating
package substrate
package
substrate
Prior art date
Application number
TW105111841A
Other languages
English (en)
Other versions
TW201737415A (zh
Inventor
Chu Chin Hu
Shih Ping Hsu
Che Wei Hsu
Chin Ming Liu
Chih Kuai Yang
Original Assignee
Phoenix Pioneer Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Pioneer Technology Co Ltd filed Critical Phoenix Pioneer Technology Co Ltd
Priority to TW105111841A priority Critical patent/TWI563602B/zh
Priority to CN201610683394.4A priority patent/CN107301954A/zh
Application granted granted Critical
Publication of TWI563602B publication Critical patent/TWI563602B/zh
Priority to US15/465,775 priority patent/US9831217B2/en
Publication of TW201737415A publication Critical patent/TW201737415A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828Etching
    • H01L21/4832Etching a temporary substrate after encapsulation process to form leads
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857Multilayer substrates
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
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    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L2224/08225Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/08238Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bonding area connecting to a bonding area protruding from the surface of the item
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Combinations Of Printed Boards (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW105111841A 2016-04-15 2016-04-15 Method of fabricating a package substrate TWI563602B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW105111841A TWI563602B (en) 2016-04-15 2016-04-15 Method of fabricating a package substrate
CN201610683394.4A CN107301954A (zh) 2016-04-15 2016-08-18 封装基板的制作方法
US15/465,775 US9831217B2 (en) 2016-04-15 2017-03-22 Method of fabricating package substrates

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW105111841A TWI563602B (en) 2016-04-15 2016-04-15 Method of fabricating a package substrate

Publications (2)

Publication Number Publication Date
TWI563602B true TWI563602B (en) 2016-12-21
TW201737415A TW201737415A (zh) 2017-10-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW105111841A TWI563602B (en) 2016-04-15 2016-04-15 Method of fabricating a package substrate

Country Status (3)

Country Link
US (1) US9831217B2 (zh)
CN (1) CN107301954A (zh)
TW (1) TWI563602B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10157887B2 (en) 2017-03-09 2018-12-18 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
CN110634832A (zh) * 2019-08-29 2019-12-31 上海先方半导体有限公司 一种基于硅通孔转接板的封装结构及其制作方法
US11469216B2 (en) * 2020-03-27 2022-10-11 Nanya Technology Corporation Dual-die semiconductor package and manufacturing method thereof

Citations (5)

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