TW201725668A - 封裝基板及其製作方法 - Google Patents

封裝基板及其製作方法 Download PDF

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Publication number
TW201725668A
TW201725668A TW105100173A TW105100173A TW201725668A TW 201725668 A TW201725668 A TW 201725668A TW 105100173 A TW105100173 A TW 105100173A TW 105100173 A TW105100173 A TW 105100173A TW 201725668 A TW201725668 A TW 201725668A
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Taiwan
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layer
package substrate
connection unit
conductive connection
conductive
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TW105100173A
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胡竹青
許詩濱
劉晉銘
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恆勁科技股份有限公司
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Priority to TW105100173A priority Critical patent/TW201725668A/zh
Priority to US15/392,246 priority patent/US20170194262A1/en
Publication of TW201725668A publication Critical patent/TW201725668A/zh
Priority to US15/654,903 priority patent/US20170317031A1/en

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Abstract

本發明揭示一種封裝基板及其製作方法。該封裝基板包括：一導線層，包含至少一金屬走線；一導電連接單元，位於該導線層上；一電路晶片，具有至少一外接腳墊，並設置於該導電連接單元上；以及一鑄模化合物層，包覆該導線層、該導電連接單元及該電路晶片；其中，該導電連接單元用以連接該至少一外接腳墊的其中一者與該至少一金屬走線的其中一者。

Description

封裝基板及其製作方法
本發明係關於一種封裝基板以及其製作方法。
新一代電子產品不僅追求輕薄短小的高密度，更有朝向高功率發展的趨勢；因此，積體電路(Integrated Circuit，簡稱IC)技術及其後端的晶片封裝技術亦隨之進展，以符合此新一代電子產品的效能規格。電路晶片埋入封裝基板的內埋元件技術，因為具有降低封裝基板產品受到雜訊干擾及產品尺寸減小的優點，近年來已成為本領域製造商的研發重點。習知技術通常是先將電路晶片或晶粒埋入作為封裝基板主體的鑄模化合物中，再來製做作為封裝基板電路布局的導線層。
然而，導線層大多為寬度較窄的細線路，製程難度高，使得當導線層發生製做上的缺陷時，該電路晶片或晶粒也必須連帶報廢。此外，一旦電路晶片或晶粒被埋入封裝基板中，該電路晶片或晶粒與外部電路的電性連接線路將會變得難以處理，例如，額外的雷射開孔、介電材料層壓合等加工製程及複雜結構的電性連接線路，這些都會提高製造成本及降低產品良率。因此，有必要發展新的封裝基板技術，以對治及改善上述的問題。
為達成此目的，本發明提供一種封裝基板，其包含：一導線層，包含至少一金屬走線；一導電連接單元，位於該導線層上；一電路晶片，具有至少一外接腳墊，並設置於該導電連接單元上；以及一鑄模化合物層，包覆該導線層、該導電連接單元及該電路晶片；其中，該導電連接單元用以連接該至少一外接腳墊的其中 一者與該至少一金屬走線的其中一者。
在一實施例中，該導電連接單元為一金屬柱狀物。
在一實施例中，該導電連接單元為一焊錫凸塊物。
在一實施例中，該封裝基板更包含一散熱片，其設置於該電路晶片上，並連接該電路晶片。
在一實施例中，該封裝基板更包含一金屬承載板，其設置於該導線層下。
另一方面，本發明提供一種封裝基板之製作方法，其步驟包含：提供一承載板；形成一第一導線層於該承載板上，使得該第一導線層包含至少一第一金屬走線；形成一導電連接單元於該第一導線層上；設置一具有至少一外接腳墊的電路晶片於該導電連接單元上，使得該導電連接單元連接該至少一外接腳墊的其中一者與該至少一第一金屬走線的其中一者；以及形成一鑄模化合物層於該電路晶片上，並使得該鑄模化合物層充填該電路晶片與該承載板之間的空間。
在一實施例中，該導電連接單元為一第一金屬柱狀物。
在一實施例中，該導電連接單元為一焊錫凸塊物。
在一實施例中，該方法更包含：移除部分的該鑄模化合物層，以露出該電路晶片的上表面；以及移除該承載板。
在一實施例中，該方法更包含：設置一散熱片於該電路晶片上，使得該散熱片連接該電路晶片的上表面。
在一實施例中，該方法更包含：形成一第二導線層於該鑄模化合物層上，使得該第二導線層包含至少一第二金屬走線；形成一導電柱層於該第二導線層上，該導電柱層包含至少一第二金屬柱狀物；以及形成一介電材料層於該鑄模化合物層上，並使得該介電材料層包覆該鑄模化合物層上所有的該至少一第二金屬走線與該至少一第二金屬柱狀物。
100、200、300‧‧‧封裝基板
110‧‧‧承載板
120‧‧‧第一導線層
121~125‧‧‧第一金屬走線
130、131~134‧‧‧導電連接單元
140‧‧‧電路晶片
141~144‧‧‧外接腳墊
150‧‧‧鑄模化合物層
160‧‧‧散熱片
170‧‧‧第二導線層
171~174‧‧‧第二金屬走線
180‧‧‧導電柱層
181~184‧‧‧金屬柱狀物
190‧‧‧介電材料層
第1圖為根據本發明第一實施例封裝基板之剖面示意圖。
第2~6圖為本發明第一實施例封裝基板的各個製程步驟之剖面圖。
第7A及7B圖為根據本發明第二實施例的封裝基板之剖面示意圖。
第8~10圖為根據本發明第三實施例封裝基板的各個製程步驟之剖面圖。
為使對本發明之特徵、目的及功能有更進一步的認知與瞭解，茲配合圖式詳細說明本發明的實施例如後。在所有的說明書及圖示中，將採用相同的元件編號以指定相同或類似的元件。
在各個實施例的說明中，當一元素被描述是在另一元素之「上方/上」或「下方/下」，係指直接地或間接地在該另一元素之上或之下的情況，其可能包含設置於其間的其他元素；接地」係指其間並未設置其他中介元素。「上方/上」或「下方/下」等的描述係以圖式為基準進行說明，但亦包含其他可能的方向轉變。所謂的「第一」、「第二」、及「第三」係用以描述不同的元素，這些元素並不因為此類謂辭而受到限制。為了說明上的便利和明確，圖式中各元素的厚度或尺寸，係以誇張或省略或概略的方式表示，且各元素的尺寸並未完全為其實際的尺寸。
第1圖為根據本發明第一實施例的封裝基板100之剖面示意圖。該封裝基板100包含：一第一導線層120、一導電連接單元130、一電路晶片140以及一鑄模化合物層150。該第一導線層120代表該封裝基板100的線路布局，其包含至少一第一金屬走線；該導電連接單元130形成於該第一導線層120上，其數量可以是一個以上；該電路晶片140設置於該導電連接單元130上，且該電路晶片140具有至少一外接腳墊；為了說明上的方便，如第1圖所示的例子，該第一導線層120具有五個第一金屬走線(由左至右編號為121~125)、該導電連接單元130的數量為四個(由左至右編號為131~134)、該電路晶片140具有四個外接腳墊(由左至 右編號為141~144)，但其數量並不以此為限，端視該封裝基板100線路布局的需要而定。各個導電連接單元131~134用以連接該等外接腳墊141~144的其中一者與該等第一金屬走線121~125的其中一者；例如，該導電連接單元131連接該外接腳墊141與該第一金屬走線121，該導電連接單元132連接該外接腳墊142與該第一金屬走線122，該導電連接單元133連接該外接腳墊143與該第一金屬走線123，該導電連接單元134連接該外接腳墊144與該第一金屬走線124。此外，該鑄模化合物層150則包覆該第一導線層120、該導電連接單元130及該電路晶片140，其超出該電路晶片140上表面的部分可作為該封裝基板100最外側的保護層。
該第一導線層120的組成材質可以是銅(Cu)、鎳(Ni)、錫(Sn)及鎳/金(Ni/Au)之組合或合金，其可在電鍍(Electrolytic plating)、濺鍍(Sputtering coating)或蒸鍍(Evaporation)形成金屬膜之後，藉由微影蝕刻(Photolithography)的圖案化製程來製作，作為該封裝基板100的電路布局線路層之其中一層。在本實施例中，該第一導線層120具有五個第一金屬走線121~125，如第1圖所示。
該電路晶片140為一主動元件。在本實施例中，該電路晶片140的製作可以是以積體電路(IC)製程施加於半導體晶圓(wafer)，並加以切割成晶粒(die)，並已預先接上外接腳墊(例如，導電接腳(pin)、導電墊片(pad)或導電凸塊(bump))，而將應用內埋元件技術而埋入該封裝基板100中。藉此，可有效減低封裝基板產品所受到的雜訊干擾及縮小其成品尺寸，而可應用於可攜式裝置的應用處理器(Application processor)及電源管理晶片。如第1圖所示，該電路晶片140具有四個外接腳墊141~144，當其設置於該導電連接單元130上時，能自我對位(Self-alignment)地將該等外接腳墊141~144分別連接該等導電連接單元131~134，而不須使用精密對準技術。
為了讓該電路晶片140能在不使用精密對準技術的情況下連接至該第一導線層120，本實施例在該第一導線層120層上製作有柱狀結構或凸塊結構的導電連接單元131~134，例如，銅柱(Cu pillar)或焊錫凸塊(solder bump)，使得該電路晶片140的外接腳墊141~144能簡易地自我對位至該等導電連接單元131~134，則將可有效降低封裝基板的製作成本。在本實施例中，單一個導電連接單元130(或，該等導電連接單元131~134)用以連接該等外接腳墊141~144的其中一者與該等第一金屬走線121~125的其中一者。如第1圖所示，該導電連接單元131連接該外接腳墊141與該第一金屬走線121，該導電連接單元132連接該外接腳墊142與該第一金屬走線122，該導電連接單元133連接該外接腳墊143與該第一金屬走線123，該導電連接單元134連接該外接腳墊144與該第一金屬走線124，使得該電路晶片140可依據該封裝基板100的電路設計而連接至該第一導線層120。
該鑄模化合物層150可藉由封裝膠體的鑄模技術來製作，例如，壓縮鑄模法(Compression Molding)，而封裝膠體的組成材質可以是酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)、或矽基樹脂(Silicone-Based Resin)等絕緣材料，但不以此為限。該鑄模化合物層150會包覆該電路晶片140，並充填該電路晶片140與該第一導線層120之間的空間，使得該封裝基板100形成具穩固結構的電子元件或產品。此外，該鑄模化合物層150之超出該電路晶片140上表面的部分亦可作為該封裝基板100的外側保護層，用以保護該封裝基板100免於受到來自外部環境或後續製程(例如，焊接)的可能傷害。
在本實施例中，該封裝基板100可作為應用於鑄模互連基板技術的覆晶式晶片尺寸封裝(FCCSP)之基板。此外，本實施例封裝基板的線路布局之單導線亦可以是多層導線層的堆疊結構，例如，二層、三層或更多層的導線層。
以下說明本發明實施例之封裝基板100的製程。請參照第2~6圖及第1圖，其分別對應上述實施例之封裝基板100的各個製程步驟之封裝基板剖面圖。
首先，如第2圖所示，提供一承載板110，其可為一導電材質的基板，例如，金屬基板或是表面鍍有一層導電層的介電材質基 板，用以承載或支持該封裝基板100的後續製程，例如，製作該封裝基板100的導電線路。上述的金屬基板包含鐵(Fe)、銅(Cu)、鎳(Ni)、錫(Sn)、鋁(Al)、鎳/金(Ni/Au)及其組合或合金，但本發明不以此為限。
接著，如第2圖所示，形成一第一導線層120於該承載板110上，使得該第一導線層120包含至少一第一金屬走線。例如，我們可使用感光型的光阻材料，先在該承載板110上形成一光阻薄膜，再藉由微影蝕刻製程進行圖案化，形成金屬電鍍的阻鍍層，再電鍍金屬膜於其上，而形成金屬走線的圖案於該承載板110上。或者是，我們可使用非感光型的介電材料，先在該承載板110上形成一介電薄膜，再藉由雷射轉印技術對該介電薄膜進行圖案化，再蒸鍍或濺鍍金屬膜於其上，最後以舉離法(Lift-off)移除該介電薄膜，同時將金屬走線的圖案留在該承載板110上。在本實施例中，該導線層120具有五個第一金屬走線121~125，且其組成材質可以是銅、鎳、錫及鎳/金之組合或合金。
接著，形成該至少一導電連接單元130於該第一導線層120上。如第4A圖所示，該至少一導電連接單元130包含四個凸塊結構的導電連接單元131~134，例如，焊錫凸塊(Solder bump)，用以在後續製程中將該電路晶片140連接至該第一導線層120。但該至少一導電連接單元130的數量並不以此為限，端視該封裝基板100線路布局的需要或該電路晶片140的外接腳墊數量而定。在另一實施例中，該等導電連接單元131’~134’亦可為柱狀結構，如第4B圖所示，例如，銅柱、鋁柱、鎳柱、錫柱或合金柱，較佳者為銅柱。為避免過多的贅述，本說明書後半部係以該等導電連接單元131~134為凸塊結構(如第4A圖所示)來說明相關的實施例，但讀者應能理解，該些實施例亦同樣適用於該等導電連接單元131’~134’為柱狀結構(如第4B圖所示)的案例。
接著，設置一具有至少一外接腳墊的電路晶片140於該至少一導電連接單元130上(在本實施例中，該電路晶片140具有四個外接腳墊141~144，如第5圖所示，但本發明並不以此為限制)， 使得各個外接腳墊141~144連接該至少一外接腳墊141~144的其中一者與該至少一第一金屬走線121~125的其中一者。該電路晶片140係以積體電路(IC)製程所製成的主動元件，而為切割成晶粒(die)形式的晶片，並已預先接上外接腳墊(例如，導電接腳、導電墊片或導電凸塊)，可應用內埋元件技術而埋入該封裝基板100中。當該電路晶片140安裝於該導電連接單元130上時，該等外接腳墊141~144可以輕易地被放置於該等導電連接單元131~134，例如，自我對位(self-alignment)，而不須使用精密對準技術。在本實施例中，該導電連接單元131連接該外接腳墊141與該第一金屬走線121，該導電連接單元132連接該外接腳墊142與該第一金屬走線122，該導電連接單元133連接該外接腳墊143與該第一金屬走線123，該導電連接單元134連接該外接腳墊144與該第一金屬走線124，使得該電路晶片140可依據該封裝基板100的電路設計而連接至該第一導線層120。
接著，如第6圖所示，形成一鑄模化合物層150於該電路晶片140上，並使得該鑄模化合物層150充填該電路晶片140與該承載板110之間的空間。該鑄模化合物層150可藉由封裝膠體的鑄模技術來製作，例如，壓縮鑄模法，而封裝膠體的組成材質可以是酚醛(Novolac)基樹脂、環氧基樹脂、或矽基樹脂等絕緣材料，但不以此為限。該鑄模化合物層150會包覆該電路晶片140，並充填該電路晶片140與該第一導線層120之間的空間，使得該封裝基板100形成具穩固結構的電子元件或產品。此外，該鑄模化合物層150之超出該電路晶片140上表面的部分亦可作為該封裝基板100的外側保護層，用以保護該封裝基板100免於受到來自外部環境或後續製程(例如，焊接)的可能傷害。至此，該封裝基板100的基本電路已完成，可先將該承載板110移除，如第1圖所示。
電路晶片埋入封裝基板的內埋元件技術，因為具有降低封裝基板產品受到雜訊干擾及產品尺寸減小的優點，近年來已成為本領域製造商的研發重點。以第1圖的封裝基板為例，習知技術通常是先將電路晶片140埋入封裝基板100的主體(鑄模化合物層 150)中，再來製做作為封裝基板電路布局的第一導線層120，而該第一導線層120大多為寬度較窄的細線路，製程難度高，使得當該第一導線層120發生製做上的缺陷，則該電路晶片140也必須連帶報廢。此外，一旦該電路晶片140被埋入該封裝基板100，該電路晶片140與外部電路的電性連接線路將會變得難以處理，例如，額外的雷射開孔、介電材料層壓合等加工製程及複雜結構的電性連接線路，這些都會提高製造成本及降低產品良率。
反觀本發明技術，如上實施例之製程步驟所述，是在將電路晶片140埋入該封裝基板100之前，就先完成作為封裝基板電路布局的第一導線層120，再將該電路晶片140黏接至該第一導線層120，最後再將鑄模化合物層150以鑄模方式注入，而完成如第1圖所示的封裝基板100。藉此，寬度較窄、製程難度較高的細線路(該第一導線層120)先會被製作，而該第一導線層120亦可包含電路晶片140與外部電路的電性連接線路而同時製作完成或不須額外加工；因此，可降低製造成本及提高產品良率。
依據上述實施例，第6圖的封裝基板可被進一步發展成具有更高階功能的產品。例如，第7A圖為根據本發明第二實施例的封裝基板200之剖面示意圖。在上述第一實施例製程進行到第6圖的步驟之後，可自上而下移除該鑄模化合物層150至露出該電路晶片140的上表面；例如，採用研磨方式來移除該鑄模化合物層150的上半部，而以該電路晶片140的上表面為研磨停止點。藉此，由於該電路晶片140的上表面為外露之狀態，這將有利於該電路晶片140的散熱效果。在另一實施例中，一散熱片(Heat sink)160可進一步設置於該電路晶片140上，使得該散熱片160連接該電路晶片140，以增強對該電路晶片140的散熱效果，如第7B圖所示。例如，採用黏貼方式，將該散熱片160直接黏貼於該電路晶片140的上表面。
此外，由於上述實施例所採用的承載板110為具有導電性的基板，無論其為整塊的金屬基板或是只在表面鍍有導電層的介電基板，該承載板110亦可作為提供該電路晶片140的散熱之用， 而將它保留於第6圖之後的製程。例如，第8~10圖為根據本發明第三實施例的封裝基板300對應後續製程步驟之剖面示意圖。在上述第一實施例進行到第6圖的步驟時，倘若欲將該承載板110作為散熱片，則該第一導線層120可作為將該電路晶片140所產生熱量向該承載板110傳送的散熱路徑。在本實施例中，我們可在該鑄模化合物層150上另行製作封裝基板的電路布局線路層；因此，如第8圖所示，一第二導線層170可形成於該鑄模化合物層150上，使得該第二導線層170包含至少一第二金屬走線；例如，該第二導線層170具有四個第二金屬走線171~174，其製作方式及組成材質可參照如第2圖步驟的第一導線層120，但不以此為限。
接著，如第9圖所示，一導電柱層180可形成於該第二導線層170上，該導電柱層180包含至少一金屬柱狀物；例如，該導電柱層180具有四個金屬柱狀物181~184，其分別對應該等第二金屬走線171~174。
接著，如第10圖所示，形成一介電材料層190於該鑄模化合物層150上，並使得該介電材料層190包覆該鑄模化合物層150上的該等第二金屬走線171~174與該等金屬柱狀物181~184。該介電材料層190的製作方式及組成材質可參照如第6圖步驟的該鑄模化合物層150，但不以此為限
此外，我們可以第1圖的封裝基板100為基礎，因應不同的需求或用途而作進一步的應用。例如，在該封裝基板100的下方製作錫球(Solder ball)以連接外部電路；在該封裝基板100的上方疊加表面黏著技術(Surface-Mount Technology，簡稱SMT)元件或是其他的電路晶片或晶粒；在該封裝基板100的上方或下方疊加其他的封裝基板，形成多層結構的封裝基板。
唯以上所述者，僅為本發明之較佳實施例，當不能以之限制本發明的範圍。即大几依本發明申請專利範圍所做之均等變化及修飾，仍將不失本發明之要義所在，亦不脫離本發明之精神和範圍，故都應視為本發明的進一步實施狀況。
100‧‧‧封裝基板
120‧‧‧第一導線層
121~125‧‧‧第一金屬走線
130、131~134‧‧‧導電連接單元
140‧‧‧電路晶片
141~144‧‧‧外接腳墊
150‧‧‧鑄模化合物層

Claims (11)

  1. 一種封裝基板，其包含：一導線層，包含至少一金屬走線；一導電連接單元，位於該導線層上；一電路晶片，具有至少一外接腳墊，並設置於該導電連接單元上；以及一鑄模化合物層，包覆該導線層、該導電連接單元及該電路晶片；其中，該導電連接單元用以連接該至少一外接腳墊的其中一者與該至少一金屬走線的其中一者。
  2. 如申請專利範圍第1項所述之封裝基板，其中，該導電連接單元為一金屬柱狀物。
  3. 如申請專利範圍第1項所述之封裝基板，其中，該導電連接單元為一焊錫凸塊物。
  4. 如申請專利範圍第1項所述之封裝基板，更包含一散熱片，其設置於該電路晶片上，並連接該電路晶片。
  5. 如申請專利範圍第1項所述之封裝基板，更包含一金屬承載板，其設置於該導線層下。
  6. 一種封裝基板之製作方法，其步驟包含：(A)提供一承載板；(B)形成一第一導線層於該承載板上，使得該第一導線層包含至少一第一金屬走線；(C)形成一導電連接單元於該第一導線層上；(D)設置一具有至少一外接腳墊的電路晶片於該導電連接單元上，使得該導電連接單元連接該至少一外接腳墊的其中一者與該至少一第一金屬走線的其中一者；以及(E)形成一鑄模化合物層於該電路晶片上，並使得該鑄模化合物層充填該電路晶片與該承載板之間的空間。
  7. 如申請專利範圍第6項所述之製作方法，其中，該導電連接單元為一第一金屬柱狀物。
  8. 如申請專利範圍第6項所述之製作方法，其中，該導電連接單元為一焊錫凸塊物。
  9. 如申請專利範圍第6項所述之製作方法，更包含：(F1)移除部分的該鑄模化合物層，以露出該電路晶片的上表面；以及(F2)移除該承載板。
  10. 如申請專利範圍第9項所述之製作方法，更包含：設置一散熱片於該電路晶片上，使得該散熱片連接該電路晶片的上表面。
  11. 如申請專利範圍第6項所述之製作方法，更包含：(H1)形成一第二導線層於該鑄模化合物層上，使得該第二導線層包含至少一第二金屬走線；(H2)形成一導電柱層於該第二導線層上，該導電柱層包含至少一第二金屬柱狀物；以及(H3)形成一介電材料層於該鑄模化合物層上，並使得該介電材料層包覆該鑄模化合物層上所有的該至少一第二金屬走線與該至少一第二金屬柱狀物。
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