TW201806101A - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

Info

Publication number
TW201806101A
TW201806101A TW106113221A TW106113221A TW201806101A TW 201806101 A TW201806101 A TW 201806101A TW 106113221 A TW106113221 A TW 106113221A TW 106113221 A TW106113221 A TW 106113221A TW 201806101 A TW201806101 A TW 201806101A
Authority
TW
Taiwan
Prior art keywords
die
wiring layer
package structure
sealing body
layer
Prior art date
Application number
TW106113221A
Other languages
English (en)
Other versions
TWI644403B (zh
Inventor
張家維
方立志
林國鼎
莊詠程
Original Assignee
力成科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 力成科技股份有限公司 filed Critical 力成科技股份有限公司
Publication of TW201806101A publication Critical patent/TW201806101A/zh
Application granted granted Critical
Publication of TWI644403B publication Critical patent/TWI644403B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本發明提供一種封裝結構及其製造方法。封裝結構包括重佈線路層、至少一第一晶粒、多個導電端子、第一密封體、多個焊球、多個第二晶粒以及第二密封體。重佈線路層具有第一表面以及相對於第一表面的第二表面。第一晶粒以及導電端子與重佈線路層電性連接且位於重佈線路層的第一表面上。第一密封體密封第一晶粒以及導電端子且暴露出導電端子的至少一部分。焊球與導電端子電性連接且位於被第一密封體暴露出的導電端子上。第二晶粒與重佈線路層電性連接且位於重佈線路層的第二表面上。第二密封體密封第二晶粒。

Description

封裝結構及其製造方法
本發明是有關於一種封裝結構及其製造方法，且特別是有關於一種具有在重佈線路層的兩面皆配置有晶粒的封裝結構。
為了使得電子產品能達到輕薄短小的設計，半導體封裝技術亦跟著日益進展，以發展出符合小體積、重量輕、高密度以及在市場上具有高競爭力等要求的產品。舉例來說，為了使得電子產品較薄，通常會希望提供具有較小厚度的高密度封裝結構。因此，如何在封裝結構微型化的同時還能夠維持封裝結構中所密封的晶片數目成為本領域的技術人員的一大挑戰。
本發明提供一種封裝結構及其製造方法，能夠有效地減小其尺寸。
本發明提供一種封裝結構，其包括重佈線路層、至少一第一晶粒、多個導電端子、第一密封體、多個焊球、多個第二晶粒以及第二密封體。重佈線路層具有第一表面以及相對於第一表面的第二表面。第一晶粒以及導電端子與重佈線路層電性連接且位於重佈線路層的第一表面上。第一密封體密封第一晶粒以及導電端子且暴露出導電端子的至少一部分。焊球與導電端子電性連接且位於被第一密封體暴露出的導電端子上。第二晶粒與重佈線路層電性連接且位於重佈線路層的第二表面上。第二密封體密封第二晶粒。
本發明提供一種封裝結構的製造方法，其至少包括以下步驟。在載板上形成重佈線路層。重佈線路層具有第一表面以及相對於第一表面的第二表面，且重佈線路層的第二表面面向載板。在重佈線路層的第一表面上形成多個導電端子以及至少一第一晶粒。藉由第一密封體密封第一晶粒以及導電端子，且第一密封體暴露出導電端子的至少一部分。將重佈線路層的第二表面與載板分離。在重佈線路層的第二表面上形成多個第二晶粒。藉由第二密封體密封第二晶粒。在被第一密封體暴露出的導電端子上形成多個焊球。
本發明提供一種封裝結構的製造方法，其至少包括以下步驟。在載板上形成至少一第一晶粒。藉由第一密封體密封第一晶粒。在第一密封體上形成重佈線路層。重佈線路層具有第一表面以及相對於第一表面的第二表面。重佈線路層的第一表面面向第一密封體。將第一密封體以及第一晶粒與載板分離。在重佈線路層的第二表面上形成多個第二晶粒。藉由第二密封體密封第二晶粒。在重佈線路層的第一表面上形成多個導電端子。
基於上述，在本發明的封裝結構中，晶粒形成在重佈線路層的兩個表面上。因此，具有較厚厚度的基板在本發明的封裝結構中可以被省略。除此之外，由於至少一個晶粒是藉由覆晶（flip-chip）的方式形成於相對於其他晶粒的另外一面，故所述至少一個晶粒可以被研磨至任意厚度。另一方面，所述至少一個晶粒可以與導電端子共面（coplanar）。因此，封裝結構的厚度能夠被減薄，藉此達到封裝結構的微型化。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1I是依據本發明一實施例的封裝結構10的製造方法的剖面示意圖。請參照圖1A，在載板100上形成重佈線路層（redistribution layer；RDL）200。載板100例如是玻璃基板或是玻璃支撐板材。然而，本發明不限於此。其他合適的基板材料也可以作為載板100，只要所述材料能夠承載在其之上所形成的封裝結構且能夠承受後續的製程即可。重佈線路層200具有第一表面202以及相對於第一表面202的第二表面204。第二表面204面向載板100。在一些實施例中，第二表面204可以與載板100直接接觸。然而，在一些替代性實施例中，為了增加在後續製程中重佈線路層200從載板100的剝離性（releasibility），可以在重佈線路層200的第二表面204以及載板100之間配置剝離層（de-bonding layer；未繪示）。剝離層例如是光熱轉換（light to heat conversion；LTHC）離型層或是其他合適的離型層。重佈線路層200被劃分為多個晶粒連接區DR以及多個接觸區CR，且接觸區CR環繞晶粒連接區DR。重佈線路層200包括第一金屬層206、第二金屬層208、第三金屬層214、多個導孔栓塞（via plug）結構210以及介電層212。第一金屬層206、第二金屬層208、第三金屬層214以及導孔栓塞結構210嵌入於介電層212中。然而，介電層212暴露出第一金屬層206、第二金屬層208以及第三金屬層214的至少一部分，用以作為之後的電性連接等目的。在一些實施例中，第一金屬層206以及第三金屬層214為藉由相同的製程所形成的相同金屬層。除此之外，第一金屬層206以及第二金屬層208位於接觸區CR中而第三金屬層214位於晶粒連接區DR中。第一金屬層206、第二金屬層208以及第三金屬層214藉由導孔栓塞結構210而彼此電性耦接。值得注意的是，為了簡單起見，在圖1A中的重佈線路層200的部分金屬層並未被繪示出。然而，在一些替代性實施例中，除了第一金屬層206、第二金屬層208以及第三金屬層214之外，重佈線路層200可以依據電路設計而包括額外的金屬層嵌入於介電層212中。重佈線路層200具有10微米至100微米的厚度。由於重佈線路層200相較於傳統上習知的基板來說較薄，故本發明的重佈線路層200不同於基板。
請參照圖1B，在重佈線路層200的第一表面202的接觸區CR中形成多個導電端子300a。在本實施例中，導電端子300a為導電凸塊（conductive bump）。然而，本發明並不限於此。導電端子300a可以由其他可能的形式呈現或為其他可能的形狀，而關於其他類型的導電端子300a的細節會在後述的實施例中描述。導電端子（導電凸塊）300a可以藉由植球製程（ball placement process）形成。舉例來說，將具有多個開口的模板（stencil）提供在重佈線路層200的第一表面202上，且模板的開口對應重佈線路層200的第一金屬層206設置。接著，將助焊劑（flux）印在被模板的開口所暴露出的第一金屬層206上。之後，將導電球體（舉例來說，焊球、金球、銅球、鎳球或類似球體）置放於模板上。藉由對導電球體施加特定的震盪頻率（vibration frequency），導電球體會掉入模板的開口中。在此之後，可以執行回焊（reflow）製程，以加強導電球體以及第一金屬層206之間的接合，並形成導電端子300a。導電端子300a與重佈線路層200的第一金屬層206電性連接。
請參照圖1C，在重佈線路層200的第一表面202的晶粒連接區DR中形成多個第一晶粒400。由於接觸區CR環繞晶粒連接區DR，在接觸區CR中形成的導電端子300a亦環繞第一晶粒400。第一晶粒400藉由覆晶（flip-chip）的方式連接至第三金屬層214，以與重佈線路層200電性連接。換言之，每一第一晶粒400的主動表面藉由凸塊402接合至重佈線路層200的第三金屬層214。除此之外，可以在第一晶粒400以及重佈線路層200之間的空隙形成底部填充膠（underfill）404以增強接合程序的信賴性。第一晶粒400例如是特殊應用積體電路（Application-Specific Integrated Circuit；ASIC）。然而，本發明不限於此。其他合適的主動元件也可以被作為第一晶粒400使用。除此之外，值得注意的是，雖然在圖1C中繪示了每一晶粒連接區DR中只有一個第一晶粒400，但每一晶粒連接區DR中的第一晶粒400的數目並不限於此。在其他實施例中，多個第一晶粒400可以在每一晶粒連接區DR中彼此相互堆疊。由於第三金屬層214與第一金屬層206電性連接，故第一晶粒400藉由凸塊402、第三金屬層214以及第一金屬層206與導電端子300a電性連接。
請參照圖1D以及圖1E，在重佈線路層200的第一表面202上形成第一密封體502以密封第一晶粒400以及導電端子300a。請參照圖1D，在第一晶粒400以及導電端子300a上形成密封材料500。第一晶粒400以及導電端子300a被密封材料500完全密封住。在一些實施例中，密封材料500可以是藉由模塑製程（molding process）所形成的模塑化合物（molding compound）。然而，在一些替代性實施例中，密封材料500可以是由例如是環氧樹脂（epoxy）或其他合適樹脂等絕緣材料所形成。密封材料500具有厚度t1且第一晶粒400具有厚度t2。接著，將密封材料500的厚度t1以及第一晶粒400的厚度t2分別減薄為厚度t3以及厚度t4，以形成暴露出導電端子300a的至少一部分的第一密封體502。在一些實施例中，厚度t1以及厚度t2可以藉由研磨來減薄。舉例來說，可以使用化學機械研磨（chemical mechanical polishing；CMP）。值得注意的是，在本實施例中，如圖1D所示，第一晶粒400高於導電端子300a。因此，為了要暴露出導電端子300a，第一晶粒400會被研磨到。然而，在一些替代性實施例中，當第一晶粒400比導電端子300a矮時，第一晶粒400的研磨為選擇性的。除此之外，由於每一第一晶粒400的主動表面朝下，故第一晶粒400可以被研磨到需求的厚度而不會影響到其電性性能。值得注意的是，第一晶粒400的厚度t4並不被特別限定，且厚度t4可以依據每一晶粒連接區DR中的第一晶粒400的數目而變化。第一晶粒400的研磨可以幫助整個封裝結構的厚度薄化，藉以達成封裝微型化的目的。值得注意的是，在本實施例中，密封第一晶粒400以及密封導電端子300a的步驟為同時執行。然而，在一些替代性實施例中，密封第一晶粒400以及密封導電端子300a的步驟可以在不同的製造步驟中進行，且其細節將會在後述的實施例中解說。
請參照圖1F，將重佈線路層200的第二表面204與載板100分離。舉例來說，重佈線路層200可以藉由化學蝕刻的方式與載板100分離。或者，如上所述，可以在重佈線路層200的第二表面204以及載板100之間配置剝離層（未繪示）。因此，可對剝離層施加外部能量（例如紫外線（UV）雷射、可見光或熱能）以使得重佈線路層200從載板100剝離。除此之外，可以對第一金屬層206、第二金屬層208以及第三金屬層214進行無電鍍鎳浸金（electroless nickel immersion gold；ENIG）鍍覆製程以加強在後續製程中的電性連接信賴性。
請參照圖1G，將圖1F所繪示的結構翻面，以使得第二表面204朝上。在重佈線路層200的第二表面204上形成多個第二晶粒600以及多個被動元件700。第二晶粒600形成於晶粒連接區DR中而被動元件700形成於接觸區CR中。第二晶粒600例如是NAND快閃記憶體等記憶體裝置。然而，本發明不限於此。其他合適的晶片也可被作為第二晶粒600使用。晶粒貼合膜（die attach film；DAF；未繪示）可以形成於第二晶粒600以及重佈線路層200之間，以加強第二晶粒600以及重佈線路層200之間的黏著力。第二晶粒600藉由導線（wire）602與重佈線路層200的第二金屬層208電性連接。換言之，第二晶粒600藉由導線602、第二金屬層208、導孔栓塞結構210以及第一金屬層206與導電端子300a電性連接。被動元件700在位於接觸區CR的第二金屬層208上形成。在一些實施例中，被動元件700對應導電端子300a設置。然而，本發明不限於此。被動元件700可以依據任何方式配置，只要被動元件700與重佈線路層200的第二金屬層208電性連接即可。類似於第二晶粒600，被動元件700也與導電端子300a電性連接。被動元件700例如是電容器、電阻器、電感器、保險絲（fuse）或是天線（antenna）。
請參照圖1H至圖1I，形成第二密封體800以密封第二晶粒600以及被動元件700。類似於第一密封體502，第二密封體800也是由模塑化合物或是絕緣材料所形成。除此之外，在導電端子300a上形成多個焊球900a，以增進與其他封裝結構的電性連接。類似於導電端子300a，焊球900a也可以藉由植球製程來形成。如上所述，導電端子300a的至少一部分被第一密封體502暴露出。因此，焊球900a形成於導電端子300a被暴露出的部分以達到電性連接的目的。在此，封裝結構陣列10a的製造過程實質上已完成。之後，對封裝結構陣列10a執行切割或單一化（singulation）製程，以形成如圖1I所示的多個封裝結構10。切割或單一化製程例如包括利用旋轉刀片或是雷射光切割。
請參照圖1I，第一晶粒400以及第二晶粒600分別形成於重佈線路層200的第一表面202以及第二表面204上。因此，具有較厚厚度的基板在封裝結構10中可以被省略。除此之外，由於第一晶粒400是藉由覆晶的方式配置，故第一晶粒400可以被研磨至任意厚度。另一方面，如圖1I所示，第一晶粒400與導電端子300a共面（coplanar）。因此，封裝結構10的厚度能夠被有效地減少，藉此達到封裝結構10的微型化。
圖2A至圖2K是依據本發明一實施例的封裝結構20的製造方法的剖面示意圖。本實施例與圖1A至圖1I的實施例相似，而差異點在於在本實施例中，導電端子300b為導電柱（conductive pillar）。
請參照圖2A，在載板100上形成重佈線路層200。載板100以及重佈線路層200類似於圖1A的實施例，故在此不再贅述。請參照圖2B，在重佈線路層200的第一表面202上形成晶種層310。晶種層310的材料例如是銅、焊料、金、鎳或其合金。晶種層310的形成方法例如是無電電鍍（electroless plating）製程、化學鍍（chemical plating）製程、熱蒸鍍（thermal evaporation）製程或濺鍍（sputtering）製程。接著，在晶種層310上形成光阻PR。光阻PR為經圖案化的膜層且具有暴露出部分晶種層310的開口OP。舉例來說，被光阻PR的開口OP暴露出的部分晶種層310對應第一金屬層206的位置。光阻PR例如包括感光性樹脂或是其他感光性材料。
請參照圖2C，在光阻PR的開口OP中填入導電材料320。換言之，導電材料320形成在被光阻PR暴露出的晶種層310上。導電材料320例如包括焊膏（solder paste）、金、銅、鎳或其他導電部材。
請參照圖2D，將光阻PR以及被導電材料320暴露出的晶種層310移除，以在第一金屬層206上形成導電端子（導電柱）300b。換言之，藉由移除光阻PR以及被光阻PR所覆蓋的晶種層310形成導電端子300b。因此，部分的晶種層310以及導電材料320構成導電端子300b。導電端子300b例如是包括焊料柱、金柱、銅柱、鎳柱或類似柱體。
請參照圖2E至圖2J，其所繪示的製程類似於圖1C至圖1H的製程，故在此不再贅述。請參照圖2J，在本實施例中，在導電端子300b上形成多個焊球900b，以增進與其他封裝結構的電性連接。焊球900b是藉由植球製程形成在被第一密封體502暴露出的導電端子300b上。類似於圖1H的封裝結構陣列10a，亦對封裝結構陣列20a執行單一化製程，以形成如圖2K所示的多個封裝結構20。
請參照圖2K，第一晶粒400以及第二晶粒600分別形成於重佈線路層200的第一表面202以及第二表面204上。因此，具有較厚厚度的基板在封裝結構20中可以被省略。除此之外，由於第一晶粒400是藉由覆晶的方式配置，故第一晶粒400可以被研磨至任意厚度。另一方面，如圖2K所示，第一晶粒400與導電端子300b共面。因此，封裝結構20的厚度能夠被有效地減少，藉此達到封裝結構20的微型化。
圖3A至圖3I是依據本發明一實施例的封裝結構30的製造方法的剖面示意圖。本實施例與圖1A至圖1I的實施例相似，而差異點在於在本實施例中，導電端子300c為模塑通孔（through molding via；TMV）。也就是說，導電端子300c在第一密封體502密封第一晶粒400之後形成。
請參照圖3A，在載板100上形成重佈線路層200。載板100以及重佈線路層200類似於圖1A的實施例，故在此不再贅述。請參照圖3B至圖3G，其所繪示的製程類似於圖1C至圖1H的製程，但省略了導電端子300a（如圖1B所示）以及焊球900a（如圖1H所示）的形成。換言之，請參照圖3C，密封材料500僅形成在第一晶粒400上。請參照圖3G，類似於圖1H的封裝結構陣列10a，在本實施例中亦對封裝結構陣列30a執行單一化製程。
接著，請參照圖3H，在第一密封體502中形成多個開口O。在一些實施例中，開口O對應第一金屬層206形成。開口O可以藉由鑽孔（drilling）製程形成。舉例來說，可以對第一密封體502執行雷射鑽孔（laser drilling）或是機械鑽孔（mechanical drilling）製程以產生開口O。由於開口O對應第一金屬層206，開口O位於接觸區CR中。
請參照圖3I，在開口O中填入導電材料以在重佈線路層200的第一表面202上形成導電端子300c。由於本實施例的導電端子300c是藉由在開口O中填入導電材料所形成，故導電端子300c可以被稱為模塑通孔。除此之外，在本實施例中，在導電端子300c上形成多個焊球900c，以增進與其他封裝結構的電性連接。焊球900c是藉由植球製程形成在被第一密封體502暴露出的導電端子300c上。
請參照圖3I，第一晶粒400以及第二晶粒600分別形成於重佈線路層200的第一表面202以及第二表面204上。因此，具有較厚厚度的基板在封裝結構30中可以被省略。除此之外，由於第一晶粒400是藉由覆晶的方式配置，故第一晶粒400可以被研磨至任意厚度。另一方面，如圖3I所示，第一晶粒400與導電端子300c共面。因此，封裝結構30的厚度能夠被有效地減少，藉此達到封裝結構30的微型化。
圖4A至圖4J是依據本發明一實施例的封裝結構的製造方法的剖面示意圖。在一些實施例中，類似於封裝結構30的封裝結構40（如圖4J所示）也可以是藉由如圖4A至圖4J的方法所製成。值得注意的是，在圖4A至圖4J的實施例中，與圖3A至圖3I類似的元件用相同的標號表示，且省略其描述。
請參照圖4A，在載板100上形成多個第一晶粒400。每一第一晶粒400具有多個凸塊402，以與後續形成的其他元件電性連接。載板100被劃分為多個晶粒連接區DR以及多個接觸區CR，且接觸區CR環繞晶粒連接區DR。第一晶粒400形成於晶粒連接區DR中。值得注意的是，圖4A中所繪示的凸塊402的形狀僅為例示，而凸塊402的具體形狀不限於此。在一些實施例中，凸塊402例如是導電柱而並非是如同圖4A所繪示的球狀。舉例來說，凸塊402可以是銅柱（copper pillar），故可以不需要錫銀。在一些實施例中，每一第一晶粒400具有重佈線路結構（未繪示）埋在第一晶粒400的上表面中，且第一晶粒400的重佈線路結構與凸塊402電性連接。在一些實施例中，載板100與第一晶粒400之間具有晶片貼合膜（die attached film；DAF；未繪示），以增強載板100與第一晶粒400彼此之間的黏著力。
請參照圖4B，在載板100以及第一晶粒400上形成第一密封體502以密封第一晶粒400。舉例來說，可以先在載板100上形成密封材料（未繪示），以密封第一晶粒400。接著，將密封材料的厚度減薄，以暴露出凸塊402並形成第一密封體502。在一些實施例中，可以使用化學機械研磨（chemical mechanical polishing；CMP）減薄密封材料的厚度，以使得第一密封體502的上表面會與凸塊402的上表面共面（coplanar）。在一些實施例中，可以進一步微蝕刻凸塊402，以使得凸塊402的上表面略低於第一密封體502的上表面，進而增進在後續步驟中形成在凸塊402以及第一密封體502上的元件的黏著力。
請參照圖4C，在第一密封體502上形成重佈線路層200。重佈線路層200具有第一表面202以及相對於第一表面202的第二表面204。第一表面202面向第一密封體502。重佈線路層200包括第一金屬層206、第二金屬層208、第三金屬層214、多個導孔栓塞（via plug）結構210以及介電層212。第一金屬層206、第二金屬層208、第三金屬層214以及導孔栓塞結構210嵌入於介電層212中。然而，介電層212暴露出第一金屬層206、第二金屬層208以及第三金屬層214的至少一部分，用以作為電性連接等目的。在一些實施例中，第一金屬層206以及第三金屬層214為藉由相同的製程所形成的相同金屬層。除此之外，第一金屬層206以及第二金屬層208位於接觸區CR中而第三金屬層214位於晶粒連接區DR中。如圖4C所示，第三金屬層214與凸塊402電性連接。第一金屬層206、第二金屬層208以及第三金屬層214藉由導孔栓塞結構210而彼此電性耦接。在一些實施例中，第一密封體502以及重佈線路層200的整體厚度約為250微米。值得注意的是，為了簡單起見，在圖4C中的重佈線路層200的部分金屬層並未被繪示出。然而，在一些替代性實施例中，除了第一金屬層206、第二金屬層208以及第三金屬層214之外，重佈線路層200可以依據電路設計而包括額外的金屬層嵌入於介電層212中。
請參照圖4D，將第一密封體502以及第一晶粒400與載板100分離。舉例來說，可以藉由化學蝕刻的方式將第一密封體502以及第一晶粒400與載板100分離。或者，可以在第一密封體502以及第一晶粒400與載板100之間配置剝離層（未繪示）。因此，可對剝離層施加外部能量（例如紫外線（UV）雷射、可見光或熱能）以使得第一密封體502以及第一晶粒400從載板100剝離。接著，對圖4D所繪示的結構進行切割或單一化（singulation）製程，以形成如圖4E所示的結構。
請參照圖4F，在重佈線路層200的第二表面204上形成多個第二晶粒600以及多個被動元件700。第二晶粒600形成於晶粒連接區DR中而被動元件700形成於接觸區CR中。晶粒貼合膜（未繪示）可以形成於第二晶粒600以及重佈線路層200之間，以加強第二晶粒600以及重佈線路層200之間的黏著力。第二晶粒600藉由導線（wire）602與重佈線路層200的第二金屬層208電性連接。被動元件700形成在位於接觸區CR的第二金屬層208上。
請參照圖4G，形成第二密封體800以密封第二晶粒600以及被動元件700。請參照圖4H，將第一密封體502以及第一晶粒400的厚度減薄。舉例來說，可以藉由機械研磨（Mechanical grinding）、化學機械研磨（Chemical-Mechanical Polishing，CMP）、蝕刻或其他合適的製程來將第一密封體502以及第一晶粒400的厚度減薄。由於第一晶粒400的主動表面是朝向重佈線路層200的第一表面202，故研磨掉的部分實際上為第一晶粒400的非主動表面。因此，就算部分的非主動表面被移除也不會影響到第一晶粒400的性能。在一些實施例中，減薄後的第一密封體502以及重佈線路層200的整體厚度約為150微米。
請參照圖4I，在第一密封體502中形成多個開口O，以暴露出重佈線路層200的第一表面202。在一些實施例中，開口O對應第一金屬層206形成。開口O可以藉由鑽孔（drilling）製程形成。舉例來說，可以對第一密封體502執行雷射鑽孔（laser drilling）或是機械鑽孔（mechanical drilling）製程以產生開口O。由於開口O對應第一金屬層206，開口O位於接觸區CR中。
請參照圖4J，在開口O中填入導電材料以在重佈線路層200的第一表面202上形成導電端子300d。由於本實施例的導電端子300d是藉由在開口O中填入導電材料所形成，故導電端子300d可以被稱為模塑通孔。除此之外，在本實施例中，在導電端子300d上形成多個焊球900d，以增進與其他封裝結構的電性連接。焊球900d是藉由植球製程形成在被第一密封體502暴露出的導電端子300d上。
請參照圖3J，第一晶粒400以及第二晶粒600分別形成於重佈線路層200的第一表面202以及第二表面204上。因此，具有較厚厚度的基板在封裝結構30中可以被省略。因此，封裝結構40的厚度能夠被有效地減少，藉此達到封裝結構40的微型化。除此之外，由於圖4A至圖4J的製程較為簡單，故亦會節省製造成本。
綜上所述，在本發明的封裝結構中，晶粒形成在重佈線路層的兩個表面上。因此，具有較厚厚度的基板在本發明的封裝結構中可以被省略。除此之外，由於至少一個晶粒是藉由覆晶的方式形成於相對於其他晶粒的另外一面，故所述至少一個晶粒可以被研磨至任意厚度。另一方面，所述至少一個晶粒可以與導電端子共面。因此，封裝結構的厚度能夠被減薄，藉此達到封裝結構的微型化。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10、20、30、40‧‧‧封裝結構
10a、20a、30a‧‧‧封裝結構陣列
100‧‧‧載板
200‧‧‧重佈線路層
202‧‧‧第一表面
204‧‧‧第二表面
206‧‧‧第一金屬層
208‧‧‧第二金屬層
210‧‧‧導孔栓塞結構
212‧‧‧介電層
214‧‧‧第三金屬層
300a、300b、300c、300d‧‧‧導電端子
310‧‧‧晶種層
320‧‧‧導電材料
400‧‧‧第一晶粒
402‧‧‧凸塊
404‧‧‧底部填充膠
500‧‧‧密封材料
502‧‧‧第一密封體
600‧‧‧第二晶粒
602‧‧‧導線
700‧‧‧被動元件
800‧‧‧第二密封體
900a、900b、900c、900d‧‧‧焊球
CR‧‧‧接觸區
DR‧‧‧晶粒連接區
PR‧‧‧光阻
OP、O‧‧‧開口
t1、t2、t3、t4‧‧‧厚度
圖1A至圖1I是依據本發明一實施例的封裝結構的製造方法的剖面示意圖。 圖2A至圖2K是依據本發明一實施例的封裝結構的製造方法的剖面示意圖。 圖3A至圖3I是依據本發明一實施例的封裝結構的製造方法的剖面示意圖。 圖4A至圖4J是依據本發明一實施例的封裝結構的製造方法的剖面示意圖。
10‧‧‧封裝結構
200‧‧‧重佈線路層
202‧‧‧第一表面
204‧‧‧第二表面
206‧‧‧第一金屬層
208‧‧‧第二金屬層
210‧‧‧導孔栓塞結構
212‧‧‧介電層
214‧‧‧第三金屬層
300a‧‧‧導電端子
400‧‧‧第一晶粒
402‧‧‧凸塊
404‧‧‧底部填充膠
502‧‧‧第一密封體
600‧‧‧第二晶粒
602‧‧‧導線
700‧‧‧被動元件
800‧‧‧第二密封體
900a‧‧‧焊球
CR‧‧‧接觸區
DR‧‧‧晶粒連接區

Claims (10)

  1. 一種封裝結構，包括： 重佈線路層，其具有第一表面以及相對於所述第一表面的第二表面； 至少一第一晶粒以及多個導電端子，其中所述第一晶粒以及所述導電端子與所述重佈線路層電性連接，且所述第一晶粒以及所述導電端子位於所述重佈線路層的所述第一表面上； 第一密封體，密封所述第一晶粒以及所述導電端子，其中所述第一密封體暴露出所述導電端子的至少一部分； 多個焊球，與所述導電端子電性連接，其中所述焊球位於被所述第一密封體暴露出的所述導電端子上； 多個第二晶粒，與所述重佈線路層電性連接且位於所述重佈線路層的所述第二表面上；以及 第二密封體，密封所述第二晶粒。
  2. 如申請專利範圍第1項所述的封裝結構，更包括多個被動元件，所述被動元件位於所述重佈線路層的所述第二表面上且對應所述導電端子設置。
  3. 如申請專利範圍第1項所述的封裝結構，其中所述第二晶粒彼此堆疊。
  4. 如申請專利範圍第1項所述的封裝結構，其中所述第一晶粒以覆晶（flip-chip）方式與所述重佈線路層電性連接。
  5. 一種封裝結構的製造方法，包括： 在載板上形成重佈線路層，其中所述重佈線路層具有第一表面以及相對於所述第一表面的第二表面，且所述重佈線路層的所述第二表面面向所述載板； 在所述重佈線路層的所述第一表面上形成多個導電端子； 在所述重佈線路層的所述第一表面上形成至少一第一晶粒； 藉由第一密封體密封所述第一晶粒； 藉由第一密封體密封所述導電端子，其中所述第一密封體暴露出所述導電端子的至少一部分； 將所述重佈線路層的所述第二表面與所述載板分離； 在所述重佈線路層的所述第二表面上形成多個第二晶粒； 藉由第二密封體密封所述第二晶粒；以及 在被所述第一密封體暴露出的所述導電端子上形成多個焊球。
  6. 一種封裝結構的製造方法，包括： 在載板上形成至少一第一晶粒； 藉由第一密封體密封所述第一晶粒； 在所述第一密封體上形成重佈線路層，其中所述重佈線路層具有第一表面以及相對於所述第一表面的第二表面，且所述重佈線路層的所述第一表面面向所述第一密封體； 將所述第一密封體以及所述第一晶粒與所述載板分離； 在所述重佈線路層的所述第二表面上形成多個第二晶粒； 藉由第二密封體密封所述第二晶粒；以及 在所述重佈線路層的所述第一表面上形成多個導電端子。
  7. 如申請專利範圍第6項所述的封裝結構的製造方法，其中在所述第一表面上形成所述導電端子的步驟包括： 在所述第一密封體中形成多個開口以暴露出所述重佈線路層的所述第一表面；以及 在所述開口中形成所述導電端子。
  8. 如申請專利範圍第6項所述的封裝結構的製造方法，其中密封所述第一晶粒的步驟在形成所述導電端子的步驟之前執行。
  9. 如申請專利範圍第6項所述的封裝結構的製造方法，其中密封所述第一晶粒的步驟包括： 在所述第一晶粒上形成密封材料；以及 減薄所述密封材料的厚度，以暴露出所述第一晶粒的至少一部分。
  10. 如申請專利範圍第6項所述的封裝結構的製造方法，其中在分離所述第一密封體以及所述第一晶粒與所述載板之後，更包括： 減薄所述密封材料以及所述第一晶粒的厚度。
TW106113221A 2016-04-20 2017-04-20 封裝結構及其製造方法 TWI644403B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662324899P 2016-04-20 2016-04-20
US62/324,899 2016-04-20
US15/264,606 US9659911B1 (en) 2016-04-20 2016-09-14 Package structure and manufacturing method thereof
US15/264,606 2016-09-14

Publications (2)

Publication Number Publication Date
TW201806101A true TW201806101A (zh) 2018-02-16
TWI644403B TWI644403B (zh) 2018-12-11

Family

ID=58708196

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106113221A TWI644403B (zh) 2016-04-20 2017-04-20 封裝結構及其製造方法

Country Status (3)

Country Link
US (2) US9659911B1 (zh)
CN (1) CN107424938A (zh)
TW (1) TWI644403B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI680553B (zh) * 2018-10-26 2019-12-21 英屬開曼群島商鳳凰先驅股份有限公司 半導體封裝結構及其製作方法
CN111106096A (zh) * 2018-10-26 2020-05-05 凤凰先驱股份有限公司 半导体封装结构及其制作方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016192447A (ja) * 2015-03-30 2016-11-10 株式会社東芝 半導体装置
US9659911B1 (en) * 2016-04-20 2017-05-23 Powertech Technology Inc. Package structure and manufacturing method thereof
US9935080B2 (en) * 2016-04-29 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Three-layer Package-on-Package structure and method forming same
US10304716B1 (en) * 2017-12-20 2019-05-28 Powertech Technology Inc. Package structure and manufacturing method thereof
JP2019149507A (ja) * 2018-02-28 2019-09-05 東芝メモリ株式会社 半導体装置及びその製造方法
US10950529B2 (en) * 2018-08-30 2021-03-16 Advanced Semiconductor Engineering Korea, Inc. Semiconductor device package
TWI665770B (zh) * 2018-12-13 2019-07-11 力成科技股份有限公司 半導體封裝結構及其製法
TWI710090B (zh) * 2019-09-06 2020-11-11 力成科技股份有限公司 半導體封裝結構及其製造方法
CN110767648A (zh) * 2019-10-29 2020-02-07 华天科技（西安）有限公司 一种加铜柱型的ssd存储芯片封装结构及其封装方法
US20230011439A1 (en) * 2021-07-07 2023-01-12 Western Digital Technologies, Inc. Semiconductor Device Package Die Stacking System and Method
WO2023223472A1 (ja) * 2022-05-18 2023-11-23 ウルトラメモリ株式会社 半導体モジュール及びその製造方法

Family Cites Families (106)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3798597B2 (ja) * 1999-11-30 2006-07-19 富士通株式会社 半導体装置
US6930256B1 (en) * 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
US6905914B1 (en) * 2002-11-08 2005-06-14 Amkor Technology, Inc. Wafer level package and fabrication method
SG133445A1 (en) * 2005-12-29 2007-07-30 Micron Technology Inc Methods for packaging microelectronic devices and microelectronic devices formed using such methods
US8072059B2 (en) * 2006-04-19 2011-12-06 Stats Chippac, Ltd. Semiconductor device and method of forming UBM fixed relative to interconnect structure for alignment of semiconductor die
US7993972B2 (en) * 2008-03-04 2011-08-09 Stats Chippac, Ltd. Wafer level die integration and method therefor
US7242081B1 (en) * 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure
US7723159B2 (en) * 2007-05-04 2010-05-25 Stats Chippac, Ltd. Package-on-package using through-hole via die on saw streets
US7651889B2 (en) * 2007-09-13 2010-01-26 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
US20090170241A1 (en) * 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
US7969018B2 (en) * 2008-07-15 2011-06-28 Infineon Technologies Ag Stacked semiconductor chips with separate encapsulations
US8546189B2 (en) * 2008-09-22 2013-10-01 Stats Chippac, Ltd. Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection
US7888181B2 (en) * 2008-09-22 2011-02-15 Stats Chippac, Ltd. Method of forming a wafer level package with RDL interconnection over encapsulant between bump and semiconductor die
US8704350B2 (en) * 2008-11-13 2014-04-22 Samsung Electro-Mechanics Co., Ltd. Stacked wafer level package and method of manufacturing the same
US8183677B2 (en) * 2008-11-26 2012-05-22 Infineon Technologies Ag Device including a semiconductor chip
US9082806B2 (en) * 2008-12-12 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US8592992B2 (en) * 2011-12-14 2013-11-26 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
US9064936B2 (en) * 2008-12-12 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US8012797B2 (en) * 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
US8194411B2 (en) * 2009-03-31 2012-06-05 Hong Kong Applied Science and Technology Research Institute Co. Ltd Electronic package with stacked modules with channels passing through metal layers of the modules
US8169070B2 (en) * 2009-05-15 2012-05-01 Infineon Technologies Ag Semiconductor device
KR101619473B1 (ko) * 2009-07-21 2016-05-11 삼성전자주식회사 히트 슬러그를 갖는 반도체 패키지
US8039304B2 (en) * 2009-08-12 2011-10-18 Stats Chippac, Ltd. Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structures
US8383457B2 (en) * 2010-09-03 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
US9875911B2 (en) * 2009-09-23 2018-01-23 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interposer with opening to contain semiconductor die
US8796561B1 (en) * 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US8937381B1 (en) * 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US8822281B2 (en) * 2010-02-23 2014-09-02 Stats Chippac, Ltd. Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier
US8338231B2 (en) * 2010-03-29 2012-12-25 Infineon Technologies Ag Encapsulated semiconductor chip with external contact pads and manufacturing method thereof
US8357564B2 (en) * 2010-05-17 2013-01-22 Stats Chippac, Ltd. Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor die
US9269691B2 (en) * 2010-05-26 2016-02-23 Stats Chippac, Ltd. Semiconductor device and method of making an embedded wafer level ball grid array (EWLB) package on package (POP) device with a slotted metal carrier interposer
US9484279B2 (en) * 2010-06-02 2016-11-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming EMI shielding layer with conductive material around semiconductor die
KR101855294B1 (ko) * 2010-06-10 2018-05-08 삼성전자주식회사 반도체 패키지
US8796137B2 (en) * 2010-06-24 2014-08-05 Stats Chippac, Ltd. Semiconductor device and method of forming RDL along sloped side surface of semiconductor die for z-direction interconnect
US8895440B2 (en) * 2010-08-06 2014-11-25 Stats Chippac, Ltd. Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
US8318541B2 (en) * 2010-08-10 2012-11-27 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect in FO-WLCSP using leadframe disposed between semiconductor die
US20120049334A1 (en) * 2010-08-27 2012-03-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Leadframe as Vertical Interconnect Structure Between Stacked Semiconductor Die
US8097490B1 (en) * 2010-08-27 2012-01-17 Stats Chippac, Ltd. Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die
US8518746B2 (en) * 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
TWI492349B (zh) * 2010-09-09 2015-07-11 矽品精密工業股份有限公司 晶片尺寸封裝件及其製法
US8263435B2 (en) * 2010-10-28 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive vias
US8482134B1 (en) * 2010-11-01 2013-07-09 Amkor Technology, Inc. Stackable package and method
US9202715B2 (en) * 2010-11-16 2015-12-01 Stats Chippac Ltd. Integrated circuit packaging system with connection structure and method of manufacture thereof
KR101817159B1 (ko) * 2011-02-17 2018-02-22 삼성전자 주식회사 Ｔｓｖ를 가지는 인터포저를 포함하는 반도체 패키지 및 그 제조 방법
US8466544B2 (en) * 2011-02-25 2013-06-18 Stats Chippac, Ltd. Semiconductor device and method of forming interposer and opposing build-up interconnect structure with connecting conductive TMV for electrical interconnect of Fo-WLCSP
US8288203B2 (en) * 2011-02-25 2012-10-16 Stats Chippac, Ltd. Semiconductor device and method of forming a wafer level package structure using conductive via and exposed bump
US9013011B1 (en) * 2011-03-11 2015-04-21 Amkor Technology, Inc. Stacked and staggered die MEMS package and method
US8883561B2 (en) * 2011-04-30 2014-11-11 Stats Chippac, Ltd. Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP
US8389333B2 (en) * 2011-05-26 2013-03-05 Stats Chippac, Ltd. Semiconductor device and method of forming EWLB package containing stacked semiconductor die electrically connected through conductive vias formed in encapsulant around die
US8530277B2 (en) * 2011-06-16 2013-09-10 Stats Chippac Ltd. Integrated circuit packaging system with package on package support and method of manufacture thereof
US20130037929A1 (en) * 2011-08-09 2013-02-14 Kay S. Essig Stackable wafer level packages and related methods
US9064883B2 (en) * 2011-08-25 2015-06-23 Intel Mobile Communications GmbH Chip with encapsulated sides and exposed surface
US9564413B2 (en) * 2011-09-15 2017-02-07 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming semiconductor die with active region responsive to external stimulus
US9177832B2 (en) * 2011-09-16 2015-11-03 Stats Chippac, Ltd. Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect
US8513057B2 (en) * 2011-09-16 2013-08-20 Stats Chippac Ltd. Integrated circuit packaging system with routable underlayer and method of manufacture thereof
US8816404B2 (en) * 2011-09-16 2014-08-26 Stats Chippac, Ltd. Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant
US8633598B1 (en) * 2011-09-20 2014-01-21 Amkor Technology, Inc. Underfill contacting stacking balls package fabrication method and structure
US9679863B2 (en) * 2011-09-23 2017-06-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interconnect substrate for FO-WLCSP
US8778733B2 (en) * 2012-03-19 2014-07-15 Infineon Technologies Ag Semiconductor package and methods of formation thereof
US10049964B2 (en) * 2012-03-23 2018-08-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
US9385006B2 (en) * 2012-06-21 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an embedded SOP fan-out package
US8889484B2 (en) * 2012-10-02 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for a component package
US8952521B2 (en) * 2012-10-19 2015-02-10 Infineon Technologies Ag Semiconductor packages with integrated antenna and method of forming thereof
US8878353B2 (en) * 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US8890284B2 (en) * 2013-02-22 2014-11-18 Infineon Technologies Ag Semiconductor device
US8993380B2 (en) * 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9337073B2 (en) * 2013-03-12 2016-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3D shielding case and methods for forming the same
KR101488590B1 (ko) * 2013-03-29 2015-01-30 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US8669140B1 (en) * 2013-04-04 2014-03-11 Freescale Semiconductor, Inc. Method of forming stacked die package using redistributed chip packaging
US8941225B2 (en) * 2013-04-18 2015-01-27 Sts Semiconductor & Telecommunications Co., Ltd. Integrated circuit package and method for manufacturing the same
US9076882B2 (en) 2013-06-03 2015-07-07 Intel Corporation Methods for high precision microelectronic die integration
US8980691B2 (en) * 2013-06-28 2015-03-17 Stats Chippac, Ltd. Semiconductor device and method of forming low profile 3D fan-out package
US9252092B2 (en) * 2013-07-24 2016-02-02 Stats Chippac, Ltd. Semiconductor device and method of forming through mold hole with alignment and dimension control
US9082766B2 (en) * 2013-08-06 2015-07-14 Google Technology Holdings LLC Method to enhance reliability of through mold via TMVA part on part POP devices
US9252076B2 (en) * 2013-08-07 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9184128B2 (en) * 2013-12-13 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC package and methods of forming the same
US9653442B2 (en) * 2014-01-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and methods of forming same
US9721852B2 (en) * 2014-01-21 2017-08-01 International Business Machines Corporation Semiconductor TSV device package to which other semiconductor device package can be later attached
US9735129B2 (en) * 2014-03-21 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US20150282367A1 (en) * 2014-03-27 2015-10-01 Hans-Joachim Barth Electronic assembly that includes stacked electronic components
US9601463B2 (en) * 2014-04-17 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) and the methods of making the same
US9385110B2 (en) * 2014-06-18 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US20150380392A1 (en) * 2014-06-27 2015-12-31 Apple Inc. Package with memory die and logic die interconnected in a face-to-face configuration
KR102212827B1 (ko) * 2014-06-30 2021-02-08 엘지이노텍 주식회사 인쇄회로기판, 패키지 기판 및 이의 제조 방법
TWI567888B (zh) * 2014-07-11 2017-01-21 矽品精密工業股份有限公司 封裝結構及其製法
US9368566B2 (en) * 2014-07-17 2016-06-14 Qualcomm Incorporated Package on package (PoP) integrated device comprising a capacitor in a substrate
TWI623984B (zh) * 2014-08-12 2018-05-11 矽品精密工業股份有限公司 封裝結構及其製法
US9646918B2 (en) * 2014-08-14 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9425179B2 (en) * 2014-08-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Chip packages and methods of manufacture thereof
US9653445B2 (en) * 2014-10-24 2017-05-16 STATS ChipPAC Pte. Ltd. Semiconductor device and method of fabricating 3D package with short cycle time and high yield
US10325853B2 (en) * 2014-12-03 2019-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
US9269887B1 (en) * 2015-01-06 2016-02-23 Triquint Semiconductor, Inc. Ultrathin flip-chip packaging techniques and configurations
KR101672622B1 (ko) * 2015-02-09 2016-11-03 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9746889B2 (en) * 2015-05-11 2017-08-29 Qualcomm Incorporated Package-on-package (PoP) device comprising bi-directional thermal electric cooler
JP2017017238A (ja) * 2015-07-03 2017-01-19 株式会社ジェイデバイス 半導体装置及びその製造方法
US9806040B2 (en) * 2015-07-29 2017-10-31 STATS ChipPAC Pte. Ltd. Antenna in embedded wafer-level ball-grid array package
US9899285B2 (en) * 2015-07-30 2018-02-20 Semtech Corporation Semiconductor device and method of forming small Z semiconductor package
US10269767B2 (en) * 2015-07-31 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip packages with multi-fan-out scheme and methods of manufacturing the same
KR102384863B1 (ko) * 2015-09-09 2022-04-08 삼성전자주식회사 반도체 칩 패키지 및 이의 제조 방법
US9449953B1 (en) * 2015-10-08 2016-09-20 Inotera Memories, Inc. Package-on-package assembly and method for manufacturing the same
US9607967B1 (en) * 2015-11-04 2017-03-28 Inotera Memories, Inc. Multi-chip semiconductor package with via components and method for manufacturing the same
US9735131B2 (en) * 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US9627365B1 (en) * 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
TW201724423A (zh) * 2015-12-23 2017-07-01 力成科技股份有限公司 扇出型封裝堆疊構造與方法
US9620465B1 (en) * 2016-01-25 2017-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dual-sided integrated fan-out package
US9659911B1 (en) * 2016-04-20 2017-05-23 Powertech Technology Inc. Package structure and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI680553B (zh) * 2018-10-26 2019-12-21 英屬開曼群島商鳳凰先驅股份有限公司 半導體封裝結構及其製作方法
CN111106096A (zh) * 2018-10-26 2020-05-05 凤凰先驱股份有限公司 半导体封装结构及其制作方法
CN111106096B (zh) * 2018-10-26 2024-01-05 恒劲科技股份有限公司 半导体封装结构及其制作方法

Also Published As

Publication number Publication date
TWI644403B (zh) 2018-12-11
US9831219B2 (en) 2017-11-28
CN107424938A (zh) 2017-12-01
US9659911B1 (en) 2017-05-23
US20170309597A1 (en) 2017-10-26

Similar Documents

Publication Publication Date Title
TWI644403B (zh) 封裝結構及其製造方法
TWI683378B (zh) 半導體封裝及其製造方法
TWI690030B (zh) 半導體封裝及其形成方法
TWI710072B (zh) 半導體裝置封裝體及其製造方法
TWI714913B (zh) 封裝結構及其製造方法
TWI683410B (zh) 半導體封裝及其形成方法
TWI749005B (zh) 半導體裝置及其製造方法
KR101822236B1 (ko) 반도체 디바이스 및 제조 방법
TWI649845B (zh) 半導體封裝結構及其製造方法
TWI508226B (zh) 在基板的孔穴中鑲嵌具有直通矽晶穿孔的晶粒用以扇入封裝疊加的電互連之半導體裝置和方法
US10340253B2 (en) Package structure and method of manufacturing the same
KR102108981B1 (ko) 반도체 패키지 및 방법
TWI697085B (zh) 半導體元件及其形成方法
TWI721225B (zh) 封裝結構及其製造方法
US10431549B2 (en) Semiconductor package and manufacturing method thereof
TW201824486A (zh) 封裝結構
US10510732B2 (en) PoP device and method of forming the same
WO2010058646A1 (ja) 半導体パッケージおよびその製造方法
TW201742209A (zh) 積體扇出型封裝體
TW201919190A (zh) 封裝結構及其製造方法
US10290610B2 (en) PoP device and method of forming the same
US11217518B2 (en) Package structure and method of forming the same
TW202133282A (zh) 半導體封裝
US11901277B2 (en) Semiconductor package and method of manufacturing the same
TWI779917B (zh) 半導體封裝及其製作方法