CN107424938A - 封装结构及其制造方法 - Google Patents

封装结构及其制造方法 Download PDF

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Publication number
CN107424938A
CN107424938A CN201710261068.9A CN201710261068A CN107424938A CN 107424938 A CN107424938 A CN 107424938A CN 201710261068 A CN201710261068 A CN 201710261068A CN 107424938 A CN107424938 A CN 107424938A
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China
Prior art keywords
crystal grain
seal
road floor
conducting terminal
encapsulating structure
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CN201710261068.9A
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English (en)
Inventor
张家维
方立志
林国鼎
庄咏程
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Powertech Technology Inc
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Powertech Technology Inc
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Publication of CN107424938A publication Critical patent/CN107424938A/zh
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Abstract

本发明提供一种封装结构及其制造方法。封装结构包括重布线路层、至少一第一晶粒、多个导电端子、第一密封体、多个焊球、多个第二晶粒以及第二密封体。重布线路层具有第一表面以及相对于第一表面的第二表面。第一晶粒以及导电端子与重布线路层电性连接且位于重布线路层的第一表面上。第一密封体密封第一晶粒以及导电端子且暴露出导电端子的至少一部分。焊球与导电端子电性连接且位于被第一密封体暴露出的导电端子上。第二晶粒与重布线路层电性连接且位于重布线路层的第二表面上。第二密封体密封第二晶粒。

Description

封装结构及其制造方法
技术领域
本发明涉及一种封装结构及其制造方法，尤其涉及一种具有在重布线路 层的两面皆配置有晶粒的封装结构及其制造方法。
背景技术
为了使得电子产品能达到轻薄短小的设计，半导体封装技术也跟着日益 进展，以发展出符合小体积、重量轻、高密度以及在市场上具有高竞争力等 要求的产品。举例来说，为了使得电子产品较薄，通常会希望提供具有较小 厚度的高密度封装结构。因此，如何在封装结构微型化的同时还能够维持封 装结构中所密封的芯片数目成为本领域的技术人员的一大挑战。
发明内容
本发明提供一种封装结构及其制造方法，能够有效地减小其尺寸。
本发明提供一种封装结构，其包括重布线路层、至少一第一晶粒、多个 导电端子、第一密封体、多个焊球、多个第二晶粒以及第二密封体。重布线 路层具有第一表面以及相对于第一表面的第二表面。第一晶粒以及导电端子 与重布线路层电性连接且位于重布线路层的第一表面上。第一密封体密封第 一晶粒以及导电端子且暴露出导电端子的至少一部分。焊球与导电端子电性 连接且位于被第一密封体暴露出的导电端子上。第二晶粒与重布线路层电性 连接且位于重布线路层的第二表面上。第二密封体密封第二晶粒。
本发明提供一种封装结构的制造方法，其至少包括以下步骤。在载板上 形成重布线路层。重布线路层具有第一表面以及相对于第一表面的第二表面， 且重布线路层的第二表面面向载板。在重布线路层的第一表面上形成多个导 电端子以及至少一第一晶粒。通过第一密封体密封第一晶粒以及导电端子， 且第一密封体暴露出导电端子的至少一部分。将重布线路层的第二表面与载 板分离。在重布线路层的第二表面上形成多个第二晶粒。通过第二密封体密 封第二晶粒。在被第一密封体暴露出的导电端子上形成多个焊球。
本发明提供一种封装结构的制造方法，其至少包括以下步骤。在载板上 形成至少一第一晶粒。通过第一密封体密封第一晶粒。在第一密封体上形成 重布线路层。重布线路层具有第一表面以及相对于第一表面的第二表面。重 布线路层的第一表面面向第一密封体。将第一密封体以及第一晶粒与载板分 离。在重布线路层的第二表面上形成多个第二晶粒。通过第二密封体密封第 二晶粒。在重布线路层的第一表面上形成多个导电端子。
基于上述，在本发明的封装结构中，晶粒形成在重布线路层的两个表面 上。因此，具有较厚厚度的基板在本发明的封装结构中可以被省略。除此之 外，由于至少一个晶粒是通过倒装芯片(flip-chip)的方式形成于相对于其他 晶粒的另外一面，故所述至少一个晶粒可以被研磨至任意厚度。另一方面， 所述至少一个晶粒可以与导电端子共面(coplanar)。因此，封装结构的厚度 能够被减薄，藉此达到封装结构的微型化。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合 所附附图作详细说明如下。
附图说明
图1A至图1I是依据本发明一实施例的封装结构的制造方法的剖面示意 图。
图2A至图2K是依据本发明一实施例的封装结构的制造方法的剖面示意 图。
图3A至图3I是依据本发明一实施例的封装结构的制造方法的剖面示意 图。
图4A至图4J是依据本发明一实施例的封装结构的制造方法的剖面示意 图。
【符号说明】
10、20、30、40：封装结构
10a、20a、30a：封装结构阵列
100：载板
200：重布线路层
202：第一表面
204：第二表面
206：第一金属层
208：第二金属层
210：导孔栓塞结构
212：介电层
214：第三金属层
300a、300b、300c、300d：导电端子
310：晶种层
320：导电材料
400：第一晶粒
402：凸块
404：底部填充胶
500：密封材料
502：第一密封体
600：第二晶粒
602：导线
700：无源元件
800：第二密封体
900a、900b、900c、900d：焊球
CR：接触区
DR：晶粒连接区
PR：光阻
OP、O：开口
t1、t2、t3、t4：厚度
具体实施方式
图1A至图1I是依据本发明一实施例的封装结构10的制造方法的剖面示 意图。请参照图1A，在载板100上形成重布线路层(redistribution layer；RDL) 200。载板100例如是玻璃基板或是玻璃支撑板材。然而，本发明不限于此。 其他合适的基板材料也可以作为载板100，只要所述材料能够承载在其上所 形成的封装结构且能够承受后续的制程即可。重布线路层200具有第一表面 202以及相对于第一表面202的第二表面204。第二表面204面向载板100。 在一些实施例中，第二表面204可以与载板100直接接触。然而，在一些替 代性实施例中，为了增加在后续制程中重布线路层200从载板100的剥离性 (releasibility)，可以在重布线路层200的第二表面204以及载板100之间 配置剥离层(de-bonding layer；未示出)。剥离层例如是光热转换(light to heat conversion；LTHC)离型层或是其他合适的离型层。重布线路层200被划分 为多个晶粒连接区DR以及多个接触区CR，且接触区CR环绕晶粒连接区 DR。重布线路层200包括第一金属层206、第二金属层208、第三金属层214、多个导孔栓塞(via plug)结构210以及介电层212。第一金属层206、第二 金属层208、第三金属层214以及导孔栓塞结构210嵌入于介电层212中。 然而，介电层212暴露出第一金属层206、第二金属层208以及第三金属层 214的至少一部分，用以作为之后的电性连接等目的。在一些实施例中，第 一金属层206以及第三金属层214为通过相同的制程所形成的相同金属层。 除此之外，第一金属层206以及第二金属层208位于接触区CR中而第三金 属层214位于晶粒连接区DR中。第一金属层206、第二金属层208以及第三 金属层214通过导孔栓塞结构210而彼此电性耦接。值得注意的是，为了简 单起见，在图1A中的重布线路层200的部分金属层并未被示出。然而，在 一些替代性实施例中，除了第一金属层206、第二金属层208以及第三金属 层214之外，重布线路层200可以依据电路设计而包括额外的金属层嵌入于 介电层212中。重布线路层200具有10微米至100微米的厚度。由于重布线 路层200相较于传统上的基板来说较薄，故本发明的重布线路层200不同于 基板。
请参照图1B，在重布线路层200的第一表面202的接触区CR中形成多 个导电端子300a。在本实施例中，导电端子300a为导电凸块(conductive bump)。然而，本发明并不限于此。导电端子300a可以由其他可能的形式 呈现或为其他可能的形状，而关于其他类型的导电端子300a的细节会在后述 的实施例中描述。导电端子(导电凸块)300a可以通过植球制程(ball placement process)形成。举例来说，将具有多个开口的模板(stencil)提供在重布线路 层200的第一表面202上，且模板的开口对应重布线路层200的第一金属层 206设置。接着，将助焊剂(flux)印在被模板的开口所暴露出的第一金属层 206上。之后，将导电球体(举例来说，焊球、金球、铜球、镍球或类似球 体)置放于模板上。通过对导电球体施加特定的震荡频率(vibration frequency)，导电球体会掉入模板的开口中。在此之后，可以执行回焊(reflow) 制程，以加强导电球体以及第一金属层206之间的接合，并形成导电端子 300a。导电端子300a与重布线路层200的第一金属层206电性连接。
请参照图1C，在重布线路层200的第一表面202的晶粒连接区DR中形 成多个第一晶粒400。由于接触区CR环绕晶粒连接区DR，在接触区CR中 形成的导电端子300a也环绕第一晶粒400。第一晶粒400通过倒装芯片 (flip-chip)的方式连接至第三金属层214，以与重布线路层200电性连接。 换言之，每一第一晶粒400的主动表面通过凸块402接合至重布线路层200 的第三金属层214。除此之外，可以在第一晶粒400以及重布线路层200之 间的空隙形成底部填充胶(underfill)404以增强接合程序的信赖性。第一晶 粒400例如是特殊应用集成电路(Application-Specific Integrated Circuit； ASIC)。然而，本发明不限于此。其他合适的有源元件也可以被作为第一晶 粒400使用。除此之外，值得注意的是，虽然在图1C中示出了每一晶粒连接 区DR中只有一个第一晶粒400，但每一晶粒连接区DR中的第一晶粒400的 数目并不限于此。在其他实施例中，多个第一晶粒400可以在每一晶粒连接区DR中彼此相互堆叠。由于第三金属层214与第一金属层206电性连接， 故第一晶粒400通过凸块402、第三金属层214以及第一金属层206与导电 端子300a电性连接。
请参照图1D以及图1E，在重布线路层200的第一表面202上形成第一 密封体502以密封第一晶粒400以及导电端子300a。请参照图1D，在第一晶 粒400以及导电端子300a上形成密封材料500。第一晶粒400以及导电端子 300a被密封材料500完全密封住。在一些实施例中，密封材料500可以是通 过模塑制程(molding process)所形成的模塑化合物(molding compound)。 然而，在一些替代性实施例中，密封材料500可以是由例如是环氧树脂(epoxy) 或其他合适树脂等绝缘材料所形成。密封材料500具有厚度t1且第一晶粒400具有厚度t2。接着，将密封材料500的厚度t1以及第一晶粒400的厚度t2分 别减薄为厚度t3以及厚度t4，以形成暴露出导电端子300a的至少一部分的 第一密封体502。在一些实施例中，厚度t1以及厚度t2可以通过研磨来减薄。 举例来说，可以使用化学机械研磨(chemicalmechanical polishing；CMP)。 值得注意的是，在本实施例中，如图1D所示，第一晶粒400高于导电端子 300a。因此，为了要暴露出导电端子300a，第一晶粒400会被研磨到。然而， 在一些替代性实施例中，当第一晶粒400比导电端子300a矮时，第一晶粒400 的研磨为选择性的。除此之外，由于每一第一晶粒400的主动表面朝下，故 第一晶粒400可以被研磨到需求的厚度而不会影响到其电性性能。值得注意 的是，第一晶粒400的厚度t4并不被特别限定，且厚度t4可以依据每一晶粒 连接区DR中的第一晶粒400的数目而变化。第一晶粒400的研磨可以帮助 整个封装结构的厚度薄化，藉以达成封装微型化的目的。值得注意的是，在 本实施例中，密封第一晶粒400以及密封导电端子300a的步骤为同时执行。 然而，在一些替代性实施例中，密封第一晶粒400以及密封导电端子300a的 步骤可以在不同的制造步骤中进行，且其细节将会在后述的实施例中解说。
请参照图1F，将重布线路层200的第二表面204与载板100分离。举例 来说，重布线路层200可以通过化学蚀刻的方式与载板100分离。或者，如 上所述，可以在重布线路层200的第二表面204以及载板100之间配置剥离 层(未示出)。因此，可对剥离层施加外部能量(例如紫外线(UV)激光、 可见光或热能)以使得重布线路层200从载板100剥离。除此之外，可以对 第一金属层206、第二金属层208以及第三金属层214进行无电镀镍浸金(electroless nickel immersion gold；ENIG)镀覆制程以加强在后续制程中的 电性连接信赖性。
请参照图1G，将图1F所示出的结构翻面，以使得第二表面204朝上。 在重布线路层200的第二表面204上形成多个第二晶粒600以及多个无源元 件700。第二晶粒600形成于晶粒连接区DR中而无源元件700形成于接触区 CR中。第二晶粒600例如是NAND快闪存储器等存储装置。然而，本发明 不限于此。其他合适的芯片也可被作为第二晶粒600使用。晶粒贴合膜(die attach film；DAF；未示出)可以形成于第二晶粒600以及重布线路层200之 间，以加强第二晶粒600以及重布线路层200之间的黏着力。第二晶粒600 通过导线(wire)602与重布线路层200的第二金属层208电性连接。换言之， 第二晶粒600通过导线602、第二金属层208、导孔栓塞结构210以及第一金 属层206与导电端子300a电性连接。无源元件700在位于接触区CR的第二 金属层208上形成。在一些实施例中，无源元件700对应导电端子300a设置。 然而，本发明不限于此。无源元件700可以依据任何方式配置，只要无源元 件700与重布线路层200的第二金属层208电性连接即可。类似于第二晶粒 600，无源元件700也与导电端子300a电性连接。无源元件700例如是电容 器、电阻器、电感器、保险丝(fuse)或是天线(antenna)。
请参照图1H至图1I，形成第二密封体800以密封第二晶粒600以及无 源元件700。类似于第一密封体502，第二密封体800也是由模塑化合物或是 绝缘材料所形成。除此之外，在导电端子300a上形成多个焊球900a，以增进 与其他封装结构的电性连接。类似于导电端子300a，焊球900a也可以通过植 球制程来形成。如上所述，导电端子300a的至少一部分被第一密封体502暴 露出。因此，焊球900a形成于导电端子300a被暴露出的部分以达到电性连 接的目的。在此，封装结构阵列10a的制造过程实质上已完成。之后，对封 装结构阵列10a执行切割或单一化(singulation)制程，以形成如图1I所示 的多个封装结构10。切割或单一化制程例如包括利用旋转刀片或是激光切割。
请参照图1I，第一晶粒400以及第二晶粒600分别形成于重布线路层200 的第一表面202以及第二表面204上。因此，具有较厚厚度的基板在封装结 构10中可以被省略。除此之外，由于第一晶粒400是通过倒装芯片的方式配 置，故第一晶粒400可以被研磨至任意厚度。另一方面，如图1I所示，第一 晶粒400与导电端子300a共面(coplanar)。因此，封装结构10的厚度能够 被有效地减少，藉此达到封装结构10的微型化。
图2A至图2K是依据本发明一实施例的封装结构20的制造方法的剖面 示意图。本实施例与图1A至图1I的实施例相似，而差异点在于在本实施例 中，导电端子300b为导电柱(conductive pillar)。
请参照图2A，在载板100上形成重布线路层200。载板100以及重布线 路层200类似于图1A的实施例，故在此不再赘述。请参照图2B，在重布线 路层200的第一表面202上形成晶种层310。晶种层310的材料例如是铜、 焊料、金、镍或其合金。晶种层310的形成方法例如是无电电镀(electroless plating)制程、化学镀(chemical plating)制程、热蒸镀(thermal evaporation) 制程或溅镀(sputtering)制程。接着，在晶种层310上形成光阻PR。光阻 PR为经图案化的膜层且具有暴露出部分晶种层310的开口OP。举例来说， 被光阻PR的开口OP暴露出的部分晶种层310对应第一金属层206的位置。 光阻PR例如包括感光性树脂或是其他感光性材料。
请参照图2C，在光阻PR的开口OP中填入导电材料320。换言之，导电 材料320形成在被光阻PR暴露出的晶种层310上。导电材料320例如包括 焊膏(solder paste)、金、铜、镍或其他导电部材。
请参照图2D，将光阻PR以及被导电材料320暴露出的晶种层310移除， 以在第一金属层206上形成导电端子(导电柱)300b。换言之，通过移除光 阻PR以及被光阻PR所覆盖的晶种层310形成导电端子300b。因此，部分的 晶种层310以及导电材料320构成导电端子300b。导电端子300b例如是包 括焊料柱、金柱、铜柱、镍柱或类似柱体。
请参照图2E至图2J，其所示出的制程类似于图1C至图1H的制程，故 在此不再赘述。请参照图2J，在本实施例中，在导电端子300b上形成多个焊 球900b，以增进与其他封装结构的电性连接。焊球900b是通过植球制程形 成在被第一密封体502暴露出的导电端子300b上。类似于图1H的封装结构 阵列10a，亦对封装结构阵列20a执行单一化制程，以形成如图2K所示的多 个封装结构20。
请参照图2K，第一晶粒400以及第二晶粒600分别形成于重布线路层 200的第一表面202以及第二表面204上。因此，具有较厚厚度的基板在封 装结构20中可以被省略。除此之外，由于第一晶粒400是通过倒装芯片的方 式配置，故第一晶粒400可以被研磨至任意厚度。另一方面，如图2K所示， 第一晶粒400与导电端子300b共面。因此，封装结构20的厚度能够被有效 地减少，藉此达到封装结构20的微型化。
图3A至图3I是依据本发明一实施例的封装结构30的制造方法的剖面示 意图。本实施例与图1A至图1I的实施例相似，而差异点在于在本实施例中， 导电端子300c为模塑通孔(through molding via；TMV)。也就是说，导电 端子300c在第一密封体502密封第一晶粒400之后形成。
请参照图3A，在载板100上形成重布线路层200。载板100以及重布线 路层200类似于图1A的实施例，故在此不再赘述。请参照图3B至图3G， 其所示出的制程类似于图1C至图1H的制程，但省略了导电端子300a(如图 1B所示)以及焊球900a(如图1H所示)的形成。换言之，请参照图3C， 密封材料500仅形成在第一晶粒400上。请参照图3G，类似于图1H的封装结构阵列10a，在本实施例中亦对封装结构阵列30a执行单一化制程。
接着，请参照图3H，在第一密封体502中形成多个开口O。在一些实施 例中，开口O对应第一金属层206形成。开口O可以通过钻孔(drilling)制 程形成。举例来说，可以对第一密封体502执行激光钻孔(laser drilling)或 是机械钻孔(mechanical drilling)制程以产生开口O。由于开口O对应第一 金属层206，开口O位于接触区CR中。
请参照图3I，在开口O中填入导电材料以在重布线路层200的第一表面 202上形成导电端子300c。由于本实施例的导电端子300c是通过在开口O中 填入导电材料所形成，故导电端子300c可以被称为模塑通孔。除此之外，在 本实施例中，在导电端子300c上形成多个焊球900c，以增进与其他封装结构 的电性连接。焊球900c是通过植球制程形成在被第一密封体502暴露出的导 电端子300c上。
请参照图3I，第一晶粒400以及第二晶粒600分别形成于重布线路层200 的第一表面202以及第二表面204上。因此，具有较厚厚度的基板在封装结 构30中可以被省略。除此之外，由于第一晶粒400是通过倒装芯片的方式配 置，故第一晶粒400可以被研磨至任意厚度。另一方面，如图3I所示，第一 晶粒400与导电端子300c共面。因此，封装结构30的厚度能够被有效地减 少，藉此达到封装结构30的微型化。
图4A至图4J是依据本发明一实施例的封装结构的制造方法的剖面示意 图。在一些实施例中，类似于封装结构30的封装结构40(如图4J所示)也 可以是通过如图4A至图4J的方法所制成。值得注意的是，在图4A至图4J 的实施例中，与图3A至图3I类似的元件用相同的标号表示，且省略其描述。
请参照图4A，在载板100上形成多个第一晶粒400。每一第一晶粒400 具有多个凸块402，以与后续形成的其他元件电性连接。载板100被划分为 多个晶粒连接区DR以及多个接触区CR，且接触区CR环绕晶粒连接区DR。 第一晶粒400形成于晶粒连接区DR中。值得注意的是，图4A中所示出的凸 块402的形状仅为例示，而凸块402的具体形状不限于此。在一些实施例中， 凸块402例如是导电柱而并非是如同图4A所示出的球状。举例来说，凸块 402可以是铜柱(copper pillar)，故可以不需要锡银。在一些实施例中，每 一第一晶粒400具有重布线路结构(未示出)埋在第一晶粒400的上表面中， 且第一晶粒400的重布线路结构与凸块402电性连接。在一些实施例中，载 板100与第一晶粒400之间具有芯片贴合膜(dieattached film；DAF；未示 出)，以增强载板100与第一晶粒400彼此之间的黏着力。
请参照图4B，在载板100以及第一晶粒400上形成第一密封体502以密 封第一晶粒400。举例来说，可以先在载板100上形成密封材料(未示出)， 以密封第一晶粒400。接着，将密封材料的厚度减薄，以暴露出凸块402并 形成第一密封体502。在一些实施例中，可以使用化学机械研磨(chemical mechanical polishing；CMP)减薄密封材料的厚度，以使得第一密封体502 的上表面会与凸块402的上表面共面(coplanar)。在一些实施例中，可以进一步微蚀刻凸块402，以使得凸块402的上表面略低于第一密封体502的上 表面，进而增进在后续步骤中形成在凸块402以及第一密封体502上的元件 的黏着力。
请参照图4C，在第一密封体502上形成重布线路层200。重布线路层200 具有第一表面202以及相对于第一表面202的第二表面204。第一表面202 面向第一密封体502。重布线路层200包括第一金属层206、第二金属层208、 第三金属层214、多个导孔栓塞(viaplug)结构210以及介电层212。第一 金属层206、第二金属层208、第三金属层214以及导孔栓塞结构210嵌入于 介电层212中。然而，介电层212暴露出第一金属层206、第二金属层208以及第三金属层214的至少一部分，用以作为电性连接等目的。在一些实施 例中，第一金属层206以及第三金属层214为通过相同的制程所形成的相同 金属层。除此之外，第一金属层206以及第二金属层208位于接触区CR中 而第三金属层214位于晶粒连接区DR中。如图4C所示，第三金属层214与 凸块402电性连接。第一金属层206、第二金属层208以及第三金属层214 通过导孔栓塞结构210而彼此电性耦接。在一些实施例中，第一密封体502 以及重布线路层200的整体厚度约为250微米。值得注意的是，为了简单起 见，在图4C中的重布线路层200的部分金属层并未被示出。然而，在一些替 代性实施例中，除了第一金属层206、第二金属层208以及第三金属层214 之外，重布线路层200可以依据电路设计而包括额外的金属层嵌入于介电层 212中。
请参照图4D，将第一密封体502以及第一晶粒400与载板100分离。举 例来说，可以通过化学蚀刻的方式将第一密封体502以及第一晶粒400与载 板100分离。或者，可以在第一密封体502以及第一晶粒400与载板100之 间配置剥离层(未示出)。因此，可对剥离层施加外部能量(例如紫外线(UV) 激光、可见光或热能)以使得第一密封体502以及第一晶粒400从载板100 剥离。接着，对图4D所示出的结构进行切割或单一化(singulation)制程，以形成如图4E所示的结构。
请参照图4F，在重布线路层200的第二表面204上形成多个第二晶粒600 以及多个无源元件700。第二晶粒600形成于晶粒连接区DR中而无源元件 700形成于接触区CR中。晶粒贴合膜(未示出)可以形成于第二晶粒600以 及重布线路层200之间，以加强第二晶粒600以及重布线路层200之间的黏 着力。第二晶粒600通过导线(wire)602与重布线路层200的第二金属层 208电性连接。无源元件700形成在位于接触区CR的第二金属层208上。
请参照图4G，形成第二密封体800以密封第二晶粒600以及无源元件 700。请参照图4H，将第一密封体502以及第一晶粒400的厚度减薄。举例 来说，可以通过机械研磨(Mechanical grinding)、化学机械研磨 (Chemical-Mechanical Polishing，CMP)、蚀刻或其他合适的制程来将第一 密封体502以及第一晶粒400的厚度减薄。由于第一晶粒400的主动表面是 朝向重布线路层200的第一表面202，故研磨掉的部分实际上为第一晶粒400 的非主动表面。因此，就算部分的非主动表面被移除也不会影响到第一晶粒 400的性能。在一些实施例中，减薄后的第一密封体502以及重布线路层200 的整体厚度约为150微米。
请参照图4I，在第一密封体502中形成多个开口O，以暴露出重布线路 层200的第一表面202。在一些实施例中，开口O对应第一金属层206形成。 开口O可以通过钻孔(drilling)制程形成。举例来说，可以对第一密封体502 执行激光钻孔(laser drilling)或是机械钻孔(mechanical drilling)制程以产 生开口O。由于开口O对应第一金属层206，开口O位于接触区CR中。
请参照图4J，在开口O中填入导电材料以在重布线路层200的第一表面202上形成导电端子300d。由于本实施例的导电端子300d是通过在开口O 中填入导电材料所形成，故导电端子300d可以被称为模塑通孔。除此之外， 在本实施例中，在导电端子300d上形成多个焊球900d，以增进与其他封装 结构的电性连接。焊球900d是通过植球制程形成在被第一密封体502暴露出 的导电端子300d上。
请参照图4J，第一晶粒400以及第二晶粒600分别形成于重布线路层200 的第一表面202以及第二表面204上。因此，具有较厚厚度的基板在封装结 构30中可以被省略。因此，封装结构40的厚度能够被有效地减少，藉此达 到封装结构40的微型化。除此之外，由于图4A至图4J的制程较为简单，故 亦会节省制造成本。
综上所述，在本发明的封装结构中，晶粒形成在重布线路层的两个表面 上。因此，具有较厚厚度的基板在本发明的封装结构中可以被省略。除此之 外，由于至少一个晶粒是通过倒装芯片的方式形成于相对于其他晶粒的另外 一面，故所述至少一个晶粒可以被研磨至任意厚度。另一方面，所述至少一 个晶粒可以与导电端子共面。因此，封装结构的厚度能够被减薄，藉此达到 封装结构的微型化。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属 技术领域中技术人员，在不脱离本发明的精神和范围内，当可作些许的更改 与润饰，故本发明的保护范围当视权利要求所界定者为准。

Claims (10)

1.一种封装结构，包括：
重布线路层，其具有第一表面以及相对于所述第一表面的第二表面；
至少一第一晶粒以及多个导电端子，其中所述第一晶粒以及所述导电端子与所述重布线路层电性连接，且所述第一晶粒以及所述导电端子位于所述重布线路层的所述第一表面上；
第一密封体，密封所述第一晶粒以及所述导电端子，其中所述第一密封体暴露出所述导电端子的至少一部分；
多个焊球，与所述导电端子电性连接，其中所述焊球位于被所述第一密封体暴露出的所述导电端子上；
多个第二晶粒，与所述重布线路层电性连接且位于所述重布线路层的所述第二表面上；以及
第二密封体，密封所述第二晶粒。
2.根据权利要求1所述的封装结构，还包括多个无源元件，所述无源元件位于所述重布线路层的所述第二表面上且对应所述导电端子设置。
3.根据权利要求1所述的封装结构，其中所述第二晶粒彼此堆叠。
4.根据权利要求1所述的封装结构，其中所述第一晶粒以倒装芯片方式与所述重布线路层电性连接。
5.一种封装结构的制造方法，包括：
在载板上形成重布线路层，其中所述重布线路层具有第一表面以及相对于所述第一表面的第二表面，且所述重布线路层的所述第二表面面向所述载板；
在所述重布线路层的所述第一表面上形成多个导电端子；
在所述重布线路层的所述第一表面上形成至少一第一晶粒；
通过第一密封体密封所述第一晶粒；
通过第一密封体密封所述导电端子，其中所述第一密封体暴露出所述导电端子的至少一部分；
将所述重布线路层的所述第二表面与所述载板分离；
在所述重布线路层的所述第二表面上形成多个第二晶粒；
通过第二密封体密封所述第二晶粒；以及
在被所述第一密封体暴露出的所述导电端子上形成多个焊球。
6.一种封装结构的制造方法，包括：
在载板上形成至少一第一晶粒；
通过第一密封体密封所述第一晶粒；
在所述第一密封体上形成重布线路层，其中所述重布线路层具有第一表面以及相对于所述第一表面的第二表面，且所述重布线路层的所述第一表面面向所述第一密封体；
将所述第一密封体以及所述第一晶粒与所述载板分离；
在所述重布线路层的所述第二表面上形成多个第二晶粒；
通过第二密封体密封所述第二晶粒；以及
在所述重布线路层的所述第一表面上形成多个导电端子。
7.根据权利要求6所述的封装结构的制造方法，其中在所述第一表面上形成所述导电端子的步骤包括：
在所述第一密封体中形成多个开口以暴露出所述重布线路层的所述第一表面；以及
在所述开口中形成所述导电端子。
8.根据权利要求6所述的封装结构的制造方法，其中密封所述第一晶粒的步骤在形成所述导电端子的步骤之前执行。
9.根据权利要求6所述的封装结构的制造方法，其中密封所述第一晶粒的步骤包括：
在所述第一晶粒上形成密封材料；以及
减薄所述密封材料的厚度，以暴露出所述第一晶粒的至少一部分。
10.根据权利要求6所述的封装结构的制造方法，其中在分离所述第一密封体以及所述第一晶粒与所述载板之后，还包括：
减薄所述密封材料以及所述第一晶粒的厚度。
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